arm: exynos: change to use clrbits macro instead of readl/writel function

Use setbits/clrbits macro instead of readl/writel function

Signed-off-by Inha Song <[email protected]>

Signed-off-by Minkyu Kang <[email protected]>

Tested-by Przemyslaw Marczak <[email protected]>

---
Changes for v2:
- Coding Style cleanup
- add signed-off-by

 arch/arm/cpu/armv7/exynos/clock.c |   82 +++++++++----------------------------
 1 file changed, 20 insertions(+), 62 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +20 -62

index 5bde9d1..6c589c9 100644
@@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos4_clock *clk =
 		(struct exynos4_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1

@@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos4x12: set the mmc clock */

@@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos4x12_clock *clk =
 		(struct exynos4x12_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1

@@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos5: set the mmc clock */

@@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val;
 
 	/*
 	 * CLK_DIV_FSYS1

@@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 		dev_index -= 2;
 	}
 
-	val = readl(addr);
-	val &= ~(0xff << ((dev_index << 4) + 8));
-	val |= (div & 0xff) << ((dev_index << 4) + 8);
-	writel(val, addr);
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos5: set the mmc clock */

@@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
 	struct exynos5420_clock *clk =
 		(struct exynos5420_clock *)samsung_get_base_clock();
 	unsigned int addr;
-	unsigned int val, shift;
+	unsigned int shift;
 
 	/*
 	 * CLK_DIV_FSYS1

@@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
 	addr = (unsigned int)&clk->div_fsys1;
 	shift = dev_index * 10;
 
-	val = readl(addr);
-	val &= ~(0x3ff << shift);
-	val |= (div & 0x3ff) << shift;
-	writel(val, addr);
+	clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
 }
 
 /* get_lcd_clk: return lcd clock frequency */

@@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK

@@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 
 	/*
 	 * CLK_SRC_LCD0

@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6);
 
 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0

@@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x1;
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xe, 0x1);
 }
 
 void exynos5_set_lcd_clk(void)
 {
 	struct exynos5_clock *clk =
 	    (struct exynos5_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK

@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 
 	/*
 	 * CLK_SRC_LCD0

@@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_disp1_0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_disp1_0);
+	clrsetbits_le32(&clk->src_disp1_0, 0x9, 0x6);
 
 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_disp1);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_disp1);
+	setbits_le32(&clk->gate_ip_disp1, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0

@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x0;
-	writel(cfg, &clk->div_disp1_0);
+	clrbits_le32(&clk->div_disp1_0, 0xf);
 }
 
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_SRC_LCD0

@@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set mipi0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf << 12);
-	cfg |= (0x6 << 12);
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9 << 12, 0x6 << 12);
 
 	/*
 	 * CLK_SRC_MASK_LCD0

@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_MASK		[12]
 	 * set src mask mipi0 0x1: Unmask
 	 */
-	cfg = readl(&clk->src_mask_lcd0);
-	cfg |= (0x1 << 12);
-	writel(cfg, &clk->src_mask_lcd0);
+	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
 
 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for MIPI0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 3;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
 
 	/*
 	 * CLK_DIV_LCD0

@@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set mipi ratio
 	 */
-	cfg &= ~(0xf << 16);
-	cfg |= (0x1 << 16);
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xe << 16, 0x1 << 16);
 }
 
 /*

Use setbits/clrbits macro instead of readl/writel function

Use setbits/clrbits macro instead of readl/writel function

Signed-off-by Inha Song <[email protected]>

Signed-off-by Minkyu Kang <[email protected]>

Tested-by Przemyslaw Marczak <[email protected]>

---
Changes for v2:
- Coding Style cleanup
- add signed-off-by

 arch/arm/cpu/armv7/exynos/clock.c |   82 +++++++++----------------------------
 1 file changed, 20 insertions(+), 62 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c +0 -0

 	/*
 	 * CLK_SRC_LCD0

arch/arm/cpu/armv7/exynos/clock.c +1 -3

 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 }
 
 void exynos5_set_lcd_clk(void)
 {
 	struct exynos5_clock *clk =
 	    (struct exynos5_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK

@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 
 	/*
 	 * CLK_SRC_LCD0

arch/arm/cpu/armv7/exynos/clock.c +2 -7

 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_disp1);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_disp1);
+	setbits_le32(&clk->gate_ip_disp1, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0

@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x0;
-	writel(cfg, &clk->div_disp1_0);
+	clrbits_le32(&clk->div_disp1_0, 0xf);
 }
 
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_SRC_LCD0

arch/arm/cpu/armv7/exynos/clock.c +2 -6

 	/*
 	 * CLK_SRC_MASK_LCD0

@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_MASK		[12]
 	 * set src mask mipi0 0x1: Unmask
 	 */
-	cfg = readl(&clk->src_mask_lcd0);
-	cfg |= (0x1 << 12);
-	writel(cfg, &clk->src_mask_lcd0);
+	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
 
 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for MIPI0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 3;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
 
 	/*
 	 * CLK_DIV_LCD0

Quoted 12 lines · Inha Song

Use setbits/clrbits macro instead of readl/writel function

Signed-off-by Inha Song <[email protected]>

Signed-off-by Minkyu Kang <[email protected]>

Tested-by Przemyslaw Marczak <[email protected]>

---
Changes for v2:
- Coding Style cleanup
- add signed-off-by

 arch/arm/cpu/armv7/exynos/clock.c |   82 +++++++++----------------------------
 1 file changed, 20 insertions(+), 62 deletions(-)

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_lcd_clk(void) · line 1073

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6);

0x9? It seems to be 0xf.

Quoted 13 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -3

 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
 

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_lcd_clk(void) · line 1097

Quoted 10 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -3

 	/*
 	 * CLK_DIV_LCD0

@@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x1;
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xe, 0x1);

ditto.

Quoted 20 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 }
 
 void exynos5_set_lcd_clk(void)
 {
 	struct exynos5_clock *clk =
 	    (struct exynos5_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK

@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 

arch/arm/cpu/armv7/exynos/clock.c void exynos5_set_lcd_clk(void) · line 1125

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_disp1_0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_disp1_0);
+	clrsetbits_le32(&clk->src_disp1_0, 0x9, 0x6);

ditto.

Quoted 31 lines

arch/arm/cpu/armv7/exynos/clock.c +2 -7

 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_disp1);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_disp1);
+	setbits_le32(&clk->gate_ip_disp1, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0

@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x0;
-	writel(cfg, &clk->div_disp1_0);
+	clrbits_le32(&clk->div_disp1_0, 0xf);
 }
 
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_mipi_clk(void) · line 1165

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set mipi0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf << 12);
-	cfg |= (0x6 << 12);
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9 << 12, 0x6 << 12);

ditto.

Quoted 24 lines

arch/arm/cpu/armv7/exynos/clock.c +2 -6

 	/*
 	 * CLK_SRC_MASK_LCD0

@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_MASK		[12]
 	 * set src mask mipi0 0x1: Unmask
 	 */
-	cfg = readl(&clk->src_mask_lcd0);
-	cfg |= (0x1 << 12);
-	writel(cfg, &clk->src_mask_lcd0);
+	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
 
 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for MIPI0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 3;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
 

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_mipi_clk(void) · line 1199

Quoted 10 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -3

 	/*
 	 * CLK_DIV_LCD0

@@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set mipi ratio
 	 */
-	cfg &= ~(0xf << 16);
-	cfg |= (0x1 << 16);
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xe << 16, 0x1 << 16);

ditto.

Review void exynos4_set_mipi_clk(void) · line 1202

Quoted 5 lines

(quoted diff) +0 -0

 }
 
 /*

Thanks,
Minkyu Kang.

Hi,

Quoted 14 lines · On Thu, 16 Jan 2014 16:50:37 +0900 Minkyu Kang <[email protected]> wrote:

Quoted 12 lines · Inha Song

Use setbits/clrbits macro instead of readl/writel function

Signed-off-by Inha Song <[email protected]>

Signed-off-by Minkyu Kang <[email protected]>

Tested-by Przemyslaw Marczak <[email protected]>

---
Changes for v2:
- Coding Style cleanup
- add signed-off-by

 arch/arm/cpu/armv7/exynos/clock.c |   82 +++++++++----------------------------
 1 file changed, 20 insertions(+), 62 deletions(-)

Quoted 13 lines

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_lcd_clk(void) · line 1073

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6);

0x9? It seems to be 0xf.

I have set the only bit that must be cleared.

In case, I want to set src_lcd0 register to 0x6(b0110).
Therefore, do not need to clear a bit of the second and third. (don't care bits)

clrsetbits_le32(addr, 0x9, 0x6) == clrsetbits_le32(addr, 0xf, 0x6) ( reg &= ~b1xx1, reg |= b0110 == reg &= ~b1111, reg |= b0110 )

Do you think any way is better?

Quoted 13 lines

Quoted 13 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -3

 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
 

Quoted 12 lines

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_lcd_clk(void) · line 1097

Quoted 10 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -3

 	/*
 	 * CLK_DIV_LCD0

@@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x1;
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xe, 0x1);

ditto.

Ditto,

Quoted 20 lines

Quoted 20 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 }
 
 void exynos5_set_lcd_clk(void)
 {
 	struct exynos5_clock *clk =
 	    (struct exynos5_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 
 	/*
 	 * CLK_GATE_BLOCK

@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_LCD1	[5]
 	 * CLK_GPS	[7]
 	 */
-	cfg = readl(&clk->gate_block);
-	cfg |= 1 << 4;
-	writel(cfg, &clk->gate_block);
+	setbits_le32(&clk->gate_block, 1 << 4);
 

Quoted 13 lines

arch/arm/cpu/armv7/exynos/clock.c void exynos5_set_lcd_clk(void) · line 1125

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_disp1_0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_disp1_0);
+	clrsetbits_le32(&clk->src_disp1_0, 0x9, 0x6);

ditto.

Ditto,

Quoted 31 lines

Quoted 31 lines

arch/arm/cpu/armv7/exynos/clock.c +2 -7

 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for FIMD0
 	 */
-	cfg = readl(&clk->gate_ip_disp1);
-	cfg |= 1 << 0;
-	writel(cfg, &clk->gate_ip_disp1);
+	setbits_le32(&clk->gate_ip_disp1, 1 << 0);
 
 	/*
 	 * CLK_DIV_LCD0

@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set fimd ratio
 	 */
-	cfg &= ~(0xf);
-	cfg |= 0x0;
-	writel(cfg, &clk->div_disp1_0);
+	clrbits_le32(&clk->div_disp1_0, 0xf);
 }
 
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
 	    (struct exynos4_clock *)samsung_get_base_clock();
-	unsigned int cfg = 0;
 

Quoted 13 lines

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_mipi_clk(void) · line 1165

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set mipi0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf << 12);
-	cfg |= (0x6 << 12);
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9 << 12, 0x6 << 12);

ditto.

Ditto,

Quoted 24 lines

Quoted 24 lines

arch/arm/cpu/armv7/exynos/clock.c +2 -6

 	/*
 	 * CLK_SRC_MASK_LCD0

@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_MASK		[12]
 	 * set src mask mipi0 0x1: Unmask
 	 */
-	cfg = readl(&clk->src_mask_lcd0);
-	cfg |= (0x1 << 12);
-	writel(cfg, &clk->src_mask_lcd0);
+	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
 
 	/*
 	 * CLK_GATE_IP_LCD0

@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
 	 * CLK_PPMULCD0		[5]
 	 * Gating all clocks for MIPI0
 	 */
-	cfg = readl(&clk->gate_ip_lcd0);
-	cfg |= 1 << 3;
-	writel(cfg, &clk->gate_ip_lcd0);
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
 

Quoted 12 lines

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_mipi_clk(void) · line 1199

Quoted 10 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -3

 	/*
 	 * CLK_DIV_LCD0

@@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
 	 * MIPI0_PRE_RATIO	[23:20]
 	 * set mipi ratio
 	 */
-	cfg &= ~(0xf << 16);
-	cfg |= (0x1 << 16);
-	writel(cfg, &clk->div_lcd0);
+	clrsetbits_le32(&clk->div_lcd0, 0xe << 16, 0x1 << 16);

ditto.

Ditto,

Quoted 8 lines

Review void exynos4_set_mipi_clk(void) · line 1202

Quoted 5 lines

(quoted diff) +0 -0

 }
 
 /*

Thanks,
Minkyu Kang.

Do you think any way is better?
e.g) clrsetbits_le32(addr, 0x9, 0x6) vs clrsetbits_le32(addr, 0xf, 0x6)

Thanks,

Hi,

Quoted 14 lines · On Thu, 16 Jan 2014 16:50:37 +0900 Minkyu Kang <[email protected]> wrote:

Quoted 12 lines · Inha Song

Use setbits/clrbits macro instead of readl/writel function

Signed-off-by Inha Song <[email protected]>

Signed-off-by Minkyu Kang <[email protected]>

Tested-by Przemyslaw Marczak <[email protected]>

---
Changes for v2:
- Coding Style cleanup
- add signed-off-by

 arch/arm/cpu/armv7/exynos/clock.c |   82 +++++++++----------------------------
 1 file changed, 20 insertions(+), 62 deletions(-)

Quoted 13 lines

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_lcd_clk(void) · line 1073

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6);

0x9? It seems to be 0xf.

I have set the only bit that must be cleared.

In case, I want to set src_lcd0 register to 0x6(b0110).
Therefore, do not need to clear a bit of the second and third. (don't care bits)

clrsetbits_le32(addr, 0x9, 0x6) == clrsetbits_le32(addr, 0xf, 0x6) ( reg &= ~b1xx1, reg |= b0110 == reg &= ~b1111, reg |= b0110 )

Do you think any way is better?

Quoted 42 lines · Inha Song

Hi,

Quoted 14 lines · On Thu, 16 Jan 2014 16:50:37 +0900 Minkyu Kang <[email protected]> wrote:

Quoted 12 lines · Inha Song

Use setbits/clrbits macro instead of readl/writel function

Signed-off-by Inha Song <[email protected]>

Signed-off-by Minkyu Kang <[email protected]>

Tested-by Przemyslaw Marczak <[email protected]>

---
Changes for v2:
- Coding Style cleanup
- add signed-off-by

 arch/arm/cpu/armv7/exynos/clock.c |   82 +++++++++----------------------------
 1 file changed, 20 insertions(+), 62 deletions(-)

Quoted 13 lines

arch/arm/cpu/armv7/exynos/clock.c void exynos4_set_lcd_clk(void) · line 1073

Quoted 11 lines

arch/arm/cpu/armv7/exynos/clock.c +1 -4

 	/*
 	 * CLK_SRC_LCD0

@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
 	 * MIPI0_SEL		[12:15]
 	 * set lcd0 src clock 0x6: SCLK_MPLL
 	 */
-	cfg = readl(&clk->src_lcd0);
-	cfg &= ~(0xf);
-	cfg |= 0x6;
-	writel(cfg, &clk->src_lcd0);
+	clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6);

0x9? It seems to be 0xf.

I have set the only bit that must be cleared.

In case, I want to set src_lcd0 register to 0x6(b0110).
Therefore, do not need to clear a bit of the second and third. (don't care bits)

clrsetbits_le32(addr, 0x9, 0x6) == clrsetbits_le32(addr, 0xf, 0x6) ( reg &= ~b1xx1, reg |= b0110 == reg &= ~b1111, reg |= b0110 )

Quoted 2 lines

Do you think any way is better?

No..
0xF is mask of FIMD0_SEL that is 4 bits.
The mask value never be changed.

Thanks,
Minkyu Kang.
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