mx6: Revert "mx6: soc: Disable VDDPU regulator"

PATCH New Fabio Estevam 5 participants 11 messages Jan 16, 2014

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Fabio Estevam

author

2014-01-16 12:57 UTC #0 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now.

Reported-by Otavio Salvador <[email protected]>

Reported-by Pierre Aubert <[email protected]>

Signed-off-by Fabio Estevam <[email protected]>

---
Stefano,

I will provide a proper fix after 2014.01 is out, but to allow people to use mainline U-boot with FSL kernels, it would be better to revert it for now.

Thanks

 arch/arm/cpu/armv7/mx6/soc.c             | 41 --------------------------------
 arch/arm/include/asm/arch-mx6/crm_regs.h |  1 -
 arch/arm/include/asm/arch-mx6/imx-regs.h | 23 ------------------
 3 files changed, 65 deletions(-)

arch/arm/cpu/armv7/mx6/soc.c +0 ~~-41~~

index 009a644..0208cba 100644
@@ -19,8 +19,6 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
-#define VDDPU_MASK	(0x1f << 9)
-
 enum ldo_reg {
 	LDO_ARM,
 	LDO_SOC,

@@ -179,50 +177,11 @@ static void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog2->wmcr);
 }
 
-static void imx_set_vddpu_power_down(void)
-{
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
-
-	u32 reg;
-
-	/*
-	 * Disable the brown out detection since we are going to be
-	 * disabling the LDO.
-	 */
-	reg = readl(&anatop->ana_misc2);
-	reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
-	writel(reg, &anatop->ana_misc2);
-
-	/* need to power down xPU in GPC before turning off PU LDO */
-	reg = readl(&gpc->gpu_ctrl);
-	writel(reg | 0x1, &gpc->gpu_ctrl);
-
-	reg = readl(&gpc->ctrl);
-	writel(reg | 0x1, &gpc->ctrl);
-	while (readl(&gpc->ctrl) & 0x1)
-		;
-
-	/* Mask the ANATOP brown out interrupt in the GPC. */
-	reg = readl(&gpc->imr4);
-	reg |= 0x80000000;
-	writel(reg, &gpc->imr4);
-
-	/* disable VDDPU */
-	writel(VDDPU_MASK, &anatop->reg_core_clr);
-
-	/* Clear the BO interrupt in the ANATOP. */
-	reg = readl(&anatop->ana_misc1);
-	reg |= 0x80000000;
-	writel(reg, &anatop->ana_misc1);
-}
-
 int arch_cpu_init(void)
 {
 	init_aips();
 
 	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
-	imx_set_vddpu_power_down();
 
 #ifdef CONFIG_APBH_DMA
 	/* Start APBH DMA */

arch/arm/include/asm/arch-mx6/crm_regs.h +0 -1

index aede126..7202073 100644
@@ -890,5 +890,4 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
 	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
 
-#define ANADIG_ANA_MISC2_REG1_BO_EN	(1 << 13)
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

arch/arm/include/asm/arch-mx6/imx-regs.h +0 ~~-23~~

index 7f89865..f2ad6e9 100644
@@ -663,28 +663,5 @@ struct wdog_regs {
 	u16	wmcr;	/* Miscellaneous Control */
 };
 
-struct gpc_regs {
-	u32	ctrl;		/* 0x000 */
-	u32	pgr;		/* 0x004 */
-	u32	imr1;		/* 0x008 */
-	u32	imr2;		/* 0x00c */
-	u32	imr3;		/* 0x010 */
-	u32	imr4;		/* 0x014 */
-	u32	isr1;		/* 0x018 */
-	u32	isr2;		/* 0x01c */
-	u32	isr3;		/* 0x020 */
-	u32	isr4;		/* 0x024 */
-	u32	reserved1[0x86];
-	u32	gpu_ctrl;	/* 0x260 */
-	u32	gpu_pupscr;	/* 0x264 */
-	u32	gpu_pdnscr;	/* 0x268 */
-	u32	gpu_sr;		/* 0x26c */
-	u32	reserved2[0xc];
-	u32	cpu_ctrl;	/* 0x2a0 */
-	u32	cpu_pupscr;	/* 0x2a4 */
-	u32	cpu_pdnscr;	/* 0x2a8 */
-	u32	cpu_sr;		/* 0x2ac */
-};
-
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

Signature · 1 line

1.8.1.2

Stefano Babic

2014-01-16 13:06 UTC #1 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Hi Fabio, hi Albert,

Quoted 12 lines · Fabio Estevam

Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now.
Reported-by Otavio Salvador <[email protected]>
Reported-by Pierre Aubert <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
Stefano,
I will provide a proper fix after 2014.01 is out, but to allow people to use mainline U-boot with FSL kernels, it would be better to revert it for now.

Anyway, is it the fix known ? Should it be done in U-Boot or FSL-3.10 kernel ?

Quoted 1 line

Thanks

Albert, commit 022298278 generate trouble to several users. There is no drawbacks for U-Boot to revert it. Can you directly pick it up or do you prefer I send a PR ?

Thanks,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Fabio Estevam

reviewer

2014-01-16 13:21 UTC #2 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Hi Stefano,

Quoted 2 lines · Stefano Babic

Anyway, is it the fix known ? Should it be done in U-Boot or FSL-3.10 kernel ?

I have just started debugging, so I am not sure at this point.

Internal FSL U-boot also disables VDDPU, but it does not cause the hang when GPU driver is loaded.

Regards,

Fabio Estevam

Otavio Salvador

2014-01-16 15:33 UTC #3 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Hello Fabio and Stefano,

Quoted 11 lines · Fabio Estevam

Quoted 2 lines · Stefano Babic
Anyway, is it the fix known ? Should it be done in U-Boot or FSL-3.10 kernel ?
I have just started debugging, so I am not sure at this point.
Internal FSL U-boot also disables VDDPU, but it does not cause the hang when GPU driver is loaded.

As I said the SabreSD case seems to be solvable adding support for the PMIC. I did it for our customer board and it works however it does not solve the case where the board does not have a PMIC. One of our customer is in that case and for now I don't know a solution for it.

The PMIC way that has been done in FSL fork is quite ugly as it does not use the PMIC API but can be used as a base for it.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

Fabio Estevam

reviewer

2014-01-16 15:42 UTC #4 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Quoted 1 line · Otavio Salvador

As I said the SabreSD case seems to be solvable adding support for the PMIC.

Have you really tried it? I tried adding PMIC support on sabresd and it did overcome the GPU hang.

Quoted 1 line

I did it for our customer board and it works however it does not solve the

It worked for you probably because you used the ldo bypass mode.

Regards,

Fabio Estevam

reviewer

2014-01-16 15:43 UTC #5 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Quoted 7 lines · Fabio Estevam

Quoted 1 line · Otavio Salvador
As I said the SabreSD case seems to be solvable adding support for the PMIC.
Have you really tried it? I tried adding PMIC support on sabresd and it did overcome the GPU hang.

I meant 'it did not overcome the GPU hang".

Otavio Salvador

2014-01-16 15:50 UTC #6 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

In reply to Fabio Estevam

Quoted 6 lines · Fabio Estevam

Quoted 1 line · Otavio Salvador
As I said the SabreSD case seems to be solvable adding support for the
PMIC.

Quoted 8 lines

Have you really tried it? I tried adding PMIC support on sabresd and it did overcome the GPU hang.
Quoted 1 line
I did it for our customer board and it works however it does not solve
the
It worked for you probably because you used the ldo bypass mode.

Yes; I did the bypass mode.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

Fabio Estevam

reviewer

2014-01-16 16:01 UTC #7 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Quoted 4 lines · Otavio Salvador

Quoted 1 line
It worked for you probably because you used the ldo bypass mode.
Yes; I did the bypass mode.

We currently don't do LDO bypass mode in mainline U-boot. We do it in FSL U-boot.

With LDO bypass, lower VDDARM and VDDSOC voltages can be supplied as per the mx6 datasheet.

I just measured with the scope and the VDDARM/SOC voltages supplied by the 3.10 FSL kernel are below the minimum for the LDO enabled case. So setting LDO bypass in U-boot 'fixes' the issue.

We can implement LDO bypass after 2014.01 is out, but for this release let's just revert the VDDPU disable patch.

Do you agree?

Regards,

Fabio Estevam

Otavio Salvador

2014-01-16 16:06 UTC #8 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

Quoted 14 lines · Fabio Estevam

Quoted 4 lines · Otavio Salvador
Quoted 1 line
It worked for you probably because you used the ldo bypass mode.
Yes; I did the bypass mode.
We currently don't do LDO bypass mode in mainline U-boot. We do it in FSL U-boot.
With LDO bypass, lower VDDARM and VDDSOC voltages can be supplied as per the mx6 datasheet.

Quoted 9 lines

I just measured with the scope and the VDDARM/SOC voltages supplied by the 3.10 FSL kernel are below the minimum for the LDO enabled case. So setting LDO bypass in U-boot 'fixes' the issue.
We can implement LDO bypass after 2014.01 is out, but for this release let's just revert the VDDPU disable patch.
Do you agree?

Yes I do.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

Stefano Babic

2014-01-16 16:08 UTC #9 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

In reply to Fabio Estevam

Hi Fabio,

Quoted 14 lines · Fabio Estevam

Quoted 4 lines · Otavio Salvador
Quoted 1 line
It worked for you probably because you used the ldo bypass mode.
Yes; I did the bypass mode.
We currently don't do LDO bypass mode in mainline U-boot. We do it in FSL U-boot.
With LDO bypass, lower VDDARM and VDDSOC voltages can be supplied as per the mx6 datasheet.

Quoted 9 lines

I just measured with the scope and the VDDARM/SOC voltages supplied by the 3.10 FSL kernel are below the minimum for the LDO enabled case. So setting LDO bypass in U-boot 'fixes' the issue.
We can implement LDO bypass after 2014.01 is out, but for this release let's just revert the VDDPU disable patch.
Do you agree?

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Pierre AUBERT

2014-01-16 16:12 UTC #10 lore raw

PATCH 1/1 mx6: Revert "mx6: soc: Disable VDDPU regulator"

In reply to Fabio Estevam

Le 16/01/2014 17:01, Fabio Estevam a ?crit :

Quoted 12 lines

Quoted 3 lines · Otavio Salvador
Quoted 1 line
It worked for you probably because you used the ldo bypass mode.
Yes; I did the bypass mode.
We currently don't do LDO bypass mode in mainline U-boot. We do it in FSL U-boot.
With LDO bypass, lower VDDARM and VDDSOC voltages can be supplied as per the mx6 datasheet.

Quoted 8 lines

I just measured with the scope and the VDDARM/SOC voltages supplied by the 3.10 FSL kernel are below the minimum for the LDO enabled case. So setting LDO bypass in U-boot 'fixes' the issue.
We can implement LDO bypass after 2014.01 is out, but for this release let's just revert the VDDPU disable patch.
Do you agree?

Quoted 4 lines

Regards,
Fabio Estevam