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mtd: spi-nor: add a new framework for SPI NOR

PATCH Superseded Huang Shijie 5 participants 22 messages Dec 25, 2013 – Jan 21, 2014

Subsystems (4)

v4 of 5 Superseded Latest is v5 →

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#0 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

1.) Why add a new framework for SPI NOR?
The SPI-NOR controller such as Freescale's Quadspi controller is working in a different way from the SPI bus. It should knows the NOR commands to find the right LUT sequence. Unfortunately, the current code can not meet this requirement.

2.) How does this patch set do?
This patch set adds a new spi-nor layer.
Before this patch, the layer is like:

                   MTD
         ------------------------
                  m25p80
         ------------------------
	       spi bus driver
         ------------------------
	        SPI NOR chip

After this patch, the layer is like:

                   MTD
         ------------------------
                  spi-nor
         ------------------------
                  m25p80
         ------------------------
	       spi bus driver
         ------------------------
	       SPI NOR chip

With the spi-nor controller driver(Freescale Quadspi), it looks like:

                   MTD
         ------------------------
                  spi-nor
         ------------------------
                fsl-quadspi
         ------------------------
	       SPI NOR chip

3.) more details
This patch set adds a new data structrue spi_nor{}, clones most the common
code to spi-nor.c. Add spi_nor_xfer_cfg {} for the fundamental primitives:
read_xfer/write_xfer.

Make the m25p80.c/fsl_quaspi.c use the new APIs.

4.) Change log:
v3 --> v4:
[1] move the wait_till_ready to the @read hook.
[2] convert to linux-doc style comment.
[3] remove the some DT property for QuadSPI driver, such as "fsl,nor-size".
[4] others

v2 --> v3:
[1] add prepare/unprepare hooks for spi_nor{}.
[2] add a new "priv" field for spi_nor{}.
[3] add the Freescale Quadspi driver which supports the Quad read by default.

v1 --> v2:

	[1] follow Angus's advice, add more hooks and data structrures.
	[2] others.

Huang Shijie (7):
mtd: spi-nor: copy the SPI NOR commands to a new header file
mtd: spi-nor: add the basic data structures
mtd: spi-nor: add the framework for SPI NOR
mtd: m25p80: use the SPI nor framework
mtd: spi-nor: add a helper to find the spi_device_id
Documentation: add the binding file for Freescale QuadSPI driver
mtd: spi-nor: Add Freescale QuadSPI driver

 .../devicetree/bindings/mtd/fsl-quadspi.txt        |   26 +
 drivers/mtd/Kconfig                                |    2 +
 drivers/mtd/Makefile                               |    1 +
 drivers/mtd/devices/Kconfig                        |    2 +-
 drivers/mtd/devices/m25p80.c                       | 1275 ++------------------
 drivers/mtd/spi-nor/Kconfig                        |   12 +
 drivers/mtd/spi-nor/Makefile                       |    2 +
 drivers/mtd/spi-nor/fsl-quadspi.c                  |  957 +++++++++++++++
 drivers/mtd/spi-nor/spi-nor.c                      | 1093 +++++++++++++++++
 include/linux/mtd/spi-nor.h                        |  194 +++
 10 files changed, 2387 insertions(+), 1177 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
 create mode 100644 drivers/mtd/spi-nor/Kconfig
 create mode 100644 drivers/mtd/spi-nor/Makefile
 create mode 100644 drivers/mtd/spi-nor/fsl-quadspi.c
 create mode 100644 drivers/mtd/spi-nor/spi-nor.c
 create mode 100644 include/linux/mtd/spi-nor.h
Signature · 1 line
1.7.2.rc3
#1 lore raw

PATCH v4 1/7 mtd: spi-nor: copy the SPI NOR commands to a new header file

This patch adds a new header :spi-nor.h,
and copies all the SPI NOR commands and relative macros into this new header.

This hearder can be used by the m25p80.c and other spi-nor controller, such as Freescale's Quadspi.

---
 include/linux/mtd/spi-nor.h |   53 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 53 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/mtd/spi-nor.h
include/linux/mtd/spi-nor.h new file +53 -0
new file mode 100644
index 0000000..ab2ea1e
@@ -0,0 +1,53 @@
+#ifndef __LINUX_MTD_SPI_NOR_H
+#define __LINUX_MTD_SPI_NOR_H
+
+/* Flash opcodes. */
+#define	OPCODE_WREN		0x06	/* Write enable */
+#define	OPCODE_RDSR		0x05	/* Read status register */
+#define	OPCODE_WRSR		0x01	/* Write status register 1 byte */
+#define	OPCODE_NORM_READ	0x03	/* Read data bytes (low frequency) */
+#define	OPCODE_FAST_READ	0x0b	/* Read data bytes (high frequency) */
+#define	OPCODE_QUAD_READ        0x6b    /* Read data bytes */
+#define	OPCODE_PP		0x02	/* Page program (up to 256 bytes) */
+#define	OPCODE_BE_4K		0x20	/* Erase 4KiB block */
+#define	OPCODE_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
+#define	OPCODE_BE_32K		0x52	/* Erase 32KiB block */
+#define	OPCODE_CHIP_ERASE	0xc7	/* Erase whole flash chip */
+#define	OPCODE_SE		0xd8	/* Sector erase (usually 64KiB) */
+#define	OPCODE_RDID		0x9f	/* Read JEDEC ID */
+#define	OPCODE_RDCR             0x35    /* Read configuration register */
+
+/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+#define	OPCODE_NORM_READ_4B	0x13	/* Read data bytes (low frequency) */
+#define	OPCODE_FAST_READ_4B	0x0c	/* Read data bytes (high frequency) */
+#define	OPCODE_QUAD_READ_4B	0x6c    /* Read data bytes */
+#define	OPCODE_PP_4B		0x12	/* Page program (up to 256 bytes) */
+#define	OPCODE_SE_4B		0xdc	/* Sector erase (usually 64KiB) */
+
+/* Used for SST flashes only. */
+#define	OPCODE_BP		0x02	/* Byte program */
+#define	OPCODE_WRDI		0x04	/* Write disable */
+#define	OPCODE_AAI_WP		0xad	/* Auto address increment word program */
+
+/* Used for Macronix and Winbond flashes. */
+#define	OPCODE_EN4B		0xb7	/* Enter 4-byte mode */
+#define	OPCODE_EX4B		0xe9	/* Exit 4-byte mode */
+
+/* Used for Spansion flashes only. */
+#define	OPCODE_BRWR		0x17	/* Bank register write */
+
+/* Status Register bits. */
+#define	SR_WIP			1	/* Write in progress */
+#define	SR_WEL			2	/* Write enable latch */
+/* meaning of other SR_* bits may differ between vendors */
+#define	SR_BP0			4	/* Block protect 0 */
+#define	SR_BP1			8	/* Block protect 1 */
+#define	SR_BP2			0x10	/* Block protect 2 */
+#define	SR_SRWD			0x80	/* SR write protect */
+
+#define SR_QUAD_EN_MX           0x40    /* Macronix Quad I/O */
+
+/* Configuration Register bits. */
+#define CR_QUAD_EN_SPAN		0x2     /* Spansion Quad I/O */
+
+#endif
Signature · 1 line
1.7.2.rc3
#2 lore raw

PATCH v4 2/7 mtd: spi-nor: add the basic data structures

In reply to Huang Shijie

The spi_nor{} is cloned from the m25p{}.
The spi_nor{} can be used by both the m25p80 and spi-nor controller.

We also add the spi_nor_xfer_cfg{} which can be used by the two fundamental primitives: read_xfer/write_xfer.

1) the hooks for spi_nor{}:
@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.

2) Add a new field sst_write_second for the SST NOR write.

---
 include/linux/mtd/spi-nor.h |  109 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 109 insertions(+), 0 deletions(-)
include/linux/mtd/spi-nor.h +109 -0
index ab2ea1e..f3d04ba 100644
@@ -50,4 +50,113 @@
 /* Configuration Register bits. */
 #define CR_QUAD_EN_SPAN		0x2     /* Spansion Quad I/O */
 
+enum read_mode {
+	SPI_NOR_NORMAL = 0,
+	SPI_NOR_FAST,
+	SPI_NOR_QUAD,
+};
+
+/**
+ * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
+ * @wren:		command for "Write Enable", or 0x00 for not required
+ * @cmd:		command for operation
+ * @cmd_pins:		number of pins to send @cmd (1, 2, 4)
+ * @addr:		address for operation
+ * @addr_pins:		number of pins to send @addr (1, 2, 4)
+ * @addr_width:		number of address bytes
+ *			(3,4, or 0 for address not required)
+ * @mode:		mode data
+ * @mode_pins:		number of pins to send @mode (1, 2, 4)
+ * @mode_cycles:	number of mode cycles (0 for mode not required)
+ * @dummy_cycles:	number of dummy cycles (0 for dummy not required)
+ */
+struct spi_nor_xfer_cfg {
+	u8		wren;
+	u8		cmd;
+	u8		cmd_pins;
+	u32		addr;
+	u8		addr_pins;
+	u8		addr_width;
+	u8		mode;
+	u8		mode_pins;
+	u8		mode_cycles;
+	u8		dummy_cycles;
+};
+
+#define	SPI_NOR_MAX_CMD_SIZE	8
+enum spi_nor_ops {
+	SPI_NOR_OPS_READ = 0,
+	SPI_NOR_OPS_WRITE,
+	SPI_NOR_OPS_ERASE,
+	SPI_NOR_OPS_LOCK,
+	SPI_NOR_OPS_UNLOCK,
+};
+
+/**
+ * struct spi_nor - Structure for defining a the SPI NOR layer
+ * @mtd:		point to a mtd_info structure
+ * @lock:		the lock for the read/write/erase/lock/unlock operations
+ * @dev:		point to a spi device, or a spi nor controller device.
+ * @page_size:		the page size of the SPI NOR
+ * @addr_width:		number of address bytes
+ * @erase_opcode:	the opcode for erasing a sector
+ * @read_opcode:	the read opcode
+ * @read_dummy:		the dummy needed by the read operation
+ * @program_opcode:	the program opcode
+ * @flash_read:		the mode of the read
+ * @sst_write_second:	used by the SST write operation
+ * @cfg:		used by the read_xfer/write_xfer
+ * @cmd_buf:		used by the write_reg
+ * @prepare:		[OPTIONAL] do some preparations for the
+ *			read/write/erase/lock/unlock operations
+ * @unprepare:		[OPTIONAL] do some post work after the
+ *			read/write/erase/lock/unlock operations
+ * @read_xfer:		[OPTIONAL] the read fundamental primitive
+ * @write_xfer:		[OPTIONAL] the writefundamental primitive
+ * @read_reg:		[DRIVER-SPECIFIC] read out the register
+ * @write_reg:		[DRIVER-SPECIFIC] write data to the register
+ * @read_id:		[REPLACEABLE] read out the ID data, and find
+ *			the proper spi_device_id
+ * @wait_till_ready:	[REPLACEABLE] wait till the NOR becomes ready
+ * @read:		[DRIVER-SPECIFIC] read data from the SPI NOR
+ * @write:		[DRIVER-SPECIFIC] write data to the SPI NOR
+ * @erase:		[DRIVER-SPECIFIC] erase a sector of the SPI NOR
+ *			at the offset @offs
+ * @priv:		the private data
+ */
+struct spi_nor {
+	struct mtd_info		*mtd;
+	struct mutex		lock;
+	struct device		*dev;
+	u32			page_size;
+	u8			addr_width;
+	u8			erase_opcode;
+	u8			read_opcode;
+	u8			read_dummy;
+	u8			program_opcode;
+	enum read_mode		flash_read;
+	bool			sst_write_second;
+	struct spi_nor_xfer_cfg	cfg;
+	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];
+
+	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+	int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
+			 u8 *buf, size_t len);
+	int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
+			  u8 *buf, size_t len);
+	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
+			int write_enable);
+	const struct spi_device_id *(*read_id)(struct spi_nor *nor);
+	int (*wait_till_ready)(struct spi_nor *nor);
+
+	int (*read)(struct spi_nor *nor, loff_t from,
+			size_t len, size_t *retlen, u_char *read_buf);
+	void (*write)(struct spi_nor *nor, loff_t to,
+			size_t len, size_t *retlen, const u_char *write_buf);
+	int (*erase)(struct spi_nor *nor, loff_t offs);
+
+	void *priv;
+};
 #endif
Signature · 1 line
1.7.2.rc3
#3 lore raw

PATCH v4 3/7 mtd: spi-nor: add the framework for SPI NOR

In reply to Huang Shijie

This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer.

Before this patch, the layer is like:

                   MTD
         ------------------------
                  m25p80
         ------------------------
	       spi bus driver
         ------------------------
	        SPI NOR chip

After this patch, the layer is like:

                   MTD
         ------------------------
                  spi-nor
         ------------------------
                  m25p80
         ------------------------
	       spi bus driver
         ------------------------
	       SPI NOR chip

With the spi-nor controller driver(Freescale Quadspi), it looks like:

                   MTD
         ------------------------
                  spi-nor
         ------------------------
                fsl-quadspi
         ------------------------
	       SPI NOR chip

New APIs:
spi_nor_scan: used to scan a spi-nor flash.

---
 drivers/mtd/Kconfig           |    2 +
 drivers/mtd/Makefile          |    1 +
 drivers/mtd/spi-nor/Kconfig   |    6 +
 drivers/mtd/spi-nor/Makefile  |    1 +
 drivers/mtd/spi-nor/spi-nor.c | 1081 +++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h   |   20 +
 6 files changed, 1111 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/spi-nor/Kconfig
 create mode 100644 drivers/mtd/spi-nor/Makefile
 create mode 100644 drivers/mtd/spi-nor/spi-nor.c
drivers/mtd/Kconfig +2 -0
index 5fab4e6e..8adb5af 100644
@@ -320,6 +320,8 @@ source "drivers/mtd/onenand/Kconfig"
 
 source "drivers/mtd/lpddr/Kconfig"
 
+source "drivers/mtd/spi-nor/Kconfig"
+
 source "drivers/mtd/ubi/Kconfig"
 
 endif # MTD
drivers/mtd/Makefile +1 -0
index 4cfb31e..40fd153 100644
@@ -32,4 +32,5 @@ inftl-objs		:= inftlcore.o inftlmount.o
 
 obj-y		+= chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
 
+obj-$(CONFIG_MTD_SPI_NOR_BASE)	+= spi-nor/
 obj-$(CONFIG_MTD_UBI)		+= ubi/
drivers/mtd/spi-nor/Kconfig new file +6 -0
new file mode 100644
index 0000000..41591af
@@ -0,0 +1,6 @@
+config MTD_SPI_NOR_BASE
+	bool "the framework for SPI-NOR support"
+	depends on MTD
+	help
+	  This is the framework for the SPI NOR which can be used by the SPI
+	  device drivers and the SPI-NOR device driver.
drivers/mtd/spi-nor/Makefile new file +1 -0
new file mode 100644
index 0000000..7dfe1f9
@@ -0,0 +1 @@
+obj-$(CONFIG_MTD_SPI_NOR_BASE)	+= spi-nor.o
drivers/mtd/spi-nor/spi-nor.c new file +1081 -0

1,081 lines not on this page · raw message

include/linux/mtd/spi-nor.h +20 -0
index f3d04ba..06bd096 100644
@@ -159,4 +159,24 @@ struct spi_nor {
 
 	void *priv;
 };
+
+/**
+ * spi_nor_scan() - scan the SPI NOR
+ * @nor:	the spi_nor structure
+ * @id:		the spi_device_id provided by the driver
+ * @mode:	the read mode supported by the driver
+ *
+ * The drivers can use this fuction to scan the SPI NOR.
+ * In the scanning, it will try to get all the necessary information to
+ * fill the mtd_info{} and the spi_nor{}.
+ *
+ * The board may assigns a spi_device_id with @id which be used to compared with
+ * the spi_device_id detected by the scanning.
+ *
+ * Return: 0 for success, others for failure.
+ */
+int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
+			enum read_mode mode);
+extern const struct spi_device_id spi_nor_ids[];
+
 #endif
Signature · 1 line
1.7.2.rc3
#4 lore raw

PATCH v4 4/7 mtd: m25p80: use the SPI nor framework

In reply to Huang Shijie

Use the new SPI nor framework, and rewrite the m25p80:
(0) remove all the NOR comands.
(1) change the m25p->command to an array.
(2) implement the necessary hooks, such as m25p_read/m25p_write.

Tested with the m25p32.

---
 drivers/mtd/devices/Kconfig  |    2 +-
 drivers/mtd/devices/m25p80.c | 1275 ++++--------------------------------------
 2 files changed, 100 insertions(+), 1177 deletions(-)
drivers/mtd/devices/Kconfig +1 -1
index 0128138..004b17b 100644
@@ -80,7 +80,7 @@ config MTD_DATAFLASH_OTP
 
 config MTD_M25P80
 	tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
-	depends on SPI_MASTER
+	depends on SPI_MASTER && MTD_SPI_NOR_BASE
 	help
 	  This enables access to most modern SPI flash chips, used for
 	  program and data storage.   Series supported include Atmel AT26DF,
drivers/mtd/devices/m25p80.c +99 -1176

1,384 lines not on this page · raw message

Signature · 1 line
1.7.2.rc3
#5 lore raw

PATCH v4 5/7 mtd: spi-nor: add a helper to find the spi_device_id

In reply to Huang Shijie

Add the spi_nor_match_id() to find the proper spi_device_id in the spi_nor_ids table.

---
 drivers/mtd/spi-nor/spi-nor.c |   12 ++++++++++++
 include/linux/mtd/spi-nor.h   |   12 ++++++++++++
 2 files changed, 24 insertions(+), 0 deletions(-)
drivers/mtd/spi-nor/spi-nor.c +12 -0
index de7b8d1..2254ca4 100644
@@ -1075,6 +1075,18 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
 	return 0;
 }
 
+const struct spi_device_id *spi_nor_match_id(char *name)
+{
+	const struct spi_device_id *id = spi_nor_ids;
+
+	while (id->name[0]) {
+		if (!strcmp(name, id->name))
+			return id;
+		id++;
+	}
+	return NULL;
+}
+
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Huang Shijie <[email protected]>");
 MODULE_AUTHOR("Mike Lavender");
include/linux/mtd/spi-nor.h +12 -0
index 06bd096..d3c3abf 100644
@@ -179,4 +179,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
 			enum read_mode mode);
 extern const struct spi_device_id spi_nor_ids[];
 
+/**
+ * spi_nor_match_id() - find the spi_device_id by the name
+ * @name:	the name of the spi_device_id
+ *
+ * The drivers use this function to find the spi_device_id
+ * specified by the @name.
+ *
+ * Return: returns the right spi_device_id pointer on success,
+ *         and returns NULL on failure.
+ */
+const struct spi_device_id *spi_nor_match_id(char *name);
+
 #endif
Signature · 1 line
1.7.2.rc3
#6 lore raw

PATCH v4 6/7 Documentation: add the binding file for Freescale QuadSPI driver

In reply to Huang Shijie

This patch adds the binding file for Freescale QuadSPI driver.

---
 .../devicetree/bindings/mtd/fsl-quadspi.txt        |   26 ++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
Documentation/devicetree/bindings/mtd/fsl-quadspi.txt new file +26 -0
new file mode 100644
index 0000000..77ba6a7
@@ -0,0 +1,26 @@
+* Freescale Quad Serial Peripheral Interface(QuadSPI)
+
+Required properties:
+- compatible : Should be "fsl,vf610-qspi"
+- reg : the first contains the register location and length,
+        the second contains the memory mapping address and length
+- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
+- interrupts : Should contain the interrupt for the device
+- clocks : The clocks needed by the QuadSPI controller
+- clock-names : the name of the clocks
+
+Example:
+
+qspi0: quadspi at 40044000 {
+	compatible = "fsl,vf610-qspi";
+	reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
+	reg-names = "QuadSPI", "QuadSPI-memory";
+	interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clks VF610_CLK_QSPI0_EN>,
+		<&clks VF610_CLK_QSPI0>;
+	clock-names = "qspi_en", "qspi";
+
+	flash0: s25fl128s at 0 {
+		....
+	};
+};
Signature · 1 line
1.7.2.rc3
#7 lore raw

PATCH v4 7/7 mtd: spi-nor: Add Freescale QuadSPI driver

In reply to Huang Shijie

(0) What is the QuadSPI controller?

The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines.

(1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers.

(2) The definition of the LUT register shows below:

---------------------------------------------------
| INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
---------------------------------------------------

There are several types of INSTRx, such as:
CMD : the SPI NOR command.
ADDR : the address for the SPI NOR command.
DUMMY : the dummy cycles needed by the SPI NOR command.
....

There are several types of PADx, such as:
PAD1 : use a singe I/O line.
PAD2 : use two I/O lines.
PAD4 : use quad I/O lines.
....

(3) Test this driver with the JFFS2 and UBIFS:

For jffs2:
-------------
#flash_eraseall /dev/mtd0
#mount -t jffs2 /dev/mtdblock0 tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5

For ubifs:
-------------
#flash_eraseall /dev/mtd0
#ubiattach /dev/ubi_ctrl -m 0
#ubimkvol /dev/ubi0 -N test -m
#mount -t ubifs ubi0:test tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5

---
 drivers/mtd/spi-nor/Kconfig       |    6 +
 drivers/mtd/spi-nor/Makefile      |    1 +
 drivers/mtd/spi-nor/fsl-quadspi.c |  957 +++++++++++++++++++++++++++++++++++++
 3 files changed, 964 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/spi-nor/fsl-quadspi.c
drivers/mtd/spi-nor/Kconfig +6 -0
index 41591af..64cfc39 100644
@@ -4,3 +4,9 @@ config MTD_SPI_NOR_BASE
 	help
 	  This is the framework for the SPI NOR which can be used by the SPI
 	  device drivers and the SPI-NOR device driver.
+config SPI_FSL_QUADSPI
+	tristate "Freescale Quad SPI controller"
+	depends on ARCH_MXC && MTD_SPI_NOR_BASE
+	help
+	  This enables support for the Quad SPI controller in master mode.
+	  We only connect the NOR to this controller now.
drivers/mtd/spi-nor/Makefile +1 -0
index 7dfe1f9..51f9d8b 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_MTD_SPI_NOR_BASE)	+= spi-nor.o
+obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o
drivers/mtd/spi-nor/fsl-quadspi.c new file +957 -0

957 lines not on this page · raw message

Signature · 1 line
1.7.2.rc3
#8 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

In reply to Huang Shijie

Hi,

Quoted 29 lines · Huang Shijie

1.) Why add a new framework for SPI NOR?
The SPI-NOR controller such as Freescale's Quadspi controller is working in a different way from the SPI bus. It should knows the NOR commands to find the right LUT sequence. Unfortunately, the current code can not meet this requirement.

2.) How does this patch set do?
This patch set adds a new spi-nor layer.
Before this patch, the layer is like:

                   MTD
         ------------------------
                  m25p80
         ------------------------
               spi bus driver
         ------------------------
                SPI NOR chip
   After this patch, the layer is like:
                   MTD
         ------------------------
                  spi-nor
         ------------------------
                  m25p80
         ------------------------
               spi bus driver
         ------------------------
               SPI NOR chip
Quoted 8 lines

With the spi-nor controller driver(Freescale Quadspi), it looks like:

                   MTD
         ------------------------
                  spi-nor
         ------------------------
                fsl-quadspi
         ------------------------
               SPI NOR chip

I'm new to this thread, may be I'll ask basic questions.
1) what does m25p80 contains with your new framework - will excludes quad stuff if they add
2) I didn't understand why the controller driver fsl-quadspi will be in mtd becuase as it's (q)spi driver
may does flash or non-flash functionalities if ie, the case should be part of drivers/spi/*
3) Can you explain your framework precisely take an example of like spi_controller_A with spi_flash_A
and qspi_controller_B and qspi_flash_B - how will this new framework operates.

Quoted 54 lines

3.) more details
This patch set adds a new data structrue spi_nor{}, clones most the common
code to spi-nor.c. Add spi_nor_xfer_cfg {} for the fundamental primitives:
read_xfer/write_xfer.

Make the m25p80.c/fsl_quaspi.c use the new APIs.

4.) Change log:
v3 --> v4:
[1] move the wait_till_ready to the @read hook.
[2] convert to linux-doc style comment.
[3] remove the some DT property for QuadSPI driver, such as "fsl,nor-size".
[4] others

v2 --> v3:
[1] add prepare/unprepare hooks for spi_nor{}.
[2] add a new "priv" field for spi_nor{}.
[3] add the Freescale Quadspi driver which supports the Quad read by default.

v1 --> v2:
[1] follow Angus's advice, add more hooks and data structrures.
[2] others.

Huang Shijie (7):
mtd: spi-nor: copy the SPI NOR commands to a new header file
mtd: spi-nor: add the basic data structures
mtd: spi-nor: add the framework for SPI NOR
mtd: m25p80: use the SPI nor framework
mtd: spi-nor: add a helper to find the spi_device_id
Documentation: add the binding file for Freescale QuadSPI driver
mtd: spi-nor: Add Freescale QuadSPI driver

 .../devicetree/bindings/mtd/fsl-quadspi.txt        |   26 +
 drivers/mtd/Kconfig                                |    2 +
 drivers/mtd/Makefile                               |    1 +
 drivers/mtd/devices/Kconfig                        |    2 +-
 drivers/mtd/devices/m25p80.c                       | 1275 ++------------------
 drivers/mtd/spi-nor/Kconfig                        |   12 +
 drivers/mtd/spi-nor/Makefile                       |    2 +
 drivers/mtd/spi-nor/fsl-quadspi.c                  |  957 +++++++++++++++
 drivers/mtd/spi-nor/spi-nor.c                      | 1093 +++++++++++++++++
 include/linux/mtd/spi-nor.h                        |  194 +++
 10 files changed, 2387 insertions(+), 1177 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
 create mode 100644 drivers/mtd/spi-nor/Kconfig
 create mode 100644 drivers/mtd/spi-nor/Makefile
 create mode 100644 drivers/mtd/spi-nor/fsl-quadspi.c
 create mode 100644 drivers/mtd/spi-nor/spi-nor.c
 create mode 100644 include/linux/mtd/spi-nor.h
Signature · 2 lines
Thanks,
Jagan.
#9 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

? 2014?01?16? 03:15, Jagan Teki ??:

Quoted 40 lines

Hi,

Quoted 29 lines · Huang Shijie

1.) Why add a new framework for SPI NOR?
The SPI-NOR controller such as Freescale's Quadspi controller is working in a different way from the SPI bus. It should knows the NOR commands to find the right LUT sequence. Unfortunately, the current code can not meet this requirement.

2.) How does this patch set do?

    This patch set adds a new spi-nor layer.
    Before this patch, the layer is like:

                    MTD
          ------------------------
                   m25p80
          ------------------------
                spi bus driver
          ------------------------
                 SPI NOR chip

    After this patch, the layer is like:
                    MTD
          ------------------------
                   spi-nor
          ------------------------
                   m25p80
          ------------------------
                spi bus driver
          ------------------------
                SPI NOR chip
Quoted 8 lines
   With the spi-nor controller driver(Freescale Quadspi), it looks like:
                    MTD
          ------------------------
                   spi-nor
          ------------------------
                 fsl-quadspi
          ------------------------
                SPI NOR chip
Quoted 3 lines

I'm new to this thread, may be I'll ask basic questions.
1) what does m25p80 contains with your new framework - will excludes quad stuff if they add

sorry, i do not understand your meaning.

do you think the m25p80 can not support the quad read after this patch set?

Quoted 4 lines

2) I didn't understand why the controller driver fsl-quadspi will be in mtd becuase as it's (q)spi driver
may does flash or non-flash functionalities if ie, the case should be part of drivers/spi/*

Please read this thread, Mark though it should be spi nor driver:

http://marc.info/?l=linux-arm-kernel&m=137782885415953&w=2

Quoted 4 lines

3) Can you explain your framework precisely take an example of like spi_controller_A with spi_flash_A
and qspi_controller_B and qspi_flash_B - how will this new framework operates.

The framework is just cloned from the m25p80.c, and extract the common code, and provides more
hooks such as

@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.

The drivers can implement these hooks.

thanks
Huang Shijie

#10 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Hi Huang Shijie,

Thanks for your response, please see below.

Quoted 38 lines · Huang Shijie

? 2014?01?16? 03:15, Jagan Teki ??:

Quoted 36 lines

Hi,

Quoted 32 lines · Huang Shijie

1.) Why add a new framework for SPI NOR?
The SPI-NOR controller such as Freescale's Quadspi controller is
working
in a different way from the SPI bus. It should knows the NOR commands
to
find the right LUT sequence. Unfortunately, the current code can not
meet
this requirement.

2.) How does this patch set do?

    This patch set adds a new spi-nor layer.
    Before this patch, the layer is like:

                    MTD
          ------------------------
                   m25p80
          ------------------------
                spi bus driver
          ------------------------
                 SPI NOR chip

    After this patch, the layer is like:
                    MTD
          ------------------------
                   spi-nor
          ------------------------
                   m25p80
          ------------------------
                spi bus driver
          ------------------------
                SPI NOR chip

Just for looking on your new framework, is that above link correct. I guess it should be MTD -- m25p80 -- spi-nor -- spi bus driver -- SPI NOR chip

Because m25p80 will register to mtd core on top and will call spi core data transfer.

Correct me if am wrong.

Quoted 38 lines
Quoted 10 lines
Quoted 9 lines
   With the spi-nor controller driver(Freescale Quadspi), it looks like:
                    MTD
          ------------------------
                   spi-nor
          ------------------------
                 fsl-quadspi
          ------------------------
                SPI NOR chip
Quoted 3 lines

I'm new to this thread, may be I'll ask basic questions.
1) what does m25p80 contains with your new framework - will excludes quad stuff if they add

sorry, i do not understand your meaning.

do you think the m25p80 can not support the quad read after this patch set?

Quoted 4 lines

2) I didn't understand why the controller driver fsl-quadspi will be in mtd becuase as it's (q)spi driver
may does flash or non-flash functionalities if ie, the case should be part of drivers/spi/*

Please read this thread, Mark though it should be spi nor driver:

http://marc.info/?l=linux-arm-kernel&m=137782885415953&w=2

Quoted 5 lines

3) Can you explain your framework precisely take an example of like spi_controller_A with spi_flash_A
and qspi_controller_B and qspi_flash_B - how will this new framework operates.

The framework is just cloned from the m25p80.c, and extract the common code, and provides more
hooks such as

Quoted 15 lines

@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2
B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

Now please tell me how your framework works in this case? how many drivers do I need to right
and call traces.

Signature · 2 lines
Thanks,
Jagan.
#11 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 11 lines · Jagan Teki
Quoted 10 lines
Quoted 10 lines
Quoted 10 lines
    After this patch, the layer is like:
                    MTD
          ------------------------
                   spi-nor
          ------------------------
                   m25p80
          ------------------------
                spi bus driver
          ------------------------
                SPI NOR chip
Quoted 2 lines

Just for looking on your new framework, is that above link correct. I guess it should be MTD -- m25p80 -- spi-nor -- spi bus driver -- SPI NOR chip

I do not think so.
The spi-nor layer does not contact with the spi bus driver directly.

Quoted 25 lines
Quoted 9 lines
Quoted 5 lines

3) Can you explain your framework precisely take an example of like spi_controller_A with spi_flash_A
and qspi_controller_B and qspi_flash_B - how will this new framework operates.

The framework is just cloned from the m25p80.c, and extract the common code, and provides more
hooks such as

Quoted 15 lines

@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.

Quoted 2 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

You can use the framework for B2. But for B1, you should not use the framework, since this framework is just for the SPI-NOR. If you do not connected with a NOR, i think it's better to code another driver for your controller.

thanks
Huang Shijie

#12 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 12 lines · Huang Shijie
Quoted 11 lines · Jagan Teki
Quoted 10 lines
Quoted 10 lines
Quoted 10 lines
    After this patch, the layer is like:
                    MTD
          ------------------------
                   spi-nor
          ------------------------
                   m25p80
          ------------------------
                spi bus driver
          ------------------------
                SPI NOR chip
Quoted 5 lines
Quoted 2 lines

Just for looking on your new framework, is that above link correct. I guess it should be MTD -- m25p80 -- spi-nor -- spi bus driver -- SPI NOR chip

I do not think so.
The spi-nor layer does not contact with the spi bus driver directly.

Yes - now I understand the flow from seeing the code.
With your new framework
1. not an exact spi-nor
have one controller driver at drivers/spi/* will register to spi core. have m25p80.c will scan the flash details from
drivers/mtd/spi-nor/spi-nor.c and
m25p80 will register the MTD core and for transfer calls m25p80
will calls spi core.
2. spi-nor style
have one controller driver at drivers/mtd/spi-nor/fsl-quadspi.c
will register MTD core
and scan the flash details from drivers/mtd/spi-nor/spi-nor.c and
for transfer will calls
through direct writel and readl with cmd+data fashion.

Correct me If my understanding was wrong.

Quoted 29 lines
Quoted 26 lines
Quoted 10 lines
Quoted 6 lines

3) Can you explain your framework precisely take an example of like spi_controller_A with spi_flash_A
and qspi_controller_B and qspi_flash_B - how will this new framework operates.

The framework is just cloned from the m25p80.c, and extract the common code, and provides more
hooks such as

Quoted 15 lines

@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.

Quoted 2 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

Quoted 8 lines

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

You can use the framework for B2. But for B1, you should not use the framework, since this framework is just for the SPI-NOR. If you do not connected with a NOR, i think it's better to code another driver for your controller.

Means we have two separate controller drivers for same controller one with spi-nor and
another with spi is it?

Do you think this is a good idea, I understand you have a complete and well guided new
spi-nor framework.

Signature · 2 lines
Thanks,
Jagan.
#13 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 8 lines · Jagan Teki
Quoted 8 lines
Quoted 2 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

Quoted 7 lines
Quoted 3 lines

You can use the framework for B2. But for B1, you should not use the framework, since this framework is just for the SPI-NOR. If you do not connected with a NOR, i think it's better to code another driver for your controller.

Means we have two separate controller drivers for same controller one with spi-nor and
another with spi is it?

Take drivers/spi/spi-imx.c for example, if you connect a NOR to it, you only need to add a NOR device node in the device tree. In the probe, it will call the m25p80.c to probe the NOR device.

But if we connect other device to it. you should set another device node for it.

I am not sure if your controller driver can works as the spi-imx.c

thanks
Huang Shijie

#14 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 16 lines · Huang Shijie
Quoted 8 lines · Jagan Teki
Quoted 8 lines
Quoted 2 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

Quoted 7 lines
Quoted 3 lines

You can use the framework for B2. But for B1, you should not use the framework, since this framework is just for the SPI-NOR. If you do not connected with a NOR, i think it's better to code another driver for your controller.

Means we have two separate controller drivers for same controller one with spi-nor and
another with spi is it?

Quoted 7 lines

Take drivers/spi/spi-imx.c for example, if you connect a NOR to it, you only need to add a NOR device node in the device tree. In the probe, it will call the m25p80.c to probe the NOR device.

But if we connect other device to it. you should set another device node for it.

I am not sure if your controller driver can works as the spi-imx.c

My question here was - this new framework suggest to write a two different controller
drivers one is for non spi-nor and spi-nor models? do you agree that?

And also one important note from your design was spi-nor mode is completely bypassing
Linux spi core is that the good idea?

Signature · 2 lines
Thanks,
Jagan.
#15 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 25 lines · Jagan Teki
Quoted 16 lines · Huang Shijie
Quoted 8 lines · Jagan Teki
Quoted 8 lines
Quoted 2 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

Quoted 7 lines
Quoted 3 lines

You can use the framework for B2. But for B1, you should not use the framework, since this framework is just for the SPI-NOR. If you do not connected with a NOR, i think it's better to code another driver for your controller.

Means we have two separate controller drivers for same controller one with spi-nor and
another with spi is it?

Quoted 7 lines

Take drivers/spi/spi-imx.c for example, if you connect a NOR to it, you only need to add a NOR device node in the device tree. In the probe, it will call the m25p80.c to probe the NOR device.

But if we connect other device to it. you should set another device node for it.

I am not sure if your controller driver can works as the spi-imx.c

Quoted 7 lines

My question here was - this new framework suggest to write a two different controller
drivers one is for non spi-nor and spi-nor models? do you agree that?

And also one important note from your design was spi-nor mode is completely bypassing
Linux spi core is that the good idea?

I feel these are good points to discuss all.
1. With new framework seems like we need two separate controller drivers one for non spi-nor and one for spi-nor with single controller hw
2. With spi-nor implementation though the hw is spi complaint but the sw is completely ignoring the Linux SPI core interaction.

I feel above two points are technically wrong - Please correct me if am wrong but need all developers will join..thanks!

Signature · 1 line
Jagan.
#16 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Hi Shijie,

Quoted 1 line

From: Jagan Teki [mailto:jagannadh.teki at gmail.com]

[...]

Quoted 10 lines

I feel these are good points to discuss all.
1. With new framework seems like we need two separate controller drivers one for non spi-nor and one for spi-nor with single controller hw
2. With spi-nor implementation though the hw is spi complaint but the sw is completely ignoring the Linux SPI core interaction.

I feel above two points are technically wrong - Please correct me if am wrong but need all developers will join..thanks!

I have been following this patch-set from sometime, And I think point (2) has been discussed back and forth in multiple times in earlier discussions. So, Is it possible for you to summarize point (2) with all pros-n-cons ?

- A README will helpful to clear all doubts and will ease your implementation as well.
- It will also help in reducing turn-around time to get this framework in acceptable state and still keep it generic enough.

You can submit the README as Documentation/mtd/spi-nor.txt

with regards, pekon

#17 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 18 lines · Pekon

Hi Shijie,

Quoted 1 line

From: Jagan Teki [mailto:jagannadh.teki at gmail.com]

[...]

Quoted 10 lines

I feel these are good points to discuss all.
1. With new framework seems like we need two separate controller drivers one for non spi-nor and one for spi-nor with single controller hw
2. With spi-nor implementation though the hw is spi complaint but the sw is completely ignoring the Linux SPI core interaction.

I feel above two points are technically wrong - Please correct me if am wrong but need all developers will join..thanks!

I have been following this patch-set from sometime, And I think point (2) has been discussed back and forth in multiple times in earlier discussions. So, Is it possible for you to summarize point (2) with all pros-n-cons ?

Quoted 6 lines

- A README will helpful to clear all doubts and will ease your implementation as well.
- It will also help in reducing turn-around time to get this framework in acceptable state and still keep it generic enough.

You can submit the README as Documentation/mtd/spi-nor.txt

okay.

thanks
Huang Shijie

#18 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

In reply to Jagan Teki

? 2014?01?17? 16:39, Jagan Teki ??:

Quoted 19 lines · Huang Shijie
Quoted 18 lines · Jagan Teki
Quoted 7 lines
Quoted 7 lines
Quoted 2 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

Quoted 6 lines
Quoted 3 lines

You can use the framework for B2. But for B1, you should not use the framework, since this framework is just for the SPI-NOR. If you do not connected with a NOR, i think it's better to code another driver for your controller.

Means we have two separate controller drivers for same controller one with spi-nor and
another with spi is it?

Take drivers/spi/spi-imx.c for example, if you connect a NOR to it, you only need to add a NOR device node in the device tree. In the probe, it will call the m25p80.c to probe the NOR device.

Quoted 6 lines
Quoted 3 lines

But if we connect other device to it. you should set another device node for it.

I am not sure if your controller driver can works as the spi-imx.c

My question here was - this new framework suggest to write a two different controller
drivers one is for non spi-nor and spi-nor models? do you agree that?

If your controller can either connects to a NOR, or can connects to other devices, it means your controller is a _BUS_.
You just need to write the bus driver for your controller, such as the spi-imx.c and drivers/bus/imx-weim.c do.

Since you have connect a device to your controller. you also need to write a driver for your device, such as the m25p80.c is for your spi nor device.

Just think about that how do you code your driver for SPI NOR _without_ this framework:
do your driver need to call the m25p80.c? if you do call the m25p80.c, you actually write your so-called "two drivers" :)

This framework does not change any logic for the current kernel, except adding a layer. With the new layer, we can code the
driver for the controllers which is a SPI-NOR controller, not a SPI bus controller.

Quoted 5 lines

And also one important note from your design was spi-nor mode is completely bypassing
Linux spi core is that the good idea?

yes. I think it's a good idea.

As Mark even pointed, the freescale's Quadspi controller is not a SPI controller, it is a SPI-NOR controller, it does _not_ need the LINUX SPI core.

thanks
Huang Shijie

#19 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 49 lines · Huang Shijie

? 2014?01?17? 16:39, Jagan Teki ??:

Quoted 30 lines
Quoted 28 lines · Huang Shijie
Quoted 16 lines · Jagan Teki
Quoted 10 lines
Quoted 3 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

Quoted 5 lines

You can use the framework for B2. But for B1, you should not use the framework,
since this framework is just for the SPI-NOR. If you do not connected with
a NOR, i think it's better to code another driver for your controller.

Quoted 3 lines

Means we have two separate controller drivers for same controller one with spi-nor and
another with spi is it?

Take drivers/spi/spi-imx.c for example, if you connect a NOR to it, you only
need to add a NOR device node in the device tree. In the probe, it will call
the m25p80.c to probe the NOR device.

Quoted 8 lines
Quoted 4 lines

But if we connect other device to it. you should set another device node for it.

I am not sure if your controller driver can works as the spi-imx.c

My question here was - this new framework suggest to write a two different controller
drivers one is for non spi-nor and spi-nor models? do you agree that?

If your controller can either connects to a NOR, or can connects to other devices, it means your controller is a _BUS_.
You just need to write the bus driver for your controller, such as the spi-imx.c and drivers/bus/imx-weim.c do.

Quoted 8 lines

Since you have connect a device to your controller. you also need to write a driver for your device, such as the m25p80.c is
for your spi nor device.

Just think about that how do you code your driver for SPI NOR _without_ this framework:
do your driver need to call the m25p80.c? if you do call the m25p80.c, you actually write your so-called "two drivers" :)

I'm still not convinced here, sorry!
Let me explain more with example, Just take your (q)spi controller as an example B_FSL1 designed with - serial flash
B_FSL2 designed with - touch screen

With this design If we follow current we just need one controller driver (drivers/spi/spi-fsl.c)
to serve touch screen and serial flash from upper layers.

MTD core Input core
------------- -------------------------------
m25p80.c spi touchscreen driver (drivers/input/touchscreen)
----------------------------------------------------
SPI core
----------------------------------------------------
controller driver (drivers/spi/spi-fsl.)
----------------------------------------------------

But with your new SPI-NOR

MTD core
------------
SPI-NOR Input core
----------- ------------------
fsl-quadspi.c spi touchscreen driver (drivers/input/touchscreen)
---------------- ------------------------------

                         SPI Core
                         -----------------------------
                         controller driver (drivers/spi/spi-fsl.c)
                         -----------------------------------------

Here see we have two separate drivers for the same controller as it offers two functionalities. and also it never talk to Linux SPI subsystem which is not a good for me as intern hw is SPI-based it must talk to subsystem to make use of Linux SPI API's.

And also you mentioned SPI-NOR controller is not a SPI controller what does that means because it's a NOR flash which is of SPI protocol based.

I understand that your framework doing good things in matured manner, but seems like it's confuse to me to follow common standards - Just my opinion, may be I'm incorrect.

One more thing question - I have 1-wire spi controller which I was used for flash in
one board and keyboard in another board, so if I follow your framework I need to write
a driver in drivers/mtd/spi-nor/foo-spi.c and one more in drivers/spi/spi-foo.c - correct?

Quoted 19 lines

This framework does nSPot change any logic for the current kernel, except adding a layer. With the new layer, we can code the
driver for the controllers which is a SPI-NOR controller, not a SPI bus controller.

Quoted 5 lines

And also one important note from your design was spi-nor mode is completely bypassing
Linux spi core is that the good idea?

yes. I think it's a good idea.

As Mark even pointed, the freescale's Quadspi controller is not a SPI controller, it is a SPI-NOR controller, it does _not_ need the LINUX SPI core.

Signature · 2 lines
Thanks,
Jagan.
#20 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

Quoted 31 lines · Jagan Teki
Quoted 4 lines

Just think about that how do you code your driver for SPI NOR _without_ this framework:
do your driver need to call the m25p80.c? if you do call the m25p80.c, you actually write your so-called "two drivers" :)

I'm still not convinced here, sorry!
Let me explain more with example, Just take your (q)spi controller as an example B_FSL1 designed with - serial flash
B_FSL2 designed with - touch screen

With this design If we follow current we just need one controller driver (drivers/spi/spi-fsl.c)
to serve touch screen and serial flash from upper layers.

MTD core Input core
------------- -------------------------------
m25p80.c spi touchscreen driver (drivers/input/touchscreen)
----------------------------------------------------
SPI core
----------------------------------------------------
controller driver (drivers/spi/spi-fsl.)
----------------------------------------------------

But with your new SPI-NOR

MTD core
------------
SPI-NOR Input core
----------- ------------------
fsl-quadspi.c spi touchscreen driver (drivers/input/touchscreen)
---------------- ------------------------------

Quoted 5 lines
                         SPI Core
                         -----------------------------
                         controller driver (drivers/spi/spi-fsl.c)
                         -----------------------------------------

There is no relationship with the fsl-quadspi.c.

It should be like this:
MTD core
------------

 SPI-NOR  framework                       Input core
 -----------                              ------------------
 m25p80.c                                 spi  touchscreen driver  (drivers/input/touchscreen)
 ----------------                         ------------------------------
 SPI Core                                 SPI Core
 -----------------------                  -----------------------------
 drivers/spi/spi-fsl.c                    controller driver (drivers/spi/spi-fsl.c)
 --------------------------               -----------------------------------------
Quoted 7 lines

Here see we have two separate drivers for the same controller as it offers two functionalities. and also it never talk to Linux SPI subsystem which is not a good for me as intern hw is SPI-based it must talk to subsystem to make use of Linux SPI API's.

And also you mentioned SPI-NOR controller is not a SPI controller what does that means because it's a NOR flash which is of SPI protocol based.

The SPI controller (or spi bus controller) only handles the _byte_ streams; while the spi-nor controller, such as fsl-quadspi.c, can has to __known__ the exact SPI NOR command to find the proper LUT.

Please read the thread i ever posted in the previous email.

Quoted 11 lines

I understand that your framework doing good things in matured manner, but seems like it's confuse to me to follow common standards - Just my opinion, may be I'm incorrect.

One more thing question - I have 1-wire spi controller which I was used for flash in
one board and keyboard in another board, so if I follow your framework I need to write
a driver in drivers/mtd/spi-nor/foo-spi.c and one more in drivers/spi/spi-foo.c - correct?

Please read the device tree node of your controller, find the code like

...................................................

	flash: m25p80 at 0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p32";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};

...................................................

if you call the m25p80, you do not need to change anything.

thanks
Huang Shijie

#21 lore raw

v4 cover mtd: spi-nor: add a new framework for SPI NOR

In reply to Jagan Teki
Quoted 66 lines · Jagan Teki
Quoted 11 lines · Huang Shijie
Quoted 10 lines · Jagan Teki
Quoted 10 lines
Quoted 10 lines
Quoted 10 lines
     After this patch, the layer is like:
                     MTD
           ------------------------
                    spi-nor
           ------------------------
                    m25p80
           ------------------------
                 spi bus driver
           ------------------------
                 SPI NOR chip
Quoted 4 lines
Quoted 2 lines

Just for looking on your new framework, is that above link correct. I guess it should be MTD -- m25p80 -- spi-nor -- spi bus driver -- SPI NOR chip

I do not think so.
The spi-nor layer does not contact with the spi bus driver directly.

Yes - now I understand the flow from seeing the code.
With your new framework
1. not an exact spi-nor
have one controller driver at drivers/spi/* will register to spi core. have m25p80.c will scan the flash details from
drivers/mtd/spi-nor/spi-nor.c and
m25p80 will register the MTD core and for transfer calls m25p80
will calls spi core.
2. spi-nor style
have one controller driver at drivers/mtd/spi-nor/fsl-quadspi.c
will register MTD core
and scan the flash details from drivers/mtd/spi-nor/spi-nor.c and
for transfer will calls
through direct writel and readl with cmd+data fashion.

Correct me If my understanding was wrong.

Quoted 26 lines
Quoted 24 lines
Quoted 9 lines
Quoted 5 lines

3) Can you explain your framework precisely take an example of like spi_controller_A with spi_flash_A
and qspi_controller_B and qspi_flash_B - how will this new framework operates.

The framework is just cloned from the m25p80.c, and extract the common code, and provides more
hooks such as

Quoted 15 lines

@prepare/unpreare: used to do some work before or after the
read/write/erase/lock/unlock.
@read_xfer/write_xfer: We can use these two hooks to code all
the following hooks if the driver tries to implement them by itself.
@read_reg: used to read the registers, such as read status register,
read configure register.
@write_reg: used to write the registers, such as write enable,
erase sector.
@read_id: read out the ID info.
@wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR.
@write: write data to the NOR.
@erase: erase a sector of the NOR.

Quoted 2 lines

My basic question is like I have a qspi spi controller in my SOC and I designed two boards B1 and B2

Quoted 8 lines

okay.

Quoted 3 lines

B1 with quad spi controller connected with non-flash as a slave and B2 with quad spi controller connected
with quad flash as a slave.

You can use the framework for B2. But for B1, you should not use the framework, since this framework is just for the SPI-NOR. If you do not connected with a NOR, i think it's better to code another driver for your controller.

Quoted 8 lines

Means we have two separate controller drivers for same controller one with spi-nor and
another with spi is it?

Do you think this is a good idea, I understand you have a complete and well guided new
spi-nor framework.

I dont think its a good idea to support a single controller with two drivers for two different usecase.