clk: samsung: pll: Fix checkpatch errors

PATCH New Sachin Kamat 2 participants 4 messages Jan 15, 2014 – Jan 24, 2014

Subsystems (3)

Common clk Arm Samsung Exynos Samsung SoC clock drivers

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Sachin Kamat

author

2014-01-15 10:01 UTC #0 lore raw

PATCH 1/2 clk: samsung: pll: Fix checkpatch errors

Fixes the following type of checkpatch errors:
ERROR: return is not a function, parentheses are not required

Signed-off-by Sachin Kamat <[email protected]>

---
 drivers/clk/samsung/clk-pll.c |   14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

drivers/clk/samsung/clk-pll.c +7 -7

index 529e11dc2c6b..f2372fca0136 100644
@@ -99,7 +99,7 @@ static inline bool samsung_pll35xx_mp_change(
 	old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
 	old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
 
-	return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
+	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
 }
 
 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,

@@ -207,8 +207,8 @@ static inline bool samsung_pll36xx_mpk_change(
 	old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
 	old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
 
-	return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
-		rate->kdiv != old_kdiv);
+	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+		rate->kdiv != old_kdiv;
 }
 
 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,

@@ -320,8 +320,8 @@ static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
 	old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
 	old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
 
-	return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
-		|| old_afc != rate->afc);
+	return old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
+		|| old_afc != rate->afc;
 }
 
 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,

@@ -467,8 +467,8 @@ static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
 	old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
 	old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
 
-	return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
-		|| old_kdiv != rate->kdiv);
+	return old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
+		|| old_kdiv != rate->kdiv;
 }
 
 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,

Signature · 1 line

1.7.9.5

Sachin Kamat

author

2014-01-15 10:01 UTC #1 lore raw

PATCH 2/2 clk: exynos4: Fix spacing related checkpatch errors

Silences the following type of checkpatch errors:
ERROR: space prohibited after that open parenthesis '('

Signed-off-by Sachin Kamat <[email protected]>

---
 drivers/clk/samsung/clk-exynos4.c |   50 ++++++++++++++++++-------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

drivers/clk/samsung/clk-exynos4.c +25 ~~-25~~

index 12a9f28f9f17..3f412b4ef3e3 100644
@@ -945,13 +945,13 @@ static struct of_device_id ext_clk_match[] __initdata = {
 static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = {
 	PLL_45XX_RATE(1200000000, 150,  3, 1, 28),
 	PLL_45XX_RATE(1000000000, 250,  6, 1, 28),
-	PLL_45XX_RATE( 800000000, 200,  6, 1, 28),
-	PLL_45XX_RATE( 666857142, 389, 14, 1, 13),
-	PLL_45XX_RATE( 600000000, 100,  4, 1, 13),
-	PLL_45XX_RATE( 533000000, 533, 24, 1,  5),
-	PLL_45XX_RATE( 500000000, 250,  6, 2, 28),
-	PLL_45XX_RATE( 400000000, 200,  6, 2, 28),
-	PLL_45XX_RATE( 200000000, 200,  6, 3, 28),
+	PLL_45XX_RATE(800000000, 200,  6, 1, 28),
+	PLL_45XX_RATE(666857142, 389, 14, 1, 13),
+	PLL_45XX_RATE(600000000, 100,  4, 1, 13),
+	PLL_45XX_RATE(533000000, 533, 24, 1,  5),
+	PLL_45XX_RATE(500000000, 250,  6, 2, 28),
+	PLL_45XX_RATE(400000000, 200,  6, 2, 28),
+	PLL_45XX_RATE(200000000, 200,  6, 3, 28),
 	{ /* sentinel */ }
 };

@@ -959,10 +959,10 @@ static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = {
 	PLL_4600_RATE(192000000, 48, 3, 1,     0, 0),
 	PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
 	PLL_4600_RATE(180000000, 45, 3, 1,     0, 0),
-	PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),
-	PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),
-	PLL_4600_RATE( 49151992, 49, 3, 3,  9961, 0),
-	PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),
+	PLL_4600_RATE(73727996, 73, 3, 3, 47710, 1),
+	PLL_4600_RATE(67737602, 90, 4, 3, 20762, 1),
+	PLL_4600_RATE(49151992, 49, 3, 3,  9961, 0),
+	PLL_4600_RATE(45158401, 45, 3, 3, 10381, 0),
 	{ /* sentinel */ }
 };

@@ -971,7 +971,7 @@ static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = {
 	PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1,  1, 1),
 	PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
 	PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0),
-	PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),
+	PLL_4650_RATE(55360351, 53, 3, 3, 2417, 0, 17, 0),
 	{ /* sentinel */ }
 };

@@ -982,14 +982,14 @@ static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = {
 	PLL_35XX_RATE(1200000000, 200, 4, 0),
 	PLL_35XX_RATE(1100000000, 275, 6, 0),
 	PLL_35XX_RATE(1000000000, 125, 3, 0),
-	PLL_35XX_RATE( 900000000, 150, 4, 0),
-	PLL_35XX_RATE( 800000000, 100, 3, 0),
-	PLL_35XX_RATE( 700000000, 175, 3, 1),
-	PLL_35XX_RATE( 600000000, 200, 4, 1),
-	PLL_35XX_RATE( 500000000, 125, 3, 1),
-	PLL_35XX_RATE( 400000000, 100, 3, 1),
-	PLL_35XX_RATE( 300000000, 200, 4, 2),
-	PLL_35XX_RATE( 200000000, 100, 3, 2),
+	PLL_35XX_RATE(900000000, 150, 4, 0),
+	PLL_35XX_RATE(800000000, 100, 3, 0),
+	PLL_35XX_RATE(700000000, 175, 3, 1),
+	PLL_35XX_RATE(600000000, 200, 4, 1),
+	PLL_35XX_RATE(500000000, 125, 3, 1),
+	PLL_35XX_RATE(400000000, 100, 3, 1),
+	PLL_35XX_RATE(300000000, 200, 4, 2),
+	PLL_35XX_RATE(200000000, 100, 3, 2),
 	{ /* sentinel */ }
 };

@@ -997,10 +997,10 @@ static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = {
 	PLL_36XX_RATE(192000000, 48, 3, 1,     0),
 	PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
 	PLL_36XX_RATE(180000000, 45, 3, 1,     0),
-	PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),
-	PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),
-	PLL_36XX_RATE( 49151992, 49, 3, 3,  9961),
-	PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),
+	PLL_36XX_RATE(73727996, 73, 3, 3, 47710),
+	PLL_36XX_RATE(67737602, 90, 4, 3, 20762),
+	PLL_36XX_RATE(49151992, 49, 3, 3,  9961),
+	PLL_36XX_RATE(45158401, 45, 3, 3, 10381),
 	{ /* sentinel */ }
 };

@@ -1011,7 +1011,7 @@ static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = {
 	PLL_36XX_RATE(266000000, 133, 3, 2,     0),
 	PLL_36XX_RATE(160000000, 160, 3, 3,     0),
 	PLL_36XX_RATE(106031250,  53, 3, 2,  1024),
-	PLL_36XX_RATE( 53015625,  53, 3, 3,  1024),
+	PLL_36XX_RATE(53015625,  53, 3, 3,  1024),
 	{ /* sentinel */ }
 };

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-01-20 12:07 UTC #2 lore raw

PATCH 2/2 clk: exynos4: Fix spacing related checkpatch errors

Hi Sachin,

Quoted 7 lines · Sachin Kamat

Silences the following type of checkpatch errors:
ERROR: space prohibited after that open parenthesis '('
Signed-off-by Sachin Kamat <[email protected]>
---
  drivers/clk/samsung/clk-exynos4.c |   50 ++++++++++++++++++-------------------
  1 file changed, 25 insertions(+), 25 deletions(-)

I believe this is a false warning. In this special case the spaces greatly improve readability of static data in the driver, which I believe is preferred over the strict rules of checkpatch.

Best regards,
Tomasz

Sachin Kamat

author

2014-01-24 09:07 UTC #3 lore raw

PATCH 2/2 clk: exynos4: Fix spacing related checkpatch errors

Hi Tomasz,

Quoted 15 lines · Tomasz Figa

Hi Sachin,
Quoted 9 lines · Sachin Kamat
Silences the following type of checkpatch errors:
ERROR: space prohibited after that open parenthesis '('
Signed-off-by Sachin Kamat <[email protected]>
---
  drivers/clk/samsung/clk-exynos4.c |   50
++++++++++++++++++-------------------
  1 file changed, 25 insertions(+), 25 deletions(-)

Quoted 3 lines

I believe this is a false warning. In this special case the spaces greatly improve readability of static data in the driver, which I believe is preferred over the strict rules of checkpatch.

I agree that the existing pattern looks good to eyes :)
But then you will keep getting many such fix patches. The intention was to bring this to your notice.
What say about the other patch in this series?

Signature · 2 lines

With warm regards,
Sachin