esdhc: Workaround for card can't be detected on T4240QDS

PATCH New Haijun Zhang 4 participants 9 messages Jan 10, 2014 – Jan 23, 2014

Subsystems (2)

PowerPC MMC, SD and SDIO

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Haijun Zhang

author

2014-01-10 05:52 UTC #0 lore raw

PATCH v3 1/3 esdhc: Workaround for card can't be detected on T4240QDS

Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.

This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0.

Signed-off-by Haijun Zhang <[email protected]>

---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- Add the judgement condition for this broken card

 drivers/mmc/fsl_esdhc.c    | 4 ++++
 include/configs/T4240QDS.h | 5 +++++
 2 files changed, 9 insertions(+)

drivers/mmc/fsl_esdhc.c +4 -0

index e522a70..2ee93cd 100644
@@ -548,6 +548,10 @@ static int esdhc_getcd(struct mmc *mmc)
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 	int timeout = 1000;
 
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+	if (CONFIG_ESDHC_DETECT_QUIRK)
+		return 1;
+#endif
 	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 		udelay(1000);

include/configs/T4240QDS.h +5 -0

index c96df54..0e0b346 100644
@@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BRDCFG5			0x55
+#define QIXIS_MUX_SDHC			2
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 
 #define CONFIG_SYS_CSPR3_EXT	(0xf)

@@ -466,6 +468,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
+	IS_SVR_REV(get_svr(), 1, 0))
 #endif
 
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */

Signature · 1 line

1.8.4.1

Haijun Zhang

author

2014-01-10 05:52 UTC #1 lore raw

PATCH v3 2/3 esdhc: Detecting 8 bit width before mmc initialization

The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width.

Signed-off-by Haijun Zhang <[email protected]>

---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- No changes

 drivers/mmc/fsl_esdhc.c    | 5 +++++
 include/configs/T4240QDS.h | 3 +++
 2 files changed, 8 insertions(+)

drivers/mmc/fsl_esdhc.c +5 -0

index 2ee93cd..72ca109 100644
@@ -644,6 +644,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	if (caps & ESDHC_HOSTCAPBLT_HSS)
 		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+		mmc->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
 	mmc->f_min = 400000;
 	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);

include/configs/T4240QDS.h +3 -0

index 0e0b346..275a7a8 100644
@@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_BRDCFG5			0x55
 #define QIXIS_MUX_SDHC			2
+#define QIXIS_MUX_SDHC_WIDTH8		1
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 
 #define CONFIG_SYS_CSPR3_EXT	(0xf)

@@ -471,6 +472,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ESDHC_DETECT_QUIRK \
 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 	IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 #endif
 
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */

Signature · 1 line

1.8.4.1

Pantelis Antoniou

2014-01-22 12:00 UTC #2 lore raw

PATCH v3 2/3 esdhc: Detecting 8 bit width before mmc initialization

Hi Haijun,

Quoted 56 lines · Haijun Zhang

The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width.

Signed-off-by Haijun Zhang <[email protected]>

---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- No changes

drivers/mmc/fsl_esdhc.c | 5 +++++
include/configs/T4240QDS.h | 3 +++

2 files changed, 8 insertions(+)

drivers/mmc/fsl_esdhc.c +5 -0

index 2ee93cd..72ca109 100644
@@ -644,6 +644,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	if (caps & ESDHC_HOSTCAPBLT_HSS)
 		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+		mmc->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
 	mmc->f_min = 400000;
 	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);

include/configs/T4240QDS.h +3 -0

index 0e0b346..275a7a8 100644
@@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_BRDCFG5			0x55
 #define QIXIS_MUX_SDHC			2
+#define QIXIS_MUX_SDHC_WIDTH8		1
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 
 #define CONFIG_SYS_CSPR3_EXT	(0xf)

@@ -471,6 +472,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ESDHC_DETECT_QUIRK \
 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 	IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 #endif
 
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */

Signature · 1 line

1.8.4.1

Acked-by Pantelis Antoniou <[email protected]>

Haijun Zhang

author

2014-01-10 05:52 UTC #3 lore raw

PATCH v3 3/3 eSDHC: Calculate envaddr accroding to the address format

In reply to Haijun Zhang

On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the 32-bit source address specifies the memory address in block address format. Block length is fixed to 512 bytes as per the SD High Capacity specification. So we need to convert the block address format to byte address format to calculate the envaddr.

If there is no enough space for environment variables or envaddr is larger than 4GiB, we relocate the envaddr to 0x400. The address relocated is in the front of the first partition that is assigned for sdboot only.

Signed-off-by Haijun Zhang <[email protected]>

---
changes for V3:
- Define quirk in SOC specific file instead of code in driver
changes for V2:
- Use 0xffffffffu instead of UINT_MAX

 arch/powerpc/include/asm/config_mpc85xx.h |  3 +++
 board/freescale/common/sdhc_boot.c        | 29 +++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

arch/powerpc/include/asm/config_mpc85xx.h +3 -0

index 15affdc..e8bd76a 100644
@@ -152,6 +152,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)

@@ -552,6 +553,7 @@
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_BSC9132)
 #define CONFIG_MAX_CPUS			2

@@ -575,6 +577,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define CONFIG_E6500

board/freescale/common/sdhc_boot.c +29 -0

index f6e2b2b..022f38b 100644
@@ -16,6 +16,8 @@
 #define ESDHC_BOOT_IMAGE_SIZE	0x48
 #define ESDHC_BOOT_IMAGE_ADDR	0x50
 
+#define ESDHC_DEFAULT_ENVADDR	0x400
+
 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
 {
 	u8 *tmp_buf;

@@ -39,6 +41,33 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
 	/* Get the code size from offset 0x48 */
 	code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
 
+#ifdef CONFIG_ESDHC_HC_BLK_ADDR
+	/*
+	 * On soc BSC9131, BSC9132:
+	 * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
+	 * code length of these soc specify the memory address in block address
+	 * format. Block length is fixed to 512 bytes as per the SD High
+	 * Capacity specification.
+	 */
+	u64 tmp;
+
+	if (mmc->high_capacity) {
+		tmp = (u64)code_offset * blklen;
+		tmp += code_len * blklen;
+	} else
+		tmp = code_offset + code_len;
+
+	if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) ||
+			(tmp > 0xFFFFFFFFU))
+		*env_addr = ESDHC_DEFAULT_ENVADDR;
+	else
+		*env_addr = tmp;
+
+	free(tmp_buf);
+
+	return 0;
+#endif
+
 	*env_addr = code_offset + code_len;
 
 	free(tmp_buf);

Signature · 1 line

1.8.4.1

Pantelis Antoniou

2014-01-22 12:01 UTC #4 lore raw

PATCH v3 3/3 eSDHC: Calculate envaddr accroding to the address format

Hi Haijun,

Quoted 101 lines · Haijun Zhang

Signed-off-by Haijun Zhang <[email protected]>

---
changes for V3:
- Define quirk in SOC specific file instead of code in driver
changes for V2:
- Use 0xffffffffu instead of UINT_MAX

arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
board/freescale/common/sdhc_boot.c | 29 +++++++++++++++++++++++++++++

2 files changed, 32 insertions(+)

arch/powerpc/include/asm/config_mpc85xx.h +3 -0

index 15affdc..e8bd76a 100644
@@ -152,6 +152,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)

@@ -552,6 +553,7 @@
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_BSC9132)
 #define CONFIG_MAX_CPUS			2

@@ -575,6 +577,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
+#define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define CONFIG_E6500

board/freescale/common/sdhc_boot.c +29 -0

index f6e2b2b..022f38b 100644
@@ -16,6 +16,8 @@
 #define ESDHC_BOOT_IMAGE_SIZE	0x48
 #define ESDHC_BOOT_IMAGE_ADDR	0x50
 
+#define ESDHC_DEFAULT_ENVADDR	0x400
+
 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
 {
 	u8 *tmp_buf;

@@ -39,6 +41,33 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
 	/* Get the code size from offset 0x48 */
 	code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
 
+#ifdef CONFIG_ESDHC_HC_BLK_ADDR
+	/*
+	 * On soc BSC9131, BSC9132:
+	 * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
+	 * code length of these soc specify the memory address in block address
+	 * format. Block length is fixed to 512 bytes as per the SD High
+	 * Capacity specification.
+	 */
+	u64 tmp;
+
+	if (mmc->high_capacity) {
+		tmp = (u64)code_offset * blklen;
+		tmp += code_len * blklen;
+	} else
+		tmp = code_offset + code_len;
+
+	if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) ||
+			(tmp > 0xFFFFFFFFU))
+		*env_addr = ESDHC_DEFAULT_ENVADDR;
+	else
+		*env_addr = tmp;
+
+	free(tmp_buf);
+
+	return 0;
+#endif
+
 	*env_addr = code_offset + code_len;
 
 	free(tmp_buf);

Signature · 1 line

1.8.4.1

Acked-by Pantelis Antoniou <[email protected]>

York Sun

2014-01-21 22:01 UTC #5 lore raw

PATCH v3 1/3 esdhc: Workaround for card can't be detected on T4240QDS

In reply to Haijun Zhang

Pantelis,

Quoted 9 lines · Haijun Zhang

Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.
This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0.

Quoted 7 lines

Signed-off-by Haijun Zhang <[email protected]>
---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- Add the judgement condition for this broken card

I think this set of patches are in your backyard. If you ack them, I can apply them to mpc85xx.

http://patchwork.ozlabs.org/patch/309168/
http://patchwork.ozlabs.org/patch/309167/
http://patchwork.ozlabs.org/patch/309170/

York

Pantelis Antoniou

2014-01-22 12:01 UTC #6 lore raw

PATCH v3 1/3 esdhc: Workaround for card can't be detected on T4240QDS

Hi York,

Quoted 20 lines · York Sun

Pantelis,
Quoted 9 lines · Haijun Zhang
Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.
This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0.
Quoted 7 lines
Signed-off-by Haijun Zhang <[email protected]>
---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- Add the judgement condition for this broken card

Quoted 3 lines

I think this set of patches are in your backyard. If you ack them, I can apply them to mpc85xx.

Go ahead please.

Quoted 6 lines

http://patchwork.ozlabs.org/patch/309168/
http://patchwork.ozlabs.org/patch/309167/
http://patchwork.ozlabs.org/patch/309170/
York

Regards

-- Pantelis

Zhang Haijun

2014-01-23 01:58 UTC #7 lore raw

PATCH v3 1/3 esdhc: Workaround for card can't be detected on T4240QDS

Many thanks.

Pantelis and York

How about below patch?

http://patchwork.ozlabs.org/patch/283002/

It's about esdhc, but is in york's backyard.

Regards

Haijun

Quoted 40 lines · Pantelis Antoniou

Hi York,
Quoted 19 lines · York Sun
Pantelis,
Quoted 9 lines · Haijun Zhang
Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.
This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0.
Quoted 7 lines
Signed-off-by Haijun Zhang <[email protected]>
---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- Add the judgement condition for this broken card
Quoted 3 lines
I think this set of patches are in your backyard. If you ack them, I can apply them to mpc85xx.
Go ahead please.
Quoted 6 lines
http://patchwork.ozlabs.org/patch/309168/
http://patchwork.ozlabs.org/patch/309167/
http://patchwork.ozlabs.org/patch/309170/
York
Regards
-- Pantelis

Pantelis Antoniou

2014-01-22 12:00 UTC #8 lore raw

PATCH v3 1/3 esdhc: Workaround for card can't be detected on T4240QDS

In reply to Haijun Zhang

Hi Haijun,

Quoted 62 lines · Haijun Zhang

Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.
This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0.
Signed-off-by Haijun Zhang <[email protected]>
---
changes for V3:
- Define quirk in board specific file instead of code in driver
changes for V2:
- Add the judgement condition for this broken card
drivers/mmc/fsl_esdhc.c | 4 ++++
include/configs/T4240QDS.h | 5 +++++
2 files changed, 9 insertions(+)
drivers/mmc/fsl_esdhc.c +4 -0
index e522a70..2ee93cd 100644
@@ -548,6 +548,10 @@ static int esdhc_getcd(struct mmc *mmc)
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 	int timeout = 1000;
 
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+	if (CONFIG_ESDHC_DETECT_QUIRK)
+		return 1;
+#endif
 	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 		udelay(1000);
 
include/configs/T4240QDS.h +5 -0
index c96df54..0e0b346 100644
@@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BRDCFG5			0x55
+#define QIXIS_MUX_SDHC			2
 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
 
 #define CONFIG_SYS_CSPR3_EXT	(0xf)
@@ -466,6 +468,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
+	IS_SVR_REV(get_svr(), 1, 0))
 #endif
 
 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
Signature · 1 line
1.8.4.1

Acked-by Pantelis Antoniou <[email protected]>