arm64 patch

new file mode 100644
index 0000000..599aa8f

arch/arm/cpu/armv8/gic.S new file +106 -0

@@ -0,0 +1,106 @@
+/*
+ * GIC Initialization Routines.
+ *
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/gic.h>
+
+
+/*************************************************************************
+ *
+ * void gic_init(void) __attribute__((weak));
+ *
+ * Currently, this routine only initialize secure copy of GIC
+ * with Security Extensions at EL3.
+ *
+ *************************************************************************/
+WEAK(gic_init)
+	branch_if_slave	x0, 2f
+
+	/* Initialize Distributor and SPIs */
+	ldr	x1, =GICD_BASE
+	mov	w0, #0x3		/* EnableGrp0 | EnableGrp1 */
+	str	w0, [x1, GICD_CTLR]	/* Secure GICD_CTLR */
+	ldr	w0, [x1, GICD_TYPER]
+	and	w2, w0, #0x1f		/* ITLinesNumber */
+	cbz	w2, 2f			/* No SPIs */
+	add	x1, x1, (GICD_IGROUPRn + 4)
+	mov	w0, #~0			/* Config SPIs as Grp1 */
+1:	str	w0, [x1], #0x4
+	sub	w2, w2, #0x1
+	cbnz	w2, 1b
+
+	/* Initialize SGIs and PPIs */
+2:	ldr	x1, =GICD_BASE
+	mov	w0, #~0			/* Config SGIs and PPIs as Grp1 */
+	str	w0, [x1, GICD_IGROUPRn]	/* GICD_IGROUPR0 */
+	mov	w0, #0x1		/* Enable SGI 0 */
+	str	w0, [x1, GICD_ISENABLERn]
+
+	/* Initialize Cpu Interface */
+	ldr	x1, =GICC_BASE
+	mov	w0, #0x1e7		/* Disable IRQ/FIQ Bypass & */
+					/* Enable Ack Group1 Interrupt & */
+					/* EnableGrp0 & EnableGrp1 */
+	str	w0, [x1, GICC_CTLR]	/* Secure GICC_CTLR */
+
+	mov	w0, #0x1 << 7		/* Non-Secure access to GICC_PMR */
+	str	w0, [x1, GICC_PMR]
+
+	ret
+ENDPROC(gic_init)
+
+
+/*************************************************************************
+ *
+ * void gic_send_sgi(u64 sgi) __attribute__((weak));
+ *
+ *************************************************************************/
+WEAK(gic_send_sgi)
+	ldr	x1, =GICD_BASE
+	mov	w2, #0x8000
+	movk	w2, #0x100, lsl #16
+	orr	w2, w2, w0
+	str	w2, [x1, GICD_SGIR]
+	ret
+ENDPROC(gic_send_sgi)
+
+
+/*************************************************************************
+ *
+ * void wait_for_wakeup(void) __attribute__((weak));
+ *
+ * Wait for SGI 0 from master.
+ *
+ *************************************************************************/
+WEAK(wait_for_wakeup)
+	ldr	x1, =GICC_BASE
+0:	wfi
+	ldr	w0, [x1, GICC_AIAR]
+	str	w0, [x1, GICC_AEOIR]
+	cbnz	w0, 0b
+	ret
+ENDPROC(wait_for_wakeup)
+
+
+/*************************************************************************
+ *
+ * void smp_kick_all_cpus(void) __attribute__((weak));
+ *
+ *************************************************************************/
+WEAK(smp_kick_all_cpus)
+	/* Kick secondary cpus up by SGI 0 interrupt */
+	mov	x0, xzr			/* SGI 0 */
+	mov	x29, lr			/* Save LR */
+	bl	gic_send_sgi
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(smp_kick_all_cpus)

arch/arm/cpu/armv8/start.S new file +63 -0

new file mode 100644
index 0000000..bcc2603
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/armv8/mmu.h>
+
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ *************************************************************************/
+
+.globl	_start
+_start:
+	b	reset
+
+	.align 3
+
+.globl	_TEXT_BASE
+_TEXT_BASE:
+	.quad	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the linker script.
+ */
+.globl	_end_ofs
+_end_ofs:
+	.quad	_end - _start
+
+.globl	_bss_start_ofs
+_bss_start_ofs:
+	.quad	__bss_start - _start
+
+.globl	_bss_end_ofs
+_bss_end_ofs:
+	.quad	__bss_end - _start
+
+reset:
+	/*
+	 * Could be EL3/EL2/EL1, Initial State:
+	 * Little Endian, MMU Disabled, i/dCache Disabled
+	 */
+	adr	x0, vectors
+	switch_el x1, 3f, 2f, 1f
+3:	msr	vbar_el3, x0
+	msr	cptr_el3, xzr			/* Enable FP/SIMD */
+	ldr	x0, =COUNTER_FREQUENCY
+	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
+	b	0f
+2:	msr	vbar_el2, x0
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0			/* Enable FP/SIMD */
+	b	0f
+1:	msr	vbar_el1, x0
+	mov	x0, #3 << 20

arch/arm/cpu/armv8/start.S new file +12 -0

+
+	branch_if_master x0, x1, master_cpu
+
+	/*
+	 * Slave CPUs
+	 */
+slave_cpu:
+	wfe
+	ldr	x1, =CPU_RELEASE_ADDR
+	ldr	x0, [x1]
+	cbz	x0, slave_cpu
+	br	x0			/* branch to the given address */

arch/arm/cpu/armv8/start.S new file +69 -0

+	/* Initialize GIC Secure Bank Status */
+	mov	x29, lr			/* Save LR */
+	bl	gic_init
+
+	branch_if_master x0, x1, 1f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent salves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+	bl	wait_for_wakeup
+
+	/*
+	 * All processors will enter EL2 and optionally EL1.
+	 */
+	bl	armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl	armv8_switch_to_el1
+#endif
+
+1:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
+
+/*-----------------------------------------------------------------------*/
+
+ENTRY(c_runtime_cpu_setup)
+	/* If I-cache is enabled invalidate it */
+#ifndef CONFIG_SYS_ICACHE_OFF
+	ic	iallu			/* I+BTB cache invalidate */
+	isb	sy
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/*
+	 * Setup MAIR and TCR.
+	 */
+	ldr	x0, =MEMORY_ATTRIBUTES
+	ldr	x1, =TCR_FLAGS
+
+	switch_el x2, 3f, 2f, 1f
+3:	orr	x1, x1, TCR_EL3_IPS_BITS
+	msr	mair_el3, x0
+	msr	tcr_el3, x1
+	b	0f
+2:	orr	x1, x1, TCR_EL2_IPS_BITS
+	msr	mair_el2, x0
+	msr	tcr_el2, x1
+	b	0f
+1:	orr	x1, x1, TCR_EL1_IPS_BITS
+	msr	mair_el1, x0
+	msr	tcr_el1, x1
+0:
+#endif
+
+	/* Relocate vBAR */
+	adr	x0, vectors
+	switch_el x1, 3f, 2f, 1f
+3:	msr	vbar_el3, x0
+	b	0f
+2:	msr	vbar_el2, x0
+	b	0f
+1:	msr	vbar_el1, x0
+0:
+
+	ret
+ENDPROC(c_runtime_cpu_setup)

arch/arm/cpu/armv8/tlb.S new file +34 -0

new file mode 100644
index 0000000..f840b04
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*
+ * void __asm_invalidate_tlb_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+ENTRY(__asm_invalidate_tlb_all)
+	switch_el x9, 3f, 2f, 1f
+3:	tlbi	alle3
+	dsb	sy
+	isb
+	b	0f
+2:	tlbi	alle2
+	dsb	sy
+	isb
+	b	0f
+1:	tlbi	vmalle1
+	dsb	sy
+	isb
+0:
+	ret
+ENDPROC(__asm_invalidate_tlb_all)

arch/arm/cpu/armv8/transition.S new file +4 -0

new file mode 100644
index 0000000..e0a5946
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *

arch/arm/cpu/armv8/transition.S new file +69 -0

+	switch_el x0, 1f, 0f, 0f
+0:	ret
+1:
+	mov	x0, #0x5b1	/* Non-secure EL0/EL1 | HVC | 64bit EL2 */
+	msr	scr_el3, x0
+	msr	cptr_el3, xzr	/* Disable coprocessor traps to EL3 */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0	/* Disable coprocessor traps to EL2 */
+
+	/* Initialize SCTLR_EL2 */
+	msr	sctlr_el2, xzr
+
+	/* Return to the EL2_SP2 mode from EL3 */
+	mov	x0, sp
+	msr	sp_el2, x0	/* Migrate SP */
+	mrs	x0, vbar_el3
+	msr	vbar_el2, x0	/* Migrate VBAR */
+	mov	x0, #0x3c9
+	msr	spsr_el3, x0	/* EL2_SP2 | D | A | I | F */
+	msr	elr_el3, lr
+	eret
+ENDPROC(armv8_switch_to_el2)
+
+ENTRY(armv8_switch_to_el1)
+	switch_el x0, 0f, 1f, 0f
+0:	ret
+1:
+	/* Initialize Generic Timers */
+	mrs	x0, cnthctl_el2
+	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
+	msr	cnthctl_el2, x0
+	msr	cntvoff_el2, x0
+	mrs	x0, cntkctl_el1
+	orr	x0, x0, #0x3		/* Enable EL0 access to timers */
+	msr	cntkctl_el1, x0
+
+	/* Initilize MPID/MPIDR registers */
+	mrs	x0, midr_el1
+	mrs	x1, mpidr_el1
+	msr	vpidr_el2, x0
+	msr	vmpidr_el2, x1
+
+	/* Disable coprocessor traps */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0		/* Disable coprocessor traps to EL2 */
+	msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0		/* Enable FP/SIMD at EL1 */
+
+	/* Initialize HCR_EL2 */
+	mov	x0, #(1 << 31)		/* 64bit EL1 */
+	orr	x0, x0, #(1 << 29)	/* Disable HVC */
+	msr	hcr_el2, x0
+
+	/* SCTLR_EL1 initialization */
+	mov	x0, #0x0800
+	movk	x0, #0x30d0, lsl #16
+	msr	sctlr_el1, x0
+
+	/* Return to the EL1_SP1 mode from EL2 */
+	mov	x0, sp
+	msr	sp_el1, x0		/* Migrate SP */
+	mrs	x0, vbar_el2
+	msr	vbar_el1, x0		/* Migrate VBAR */
+	mov	x0, #0x3c5
+	msr	spsr_el2, x0		/* EL1_SP1 | D | A | I | F */
+	msr	elr_el2, lr
+	eret
+ENDPROC(armv8_switch_to_el1)

arch/arm/cpu/armv8/u-boot.lds new file +89 -0

new file mode 100644
index 0000000..4c12222
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(8);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(8);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(8);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(8);
+
+	. = .;
+
+	. = ALIGN(8);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(8);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	. = ALIGN(8);
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rela.dyn : {
+		*(.rela*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	_end = .;
+
+	. = ALIGN(8);
+
+	.bss_start : {
+		KEEP(*(.__bss_start));
+	}
+
+	.bss : {
+		*(.bss*)
+		 . = ALIGN(8);
+	}
+
+	.bss_end : {
+		KEEP(*(.__bss_end));
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}

arch/arm/include/asm/armv8/mmu.h new file +111 -0

new file mode 100644
index 0000000..1193e76
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_MMU_H_
+#define _ASM_ARMV8_MMU_H_
+
+#ifdef __ASSEMBLY__
+#define _AC(X, Y)	X
+#else
+#define _AC(X, Y)	(X##Y)
+#endif
+
+#define UL(x)		_AC(x, UL)
+
+/***************************************************************/
+/*
+ * The following definitions are related each other, shoud be
+ * calculated specifically.
+ */
+#define VA_BITS			(42)	/* 42 bits virtual address */
+
+/* PAGE_SHIFT determines the page size */
+#undef  PAGE_SIZE
+#define PAGE_SHIFT		16
+#define PAGE_SIZE		(1 << PAGE_SHIFT)
+#define PAGE_MASK		(~(PAGE_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT		29
+#define SECTION_SIZE		(UL(1) << SECTION_SHIFT)
+#define SECTION_MASK		(~(SECTION_SIZE-1))
+/***************************************************************/
+
+/*
+ * Memory types
+ */
+#define MT_DEVICE_NGNRNE	0
+#define MT_DEVICE_NGNRE		1
+#define MT_DEVICE_GRE		2
+#define MT_NORMAL_NC		3
+#define MT_NORMAL		4
+
+#define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE*8)) |	\
+				(0x04 << (MT_DEVICE_NGNRE*8)) |		\
+				(0x0c << (MT_DEVICE_GRE*8)) |		\
+				(0x44 << (MT_NORMAL_NC*8)) |		\
+				(UL(0xff) << (MT_NORMAL*8)))
+
+/*
+ * Hardware page table definitions.
+ *
+ * Level 2 descriptor (PMD).
+ */
+#define PMD_TYPE_MASK		(3 << 0)
+#define PMD_TYPE_FAULT		(0 << 0)
+#define PMD_TYPE_TABLE		(3 << 0)
+#define PMD_TYPE_SECT		(1 << 0)
+
+/*
+ * Section
+ */
+#define PMD_SECT_S		(3 << 8)
+#define PMD_SECT_AF		(1 << 10)
+#define PMD_SECT_NG		(1 << 11)
+#define PMD_SECT_PXN		(UL(1) << 53)
+#define PMD_SECT_UXN		(UL(1) << 54)
+
+/*
+ * AttrIndx[2:0]
+ */
+#define PMD_ATTRINDX(t)		((t) << 2)
+#define PMD_ATTRINDX_MASK	(7 << 2)
+
+/*
+ * TCR flags.
+ */
+#define TCR_T0SZ(x)		((64 - (x)) << 0)
+#define TCR_IRGN_NC		(0 << 8)
+#define TCR_IRGN_WBWA		(1 << 8)
+#define TCR_IRGN_WT		(2 << 8)
+#define TCR_IRGN_WBNWA		(3 << 8)
+#define TCR_IRGN_MASK		(3 << 8)
+#define TCR_ORGN_NC		(0 << 10)
+#define TCR_ORGN_WBWA		(1 << 10)
+#define TCR_ORGN_WT		(2 << 10)
+#define TCR_ORGN_WBNWA		(3 << 10)
+#define TCR_ORGN_MASK		(3 << 10)
+#define TCR_SHARED_NON		(0 << 12)
+#define TCR_SHARED_OUTER	(1 << 12)
+#define TCR_SHARED_INNER	(2 << 12)
+#define TCR_TG0_4K		(0 << 14)
+#define TCR_TG0_64K		(1 << 14)
+#define TCR_TG0_16K		(2 << 14)
+#define TCR_EL1_IPS_BITS	(UL(3) << 32)	/* 42 bits physical address */
+#define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
+#define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
+
+/* PTWs cacheable, inner/outer WBWA and non-shareable */
+#define TCR_FLAGS		(TCR_TG0_64K |		\
+				TCR_SHARED_NON |	\
+				TCR_ORGN_WBWA |		\
+				TCR_IRGN_WBWA |		\
+				TCR_T0SZ(VA_BITS))
+
+#endif /* _ASM_ARMV8_MMU_H_ */

arch/arm/include/asm/byteorder.h +12 -0

index c3489f1..71a9966 100644
@@ -23,10 +23,22 @@
  #  define __SWAB_64_THRU_32__
  #endif
 
+#ifdef	CONFIG_ARM64
+
+#ifdef __AARCH64EB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#else	/* CONFIG_ARM64 */
+
  #ifdef __ARMEB__
  #include <linux/byteorder/big_endian.h>
  #else
  #include <linux/byteorder/little_endian.h>
  #endif
 
+#endif	/* CONFIG_ARM64 */
+
  #endif

arch/arm/include/asm/cache.h +5 -0

index 6d60a4a..ddebbc8 100644
@@ -11,6 +11,8 @@
 
  #include <asm/system.h>
 
+#ifndef CONFIG_ARM64
+
  /*
   * Invalidate L2 Cache using co-proc instruction
   */

@@ -28,6 +30,9 @@ void l2_cache_disable(void);
  void set_section_dcache(int section, enum dcache_option option);
 
  void dram_bank_mmu_setup(int bank);
+
+#endif
+
  /*
   * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
   * use that value for aligning DMA buffers unless the board config has specified

arch/arm/include/asm/config.h +6 -0

index 99b703e..abf79e5 100644
@@ -9,4 +9,10 @@
 
  #define CONFIG_LMB
  #define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#ifdef CONFIG_ARM64
+#define CONFIG_PHYS_64BIT
+#define CONFIG_STATIC_RELA
+#endif
+
  #endif

arch/arm/include/asm/gic.h +42 -7

index a0891cc..ac2b2bf 100644
@@ -1,19 +1,54 @@
-#ifndef __GIC_V2_H__
-#define __GIC_V2_H__
+#ifndef __GIC_H__
+#define __GIC_H__
 
-/* register offsets for the ARM generic interrupt controller (GIC) */
+/* Register offsets for the ARM generic interrupt controller (GIC) */
 
  #define GIC_DIST_OFFSET		0x1000
+#define GIC_CPU_OFFSET_A9	0x0100
+#define GIC_CPU_OFFSET_A15	0x2000
+
+/* Distributor Registers */
  #define GICD_CTLR		0x0000
  #define GICD_TYPER		0x0004
+#define GICD_IIDR		0x0008
+#define GICD_STATUSR		0x0010
+#define GICD_SETSPI_NSR		0x0040
+#define GICD_CLRSPI_NSR		0x0048
+#define GICD_SETSPI_SR		0x0050
+#define GICD_CLRSPI_SR		0x0058
+#define GICD_SEIR		0x0068
  #define GICD_IGROUPRn		0x0080
-#define GICD_SGIR		0x0F00
+#define GICD_ISENABLERn		0x0100
+#define GICD_ICENABLERn		0x0180
+#define GICD_ISPENDRn		0x0200
+#define GICD_ICPENDRn		0x0280
+#define GICD_ISACTIVERn		0x0300
+#define GICD_ICACTIVERn		0x0380
+#define GICD_IPRIORITYRn	0x0400
+#define GICD_ITARGETSRn		0x0800
+#define GICD_ICFGR		0x0c00
+#define GICD_IGROUPMODRn	0x0d00
+#define GICD_NSACRn		0x0e00
+#define GICD_SGIR		0x0f00
+#define GICD_CPENDSGIRn		0x0f10
+#define GICD_SPENDSGIRn		0x0f20
+#define GICD_IROUTERn		0x6000
 
-#define GIC_CPU_OFFSET_A9	0x0100
-#define GIC_CPU_OFFSET_A15	0x2000
+/* Cpu Interface Memory Mapped Registers */
  #define GICC_CTLR		0x0000
  #define GICC_PMR		0x0004
+#define GICC_BPR		0x0008
  #define GICC_IAR		0x000C
  #define GICC_EOIR		0x0010
+#define GICC_RPR		0x0014
+#define GICC_HPPIR		0x0018
+#define GICC_ABPR		0x001c
+#define GICC_AIAR		0x0020
+#define GICC_AEOIR		0x0024
+#define GICC_AHPPIR		0x0028
+#define GICC_APRn		0x00d0
+#define GICC_NSAPRn		0x00e0
+#define GICC_IIDR		0x00fc
+#define GICC_DIR		0x1000
 
-#endif
+#endif /* __GIC_H__ */

arch/arm/include/asm/global_data.h +5 -1

index e126436..60e8726 100644
@@ -47,6 +47,10 @@ struct arch_global_data {
 
  #include <asm-generic/global_data.h>
 
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r9")
+#ifdef CONFIG_ARM64
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("x18")
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r9")
+#endif
 
  #endif /* __ASM_GBL_DATA_H */

arch/arm/include/asm/io.h +9 -6

index 1fbc531..6a1f05a 100644
@@ -75,42 +75,45 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
  #define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
  #define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
 
-extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
+extern inline void __raw_writesb(unsigned long addr, const void *data,
+				 int bytelen)
  {
  	uint8_t *buf = (uint8_t *)data;
  	while(bytelen--)
  		__arch_putb(*buf++, addr);
  }
 
-extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
+extern inline void __raw_writesw(unsigned long addr, const void *data,
+				 int wordlen)
  {
  	uint16_t *buf = (uint16_t *)data;
  	while(wordlen--)
  		__arch_putw(*buf++, addr);
  }
 
-extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
+extern inline void __raw_writesl(unsigned long addr, const void *data,
+				 int longlen)
  {
  	uint32_t *buf = (uint32_t *)data;
  	while(longlen--)
  		__arch_putl(*buf++, addr);
  }
 
-extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
+extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
  {
  	uint8_t *buf = (uint8_t *)data;
  	while(bytelen--)
  		*buf++ = __arch_getb(addr);
  }
 
-extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
+extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
  {
  	uint16_t *buf = (uint16_t *)data;
  	while(wordlen--)
  		*buf++ = __arch_getw(addr);
  }
 
-extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
+extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
  {
  	uint32_t *buf = (uint32_t *)data;
  	while(longlen--)

arch/arm/include/asm/macro.h +53 -0

index ff13f36..f77e4b8 100644
@@ -54,5 +54,58 @@
  	bcs	1b
  .endm
 
+#ifdef CONFIG_ARM64
+/*
+ * Register aliases.
+ */
+lr	.req	x30
+
+/*
+ * Branch according to exception level
+ */
+.macro	switch_el, xreg, el3_label, el2_label, el1_label
+	mrs	\xreg, CurrentEL
+	cmp	\xreg, 0xc
+	b.eq	\el3_label
+	cmp	\xreg, 0x8
+	b.eq	\el2_label
+	cmp	\xreg, 0x4
+	b.eq	\el1_label
+.endm
+
+/*
+ * Branch if current processor is a slave,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_slave, xreg, slave_label
+	mrs	\xreg, mpidr_el1
+	tst	\xreg, #0xff		/* Test Affinity 0 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 1 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 2 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #16
+	tst	\xreg, #0xff		/* Test Affinity 3 */
+	b.ne	\slave_label
+.endm
+
+/*
+ * Branch if current processor is a master,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_master, xreg1, xreg2, master_label
+	mrs	\xreg1, mpidr_el1
+	lsr	\xreg2, \xreg1, #32
+	lsl	\xreg1, \xreg1, #40
+	lsr	\xreg1, \xreg1, #40
+	orr	\xreg1, \xreg1, \xreg2
+	cbz	\xreg1, \master_label
+.endm
+
+#endif /* CONFIG_ARM64 */
+
  #endif /* __ASSEMBLY__ */
  #endif /* __ASM_ARM_MACRO_H__ */

arch/arm/include/asm/posix_types.h +10 -0

index c412486..9ba9add 100644
@@ -13,6 +13,8 @@
  #ifndef __ARCH_ARM_POSIX_TYPES_H
  #define __ARCH_ARM_POSIX_TYPES_H
 
+#include <config.h>
+
  /*
   * This file is generally used by user-level software, so you need to
   * be a little careful about namespace pollution etc.  Also, we cannot

@@ -28,9 +30,17 @@ typedef int			__kernel_pid_t;
  typedef unsigned short		__kernel_ipc_pid_t;
  typedef unsigned short		__kernel_uid_t;
  typedef unsigned short		__kernel_gid_t;
+
+#ifdef	CONFIG_ARM64
+typedef unsigned long		__kernel_size_t;
+typedef long			__kernel_ssize_t;
+typedef long			__kernel_ptrdiff_t;
+#else	/* CONFIG_ARM64 */
  typedef unsigned int		__kernel_size_t;
  typedef int			__kernel_ssize_t;
  typedef int			__kernel_ptrdiff_t;
+#endif	/* CONFIG_ARM64 */
+
  typedef long			__kernel_time_t;
  typedef long			__kernel_suseconds_t;
  typedef long			__kernel_clock_t;

arch/arm/include/asm/proc-armv/ptrace.h +21 -0

index a060ee6..21aef58 100644
@@ -10,6 +10,25 @@
  #ifndef __ASM_PROC_PTRACE_H
  #define __ASM_PROC_PTRACE_H
 
+#ifdef CONFIG_ARM64
+
+#define PCMASK		0
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored
+ * on the stack during an exception.
+ */
+struct pt_regs {
+	unsigned long elr;
+	unsigned long regs[31];
+};
+
+#endif	/* __ASSEMBLY__ */
+
+#else	/* CONFIG_ARM64 */
+
  #define USR26_MODE	0x00
  #define FIQ26_MODE	0x01
  #define IRQ26_MODE	0x02

@@ -104,4 +123,6 @@ static inline int valid_user_regs(struct pt_regs *regs)
 
  #endif	/* __ASSEMBLY__ */
 
+#endif	/* CONFIG_ARM64 */
+
  #endif

arch/arm/include/asm/proc-armv/system.h +58 -1

index cda8976..693d1f4 100644
@@ -13,6 +13,60 @@
  /*
   * Save the current interrupt enable state & disable IRQs
   */
+#ifdef CONFIG_ARM64
+
+/*
+ * Save the current interrupt enable state
+ * and disable IRQs/FIQs
+ */
+#define local_irq_save(flags)					\
+	({							\
+	asm volatile(						\
+	"mrs	%0, daif"					\
+	"msr	daifset, #3"					\
+	: "=r" (flags)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(flags)				\
+	({							\
+	asm volatile(						\
+	"msr	daif, %0"					\
+	:							\
+	: "r" (flags)						\
+	: "memory");						\
+	})
+
+/*
+ * Enable IRQs/FIQs
+ */
+#define local_irq_enable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifclr, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable IRQs/FIQs
+ */
+#define local_irq_disable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifset, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+#else	/* CONFIG_ARM64 */
+
  #define local_irq_save(x)					\
  	({							\
  		unsigned long temp;				\

@@ -107,7 +161,10 @@
  	: "r" (x)						\
  	: "memory")
 
-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+#endif	/* CONFIG_ARM64 */
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
+	defined(CONFIG_ARM64)
  /*
   * On the StrongARM, "swp" is terminally broken since it bypasses the
   * cache totally.  This means that the cache becomes inconsistent, and,

arch/arm/include/asm/system.h +84 -0

index 760345f..4178f8c 100644
@@ -1,6 +1,86 @@
  #ifndef __ASM_ARM_SYSTEM_H
  #define __ASM_ARM_SYSTEM_H
 
+#ifdef CONFIG_ARM64
+
+/*
+ * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
+ */
+#define CR_M		(1 << 0)	/* MMU enable			*/
+#define CR_A		(1 << 1)	/* Alignment abort enable	*/
+#define CR_C		(1 << 2)	/* Dcache enable		*/
+#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
+#define CR_I		(1 << 12)	/* Icache enable		*/
+#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
+#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
+
+#define PGTABLE_SIZE	(0x10000)
+
+#ifndef __ASSEMBLY__
+
+#define isb()				\
+	({asm volatile(			\
+	"isb" : : : "memory");		\
+	})
+
+#define wfi()				\
+	({asm volatile(			\
+	"wfi" : : : "memory");		\
+	})
+
+static inline unsigned int current_el(void)
+{
+	unsigned int el;
+	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
+	return el >> 2;
+}
+
+static inline unsigned int get_sctlr(void)
+{
+	unsigned int el, val;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+	else if (el == 2)
+		asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
+	else
+		asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
+
+	return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+	unsigned int el;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+	else if (el == 2)
+		asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
+	else
+		asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
+
+	asm volatile("isb");
+}
+
+void __asm_flush_dcache_all(void);
+void __asm_flush_dcache_range(u64 start, u64 end);
+void __asm_invalidate_tlb_all(void);
+void __asm_invalidate_icache_all(void);
+
+void armv8_switch_to_el2(void);
+void armv8_switch_to_el1(void);
+void gic_init(void);
+void gic_send_sgi(unsigned long sgino);
+void wait_for_wakeup(void);
+void smp_kick_all_cpus(void);
+
+#endif	/* __ASSEMBLY__ */
+
+#else /* CONFIG_ARM64 */
+
  #ifdef __KERNEL__
 
  #define CPU_ARCH_UNKNOWN	0

@@ -45,6 +125,8 @@
  #define CR_AFE	(1 << 29)	/* Access flag enable			*/
  #define CR_TE	(1 << 30)	/* Thumb exception enable		*/
 
+#define PGTABLE_SIZE		(4096 * 4)
+
  /*
   * This is used to ensure the compiler did actually allocate the register we
   * asked it for some inline assembly sequences.  Apparently we can't trust

@@ -132,4 +214,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
 
  #endif /* __KERNEL__ */
 
+#endif /* CONFIG_ARM64 */
+
  #endif

arch/arm/include/asm/types.h +4 -0

index 71dc049..2326420 100644
@@ -39,7 +39,11 @@ typedef unsigned int u32;
  typedef signed long long s64;
  typedef unsigned long long u64;
 
+#ifdef	CONFIG_ARM64
+#define BITS_PER_LONG 64
+#else	/* CONFIG_ARM64 */
  #define BITS_PER_LONG 32
+#endif	/* CONFIG_ARM64 */
 
  /* Dma addresses are 32-bits wide.  */
 

arch/arm/include/asm/u-boot.h +4 -0

index 2b5fce8..cb81232 100644
@@ -44,6 +44,10 @@ typedef struct bd_info {
  #endif /* !CONFIG_SYS_GENERIC_BOARD */
 
  /* For image.h:image_check_target_arch() */
+#ifndef CONFIG_ARM64
  #define IH_ARCH_DEFAULT IH_ARCH_ARM
+#else
+#define IH_ARCH_DEFAULT IH_ARCH_ARM64
+#endif
 
  #endif	/* _U_BOOT_H_ */

arch/arm/include/asm/unaligned.h +1 -1

index 44593a8..0a228fb 100644
@@ -8,7 +8,7 @@
  /*
   * Select endianness
   */
-#ifndef __ARMEB__
+#if __BYTE_ORDER == __LITTLE_ENDIAN
  #define get_unaligned	__get_unaligned_le
  #define put_unaligned	__put_unaligned_le
  #else

arch/arm/lib/Makefile +17 -3

index 679f19a..321997c 100644
@@ -17,14 +17,22 @@ lib-y	+= _umodsi3.o
  lib-y	+= div0.o
  endif
 
-obj-y += crt0.o
+ifdef CONFIG_ARM64
+obj-y	+= crt0_64.o
+else
+obj-y	+= crt0.o
+endif
 
  ifndef CONFIG_SPL_BUILD
-obj-y += relocate.o
+ifdef CONFIG_ARM64
+obj-y	+= relocate_64.o
+else
+obj-y	+= relocate.o
+endif
  ifndef CONFIG_SYS_GENERIC_BOARD
  obj-y	+= board.o
  endif
-obj-y += sections.o
+obj-y	+= sections.o
 
  obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
  obj-$(CONFIG_CMD_BOOTM) += bootm.o

@@ -35,11 +43,17 @@ else
  obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
  endif
 
+ifdef CONFIG_ARM64
+obj-y	+= interrupts_64.o
+else
  obj-y	+= interrupts.o
+endif
  obj-y	+= reset.o
 
  obj-y	+= cache.o
+ifndef CONFIG_ARM64
  obj-y	+= cache-cp15.o
+endif
 
  # For EABI conformant tool chains, provide eabi_compat()
  ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))

arch/arm/lib/board.c +6 -1

index 34f50b0..c4904b4 100644
@@ -344,7 +344,7 @@ void board_init_f(ulong bootflag)
 
  #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  	/* reserve TLB table */
-	gd->arch.tlb_size = 4096 * 4;
+	gd->arch.tlb_size = PGTABLE_SIZE;
  	addr -= gd->arch.tlb_size;
 
  	/* round down to next 64 kB limit */

@@ -419,6 +419,7 @@ void board_init_f(ulong bootflag)
  	}
  #endif
 
+#ifndef CONFIG_ARM64
  	/* setup stackpointer for exeptions */
  	gd->irq_sp = addr_sp;
  #ifdef CONFIG_USE_IRQ

@@ -431,6 +432,10 @@ void board_init_f(ulong bootflag)
 
  	/* 8-byte alignment for ABI compliance */
  	addr_sp &= ~0x07;
+#else	/* CONFIG_ARM64 */
+	/* 16-byte alignment for ABI compliance */
+	addr_sp &= ~0x0f;
+#endif	/* CONFIG_ARM64 */
  #else
  	addr_sp += 128;	/* leave 32 words for abort-stack   */
  	gd->irq_sp = addr_sp;

arch/arm/lib/bootm.c +24 -0

index f476a89..77f1a5c 100644
@@ -196,6 +196,14 @@ static void do_nonsec_virt_switch(void)
  		debug("entered non-secure state\n");
  #endif
  #endif
+
+#ifdef CONFIG_ARM64
+	smp_kick_all_cpus();
+	armv8_switch_to_el2();
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	armv8_switch_to_el1();
+#endif
+#endif
  }
 
  /* Subcommand: PREP */

@@ -240,6 +248,21 @@ static void boot_prep_linux(bootm_headers_t *images)
  /* Subcommand: GO */
  static void boot_jump_linux(bootm_headers_t *images, int flag)
  {
+#ifdef CONFIG_ARM64
+	void (*kernel_entry)(void *fdt_addr);
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+	kernel_entry = (void (*)(void *fdt_addr))images->ep;
+
+	debug("## Transferring control to Linux (at address %lx)...\n",
+		(ulong) kernel_entry);
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+	announce_and_cleanup(fake);
+
+	if (!fake)
+		kernel_entry(images->ft_addr);
+#else
  	unsigned long machid = gd->bd->bi_arch_number;
  	char *s;
  	void (*kernel_entry)(int zero, int arch, uint params);

@@ -266,6 +289,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 
  	if (!fake)
  		kernel_entry(0, machid, r2);
+#endif
  }
 
  /* Main Entry point for arm bootm implementation

arch/arm/lib/crt0_64.S new file +113 -0

new file mode 100644
index 0000000..7756396
@@ -0,0 +1,113 @@
+/*
+ * crt0 - C-runtime startup Code for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *
+ * (C) Copyright 2012
+ * Albert ARIBAUD <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * This file handles the target-independent stages of the U-Boot
+ * start-up where a C runtime environment is needed. Its entry point
+ * is _main and is branched into from the target's start.S file.
+ *
+ * _main execution sequence is:
+ *
+ * 1. Set up initial environment for calling board_init_f().
+ *    This environment only provides a stack and a place to store
+ *    the GD ('global data') structure, both located in some readily
+ *    available RAM (SRAM, locked cache...). In this context, VARIABLE
+ *    global data, initialized or not (BSS), are UNAVAILABLE; only
+ *    CONSTANT initialized data are available.
+ *
+ * 2. Call board_init_f(). This function prepares the hardware for
+ *    execution from system RAM (DRAM, DDR...) As system RAM may not
+ *    be available yet, , board_init_f() must use the current GD to
+ *    store any data which must be passed on to later stages. These
+ *    data include the relocation destination, the future stack, and
+ *    the future GD location.
+ *
+ * (the following applies only to non-SPL builds)
+ *
+ * 3. Set up intermediate environment where the stack and GD are the
+ *    ones allocated by board_init_f() in system RAM, but BSS and
+ *    initialized non-const data are still not available.
+ *
+ * 4. Call relocate_code(). This function relocates U-Boot from its
+ *    current location into the relocation destination computed by
+ *    board_init_f().
+ *
+ * 5. Set up final environment for calling board_init_r(). This
+ *    environment has BSS (initialized to 0), initialized non-const
+ *    data (initialized to their intended value), and stack in system
+ *    RAM. GD has retained values set by board_init_f(). Some CPUs
+ *    have some work left to do at this point regarding memory, so
+ *    call c_runtime_cpu_setup.
+ *
+ * 6. Branch to board_init_r().
+ */
+
+ENTRY(_main)
+
+/*
+ * Set up initial C runtime environment and call board_init_f(0).
+ */
+	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
+	sub	x0, x0, #GD_SIZE	/* allocate one GD above SP */
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+	mov	x18, sp			/* GD is above SP */
+	mov	x0, #0
+	bl	board_init_f
+
+/*
+ * Set up intermediate environment (new sp and gd) and call
+ * relocate_code(addr_moni). Trick here is that we'll return
+ * 'here' but relocated.
+ */
+	ldr	x0, [x18, #GD_START_ADDR_SP]	/* x0 <- gd->start_addr_sp */
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+	ldr	x18, [x18, #GD_BD]		/* x18 <- gd->bd */
+	sub	x18, x18, #GD_SIZE		/* new GD is below bd */
+
+	adr	lr, relocation_return
+	ldr	x9, [x18, #GD_RELOC_OFF]	/* x9 <- gd->reloc_off */
+	add	lr, lr, x9	/* new return address after relocation */
+	ldr	x0, [x18, #GD_RELOCADDR]	/* x0 <- gd->relocaddr */
+	b	relocate_code
+
+relocation_return:
+
+/*
+ * Set up final (full) environment
+ */
+	bl	c_runtime_cpu_setup		/* still call old routine */
+
+/*
+ * Clear BSS section
+ */
+	ldr	x0, =__bss_start		/* this is auto-relocated! */
+	ldr	x1, =__bss_end			/* this is auto-relocated! */
+	mov	x2, #0
+clear_loop:
+	str	x2, [x0]
+	add	x0, x0, #8
+	cmp	x0, x1
+	b.lo	clear_loop
+
+	/* call board_init_r(gd_t *id, ulong dest_addr) */
+	mov	x0, x18				/* gd_t */
+	ldr	x1, [x18, #GD_RELOCADDR]	/* dest_addr */
+	b	board_init_r			/* PC relative jump */
+
+	/* NOTREACHED - board_init_r() does not return */
+
+ENDPROC(_main)

arch/arm/lib/interrupts_64.c new file +120 -0

new file mode 100644
index 0000000..b476722
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+	return;
+}
+
+int disable_interrupts(void)
+{
+	return 0;
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printf("ELR:     %lx\n", regs->elr);
+	printf("LR:      %lx\n", regs->regs[30]);
+	for (i = 0; i < 29; i += 2)
+		printf("x%-2d: %016lx x%-2d: %016lx\n",
+		       i, regs->regs[i], i+1, regs->regs[i+1]);
+	printf("\n");
+}
+
+/*
+ * do_bad_sync handles the impossible case in the Synchronous Abort vector.
+ */
+void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_irq handles the impossible case in the Irq vector.
+ */
+void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_fiq handles the impossible case in the Fiq vector.
+ */
+void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_error handles the impossible case in the Error vector.
+ */
+void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_sync handles the Synchronous Abort exception.
+ */
+void do_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_irq handles the Irq exception.
+ */
+void do_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Irq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_fiq handles the Fiq exception.
+ */
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Fiq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_error handles the Error exception.
+ * Errors are more likely to be processor specific,
+ * it is defined with weak attribute and can be redefined
+ * in processor specific code.
+ */
+void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Error\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}

arch/arm/lib/relocate_64.S new file +58 -0

new file mode 100644
index 0000000..7fba9e2
@@ -0,0 +1,58 @@
+/*
+ * relocate - common relocation function for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * Albert ARIBAUD <[email protected]>
+ * David Feng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+/*
+ * void relocate_code (addr_moni)
+ *
+ * This function relocates the monitor code.
+ * x0 holds the destination address.
+ */
+ENTRY(relocate_code)
+	/*
+	 * Copy u-boot from flash to RAM
+	 */
+	ldr	x1, =__image_copy_start	/* x1 <- SRC &__image_copy_start */
+	subs	x9, x0, x1		/* x9 <- relocation offset */
+	b.eq	relocate_done		/* skip relocation */
+	ldr	x2, =__image_copy_end	/* x2 <- SRC &__image_copy_end */
+
+copy_loop:
+	ldp	x10, x11, [x1], #16	/* copy from source address [x1] */
+	stp	x10, x11, [x0], #16	/* copy to   target address [x0] */
+	cmp	x1, x2			/* until source end address [x2] */
+	b.lo	copy_loop
+
+	/*
+	 * Fix .rela.dyn relocations
+	 */
+	ldr	x2, =__rel_dyn_start	/* x2 <- SRC &__rel_dyn_start */
+	ldr	x3, =__rel_dyn_end	/* x3 <- SRC &__rel_dyn_end */
+fixloop:
+	ldp	x0, x1, [x2], #16	/* (x0,x1) <- (SRC location, fixup) */
+	ldr	x4, [x2], #8		/* x4 <- addend */
+	and	x1, x1, #0xffffffff
+	cmp	x1, #1027		/* relative fixup? */
+	bne	fixnext
+
+	/* relative fix: store addend plus offset at dest location */
+	add	x0, x0, x9
+	add	x4, x4, x9
+	str	x4, [x0]
+fixnext:
+	cmp	x2, x3
+	b.lo	fixloop
+
+relocate_done:
+	ret
+ENDPROC(relocate_code)

common/image.c +1 -0

index b0ae58f..4145354 100644
@@ -81,6 +81,7 @@ static const table_entry_t uimage_arch[] = {
  	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
  	{	IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
  	{	IH_ARCH_SANDBOX,	"sandbox",	"Sandbox",	},
+	{	IH_ARCH_ARM64,		"arm64",	"AArch64",	},
  	{	-1,			"",		"",		},
  };
 

doc/README.arm64 new file +46 -0

new file mode 100644
index 0000000..75586db
@@ -0,0 +1,46 @@
+U-boot for arm64
+
+Summary
+=======
+No hardware platform of arm64 is available now. The u-boot is
+simulated on Foundation Model and Fast Model for ARMv8.
+
+Notes
+=====
+
+1. Currenly, u-boot run at the highest exception level processor
+   supported and jump to EL2 or optionally EL1 before enter OS.
+
+2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
+   use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
+   is used to encode the initial addend of rela to u-boot.bin. After running,
+   the u-boot will be relocated to destination again.
+
+3. Fdt should be placed at a 2-megabyte boundary and within the first 512
+   megabytes from the start of the kernel image. So, fdt_high should be
+   defined specially.
+   Please reference linux/Documentation/arm64/booting.txt for detail.
+
+4. Spin-table is used to wake up secondary processors. One location
+   (or per processor location) is defined to hold the kernel entry point
+   for secondary processors. It must be ensured that the location is
+   accessible and zero immediately after secondary processor
+   enter slave_cpu branch execution in start.S. The location address
+   is encoded in cpu node of DTS. Linux kernel store the entry point
+   of secondary processors to it and send event to wakeup secondary
+   processors.
+   Please reference linux/Documentation/arm64/booting.txt for detail.
+
+5. Generic board is supported.
+
+6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
+   aarch32 specific codes.
+
+Contributor
+===========
+   Tom Rini       <[email protected]>
+   Scott Wood     <[email protected]>
+   York Sun       <[email protected]>
+   Simon Glass    <[email protected]>
+   Sharma Bhupesh <[email protected]>
+   Rob Herring    <[email protected]>

examples/standalone/stubs.c +15 -0

index 8fb1765..fc5d7ef 100644
@@ -39,6 +39,20 @@ gd_t *global_data;
  "	bctr\n"				\
  	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11");
  #elif defined(CONFIG_ARM)
+#ifdef CONFIG_ARM64
+/*
+ * x18 holds the pointer to the global_data, x9 is a call-clobbered
+ * register
+ */
+#define EXPORT_FUNC(x) \
+	asm volatile (			\
+"	.globl " #x "\n"		\
+#x ":\n"				\
+"	ldr	x9, [x18, %0]\n"		\
+"	ldr	x9, [x9, %1]\n"		\
+"	br	x9\n"		\
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "x9");
+#else
  /*
   * r8 holds the pointer to the global_data, ip is a call-clobbered
   * register

@@ -50,6 +64,7 @@ gd_t *global_data;
  "	ldr	ip, [r8, %0]\n"		\
  "	ldr	pc, [ip, %1]\n"		\
  	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip");
+#endif
  #elif defined(CONFIG_MIPS)
  /*
   * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-

include/image.h +0 -0

index ee6eb8d..7de2bb2 100644

arch/arm/cpu/armv8/gic.S

Quoted 11 lines

arch/arm/cpu/armv8/generic_timer.c new file +10 -0

+/*
+ * Generic timer implementation of timer_read_counter()
+ */
+unsigned long timer_read_counter(void)
+{
+	unsigned long cntpct;
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	return cntpct;
+}

arch/arm/cpu/armv8/gic.S +0 -0

The ARMv8 foundation model has support for GICv2 while GICv3 is actually compatible to ARMv8. So although you mention in the cover letter that this is currently GICv2 support, now while trying to add GICv3 support it will be difficult to envision GICv2 code in 'arch/arm/cpu/armv8/' directory.

Infact GICv2 is compatible with ARMv7 and as secure and non-secure copies of GIC registers are equally applicable to ARMv7, would it make sense to keep the GICv2 code at a place where both ARMv7 and ARMv8 can use it?

Can we reuse something from [1] for GICv2:

[1]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonsec_virt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l88

arch/arm/cpu/armv8/gic.S

Quoted 7 lines

arch/arm/cpu/armv8/gic.S +7 -0

+	/* Cache/BPB/TLB Invalidate */
+	bl	__asm_flush_dcache_all		/* dCache clean&invalidate */
+	bl	__asm_invalidate_icache_all	/* iCache invalidate */
+	bl	__asm_invalidate_tlb_all	/* invalidate TLBs */
+
+	/* Processor specific initialization */
+	bl	lowlevel_init

Shouldn't this call be protected inside a
'#ifndef CONFIG_SKIP_LOWLEVEL_INIT'?

Quoted 1 line

+WEAK(lowlevel_init)

Ok, so this means that a specific SoC lowlevel_init implementation can override this generic implementation. Because I sure other secure/non-secure settings need to be put into place for ARM IPs like SMMU-500.

Quoted 1 line

+ENTRY(armv8_switch_to_el2)

Do we need a switch to Secure Monitor here? I am not able to relate how this with the present ARMv7 code (see [2]):

[2]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonsec_virt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l29

-----Original Message-----
From: FengHua [mailto:fenghua at phytium.com.cn]
Sent: Friday, November 29, 2013 7:05 PM
To: Bhupesh SHARMA
Cc: u-boot at lists.denx.de; Sharma Bhupesh-B45370; trini at ti.com; Wood Scott-B07421
Subject: Re: Re: [U-Boot] [PATCH v15 07/10] arm64: core support

hi Bhupesh,
Thank you for reviewing of the patch.

Quoted 6 lines

Quoted 6 lines

arch/arm/cpu/armv8/generic_timer.c new file +6 -0

+/*
+ * Generic timer implementation of timer_read_counter()  */
+unsigned long timer_read_counter(void) {
+	unsigned long cntpct;
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));

Quoted 8 lines

arch/arm/cpu/armv8/gic.S

Quoted 3 lines

arch/arm/cpu/armv8/generic_timer.c new file +2 -0

+	return cntpct;
+}

arch/arm/cpu/armv8/gic.S +0 -0

The ARMv8 foundation model has support for GICv2 while GICv3 is actually compatible to ARMv8. So although you mention in the cover letter that this is currently GICv2 support, now while trying to add GICv3 support it will be difficult to envision GICv2 code in

'arch/arm/cpu/armv8/'

Quoted 7 lines

directory.

Infact GICv2 is compatible with ARMv7 and as secure and non-secure copies of GIC registers are equally applicable to ARMv7, would it make sense to keep the GICv2 code at a place where both ARMv7 and ARMv8 can use it?

Quoted 6 lines

Can we reuse something from [1] for GICv2:

[1]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonsec_vi
rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l88

Gicv2 only support maximum 8 cores, but still could be used with armv8 processors if the processor contains less than 8 cores. AMCC's armv8 processor use Gicv2.
Yes, as you said it would be better to abstract a few common routines of Gicv2 and Gicv3 code and place them at a common place (such as arm/lib) so that both ARMv7 and ARMv8 could use it.

Quoted 11 lines

arch/arm/cpu/armv8/gic.S

Quoted 7 lines

arch/arm/cpu/armv8/gic.S +7 -0

+	/* Cache/BPB/TLB Invalidate */
+	bl	__asm_flush_dcache_all		/* dCache clean&invalidate */
+	bl	__asm_invalidate_icache_all	/* iCache invalidate */
+	bl	__asm_invalidate_tlb_all	/* invalidate TLBs */
+
+	/* Processor specific initialization */
+	bl	lowlevel_init

Shouldn't this call be protected inside a '#ifndef CONFIG_SKIP_LOWLEVEL_INIT'?

We could do so when it is actually needed.

Quoted 13 lines

Quoted 1 line

+WEAK(lowlevel_init)

Ok, so this means that a specific SoC lowlevel_init implementation can override this generic implementation. Because I sure other secure/non-secure settings need to be put into place for ARM IPs like SMMU-500.

Quoted 1 line

+ENTRY(armv8_switch_to_el2)

Do we need a switch to Secure Monitor here? I am not able to relate how this with the present ARMv7 code (see [2]):

Quoted 4 lines

[2]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonsec_vi
rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l29

Armv8 processor reset at el3(if it support security extension). So we need to switch the processor to el2 or el1 before u-boot jump to linux kernel due to linux-aarch64 only run at el2 or el1.

-----Original Message-----
From: FengHua [mailto:fenghua at phytium.com.cn]
Sent: Sunday, December 01, 2013 7:48 PM
To: Sharma Bhupesh-B45370
Cc: 'Bhupesh SHARMA'; 'u-boot at lists.denx.de'; 'trini at ti.com'; Wood Scott- B07421
Subject: Re: RE: Re: [U-Boot] [PATCH v15 07/10] arm64: core support

Quoted 51 lines

Quoted 51 lines

-----Original Message-----
From: FengHua [mailto:fenghua at phytium.com.cn]
Sent: Friday, November 29, 2013 7:05 PM
To: Bhupesh SHARMA
Cc: u-boot at lists.denx.de; Sharma Bhupesh-B45370; trini at ti.com; Wood Scott-B07421
Subject: Re: Re: [U-Boot] [PATCH v15 07/10] arm64: core support

hi Bhupesh,
Thank you for reviewing of the patch.

Quoted 7 lines

Quoted 7 lines

arch/arm/cpu/armv8/generic_timer.c new file +7 -0

+/*
+ * Generic timer implementation of timer_read_counter()  */
+unsigned long timer_read_counter(void) {
+	unsigned long cntpct;
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	return cntpct;

Quoted 8 lines

arch/arm/cpu/armv8/gic.S

Quoted 2 lines

(quoted diff) +1 -0

+}

arch/arm/cpu/armv8/gic.S +0 -0

The ARMv8 foundation model has support for GICv2 while GICv3 is actually compatible to ARMv8. So although you mention in the cover letter that this is currently GICv2 support, now while trying to add
GICv3 support it will be difficult to envision GICv2 code in

'arch/arm/cpu/armv8/'

Quoted 7 lines

directory.

Infact GICv2 is compatible with ARMv7 and as secure and non-secure copies of GIC registers are equally applicable to ARMv7, would it make sense to keep the GICv2 code at a place where both ARMv7 and ARMv8 can use it?

Quoted 7 lines

Can we reuse something from [1] for GICv2:

[1]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonse
c_vi rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l88

Gicv2 only support maximum 8 cores, but still could be used with armv8 processors if the processor contains less than 8 cores. AMCC's armv8 processor use Gicv2.
Yes, as you said it would be better to abstract a few common routines of
Gicv2 and Gicv3 code and place them at a common place (such as arm/lib) so that both ARMv7 and ARMv8 could use it.

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

arch/arm/cpu/armv8/gic.S

Quoted 2 lines

arch/arm/cpu/armv8/gic.S +2 -0

+	/* Cache/BPB/TLB Invalidate */
+	bl	__asm_flush_dcache_all		/* dCache

clean&invalidate */

Quoted 34 lines

Quoted 24 lines

Quoted 9 lines

arch/arm/cpu/armv8/gic.S

Quoted 5 lines

arch/arm/cpu/armv8/gic.S +5 -0

+	bl	__asm_invalidate_icache_all	/* iCache invalidate */
+	bl	__asm_invalidate_tlb_all	/* invalidate TLBs */
+
+	/* Processor specific initialization */
+	bl	lowlevel_init

Shouldn't this call be protected inside a '#ifndef CONFIG_SKIP_LOWLEVEL_INIT'?

We could do so when it is actually needed.

Quoted 13 lines

Quoted 1 line

+WEAK(lowlevel_init)

Ok, so this means that a specific SoC lowlevel_init implementation can override this generic implementation. Because I sure other secure/non-secure settings need to be put into place for ARM IPs like SMMU-500.

Quoted 1 line

+ENTRY(armv8_switch_to_el2)

Do we need a switch to Secure Monitor here? I am not able to relate how this with the present ARMv7 code (see [2]):

Quoted 9 lines

Quoted 5 lines

[2]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonse
c_vi rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l29

Armv8 processor reset at el3(if it support security extension). So we need to switch the processor to el2 or el1 before u-boot jump to linux kernel due to linux-aarch64 only run at el2 or el1.

Quoted 6 lines

Hi David,

As per ARMv8 Arch Reference Manual (ARM), Monitor mode is provided to support switching between Secure and Non-secure states. For switching from secure to non secure state the usual mechanism is an exception return. To return to Non-secure state (EL1/EL2), software executing in

Monitor mode(EL3) sets SCR.NS to 1 and then performs the exception return.

Quoted 5 lines

The implementation already in place for ARMv7 (see:
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonsec_vi
rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l29), does this (sets up SMC handler and start.S calls smc #0 to switch to

non-secure state).

Quoted 3 lines

Something similar must be put into place for ARMv8 as well.

Sorry?I did not get your initially.
In my opinion, u-boot runs at monitor mode(EL3), it coulde set SCR.NS to 1 directly.
Why we need to setup SMC handler and call SMC #0 to switch to non-secure state?
I don't understand why armv7 did so. Did you have any understanding about this?

-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Bhupesh Sharma
Sent: Tuesday, December 03, 2013 3:33 PM
To: 'FengHua'
Cc: 'trini at ti.com'; 'u-boot at lists.denx.de'; Wood Scott-B07421
Subject: Re: [U-Boot] [PATCH v15 07/10] arm64: core support

Quoted 122 lines

-----Original Message-----
From: FengHua [mailto:fenghua at phytium.com.cn]
Sent: Sunday, December 01, 2013 7:48 PM
To: Sharma Bhupesh-B45370
Cc: 'Bhupesh SHARMA'; 'u-boot at lists.denx.de'; 'trini at ti.com'; Wood Scott-
B07421
Subject: Re: RE: Re: [U-Boot] [PATCH v15 07/10] arm64: core support

Quoted 56 lines

Quoted 56 lines

-----Original Message-----
From: FengHua [mailto:fenghua at phytium.com.cn]
Sent: Friday, November 29, 2013 7:05 PM
To: Bhupesh SHARMA
Cc: u-boot at lists.denx.de; Sharma Bhupesh-B45370; trini at ti.com; Wood
Scott-B07421
Subject: Re: Re: [U-Boot] [PATCH v15 07/10] arm64: core support

hi Bhupesh,
Thank you for reviewing of the patch.

Quoted 8 lines

Quoted 8 lines

arch/arm/cpu/armv8/generic_timer.c new file +8 -0

+/*
+ * Generic timer implementation of timer_read_counter()  */
+unsigned long timer_read_counter(void) {
+	unsigned long cntpct;
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	return cntpct;
+}

Quoted 8 lines

arch/arm/cpu/armv8/gic.S

Quoted 2 lines

arch/arm/cpu/armv8/gic.S +0 -0

The ARMv8 foundation model has support for GICv2 while GICv3 is actually compatible to ARMv8. So although you mention in the cover letter that this is currently GICv2 support, now while trying to add
GICv3 support it will be difficult to envision GICv2 code in

'arch/arm/cpu/armv8/'

Quoted 8 lines

directory.

Infact GICv2 is compatible with ARMv7 and as secure and non-secure copies of GIC registers are equally applicable to ARMv7, would it make sense to keep the GICv2 code at a place where both ARMv7 and
ARMv8 can use it?

Quoted 8 lines

Can we reuse something from [1] for GICv2:

[1]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/non
se
c_vi rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l88

Gicv2 only support maximum 8 cores, but still could be used with armv8 processors if the processor contains less than 8 cores. AMCC's
armv8 processor use Gicv2.
Yes, as you said it would be better to abstract a few common routines of
Gicv2 and Gicv3 code and place them at a common place (such as arm/lib) so that both ARMv7 and ARMv8 could use it.

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

arch/arm/cpu/armv8/gic.S

Quoted 2 lines

arch/arm/cpu/armv8/gic.S +2 -0

+	/* Cache/BPB/TLB Invalidate */
+	bl	__asm_flush_dcache_all		/* dCache

clean&invalidate */

Quoted 35 lines

Quoted 30 lines

Quoted 9 lines

arch/arm/cpu/armv8/gic.S

Quoted 5 lines

arch/arm/cpu/armv8/gic.S +5 -0

+	bl	__asm_invalidate_icache_all	/* iCache invalidate */
+	bl	__asm_invalidate_tlb_all	/* invalidate TLBs */
+
+	/* Processor specific initialization */
+	bl	lowlevel_init

Shouldn't this call be protected inside a '#ifndef CONFIG_SKIP_LOWLEVEL_INIT'?

We could do so when it is actually needed.

Quoted 10 lines

Quoted 1 line

+WEAK(lowlevel_init)

Ok, so this means that a specific SoC lowlevel_init implementation can override this generic implementation. Because I sure other secure/non-secure settings need to be put into place for ARM IPs like SMMU-500.

Quoted 1 line

+ENTRY(armv8_switch_to_el2)

Quoted 9 lines

Do we need a switch to Secure Monitor here? I am not able to relate how this with the present ARMv7 code (see [2]):

[2]
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/non
se
c_vi rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l29

Quoted 4 lines

Armv8 processor reset at el3(if it support security extension). So we need to switch the processor to el2 or el1 before u-boot jump to linux kernel due to linux-aarch64 only run at el2 or el1.

Quoted 7 lines

Hi David,

As per ARMv8 Arch Reference Manual (ARM), Monitor mode is provided to support switching between Secure and Non-secure states. For switching from secure to non secure state the usual mechanism is an exception return. To return to Non-secure state (EL1/EL2), software executing in

Monitor mode(EL3) sets SCR.NS to 1 and then performs the exception return.

Quoted 5 lines

The implementation already in place for ARMv7 (see:
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/nonsec_
vi rt.S;h=24b4c18bd452fa155bcd5ed94c755aa05a33efe7;hb=HEAD#l29), does this (sets up SMC handler and start.S calls smc #0 to switch to

non-secure state).

Quoted 3 lines

Something similar must be put into place for ARMv8 as well.

Quoted 8 lines

Sorry?I did not get your initially.
In my opinion, u-boot runs at monitor mode(EL3), it coulde set SCR.NS to
1 directly.
Why we need to setup SMC handler and call SMC #0 to switch to non-secure state?
I don't understand why armv7 did so. Did you have any understanding about this?

Well, all ARM cores which support security extensions must support a SMC exception handler (ARMv7/v8). The monitor mode (which is entered by executing a SMC
instruction) allows ARM core to switch from secure to non-secure state and vice-versa.

Note that for supporting ARM TrustZone, ARM specifies a SMC calling convention
spec:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0028a/inde
x.html

Hi David,

In reference to my mail above, I see that the transition to EL2 (from EL3) which occurs very early in start.S needs to be changed on lines of the ARMv7 code, i.e. the EL2 transition should happen just before Linux is booted up by the u-boot.

The reason for the same is that a no of ARM IPs like GIC, SMMU and TZPC/TZASC need to be configured to allow non-secure accesses from Linux world (which runs in EL1 mode). Adding the assembly code for all such IPs in 'setup_el3' function in start.S, will bloat the start.S and also increase the chances of a bug in the assembly code.

Hence, I would like to propose a strategy to shift from EL3 to EL2 to some point in u-boot code after the C Run Time has been initialized (similar to present ARMv7 u-boot code).

If you are ok with the same, I can try to send out some RFC patches rebased against your latest v16 code-base.

Please let me know.
Regards,
Bhupesh

hi bhupesh,

Quoted 14 lines

Hi David,

In reference to my mail above, I see that the transition to EL2 (from EL3) which occurs very early in start.S needs to be changed on lines of the ARMv7 code, i.e. the EL2 transition should happen just before Linux is booted up by the u-boot.

The reason for the same is that a no of ARM IPs like GIC, SMMU and TZPC/TZASC need to be configured to allow non-secure accesses from Linux world (which runs in EL1 mode). Adding the assembly code for all such IPs in 'setup_el3' function in start.S, will bloat the start.S and also increase the chances of a bug in the assembly code.

Hence, I would like to propose a strategy to shift from EL3 to EL2 to some point in u-boot code after the C Run Time has been initialized (similar to present ARMv7 u-boot code).

Quoted 6 lines

If you are ok with the same, I can try to send out some RFC patches rebased against your latest v16 code-base.

Please let me know.
Regards,
Bhupesh

Actually, patch v16 did exception level switch in the way as you said. please review the code.
Both master and slaves switch to el2(el1) just before jumping to linux kernel. BTW,if any good conception please feel free to patch it.

Quoted 16 lines · FengHua

hi bhupesh,

Quoted 14 lines

Hi David,

In reference to my mail above, I see that the transition to EL2 (from EL3) which occurs very early in start.S needs to be changed on lines of the ARMv7 code, i.e. the EL2 transition should happen just before Linux is booted up by the u-boot.

The reason for the same is that a no of ARM IPs like GIC, SMMU and TZPC/TZASC need to be configured to allow non-secure accesses from Linux world (which runs in EL1 mode). Adding the assembly code for all such IPs in 'setup_el3' function in start.S, will bloat the start.S and also increase the chances of a bug in the assembly code.

Hence, I would like to propose a strategy to shift from EL3 to EL2 to some point in u-boot code after the C Run Time has been initialized (similar to present ARMv7 u-boot code).

Quoted 8 lines

Quoted 6 lines

If you are ok with the same, I can try to send out some RFC patches rebased against your latest v16 code-base.

Please let me know.
Regards,
Bhupesh

Actually, patch v16 did exception level switch in the way as you said. please review the code.
Both master and slaves switch to el2(el1) just before jumping to linux kernel. BTW,if any good conception please feel free to patch it.

How would you handle running U-Boot under a secure firmware, or under a hypervisor? Why not take the Linux approach of running most code in EL1, with exception handlers pointing at code to handle special situations (such as returning to EL2 before OS entry)?

As for bloating start.S, could leaving EL3 be done in early C code rather than in early asm or late C code? Or, bundle U-Boot with a tiny "insecure firmware" that provides the minimum functionality needed with similar APIs that would be used with real secure firmware.

-Scott

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-----Original Messages-----
From: "Scott Wood" <[email protected]>
Sent Time: 2014-01-23 08:28:06 (Thursday)
To: FengHua <[email protected]>
Cc: "bhupesh.sharma at freescale.com" <[email protected]>, "'trini at ti.com'" <[email protected]>, "'u-boot at lists.denx.de'" <[email protected]>, rod.dorris at freescale.com
Subject: Re: [U-Boot] [PATCH v15 07/10] arm64: core support

Quoted 16 lines · FengHua

hi bhupesh,

Quoted 14 lines

Hi David,

In reference to my mail above, I see that the transition to EL2 (from EL3) which occurs very early in start.S needs to be changed on lines of the ARMv7 code, i.e. the EL2 transition should happen just before Linux is booted up by the u-boot.

The reason for the same is that a no of ARM IPs like GIC, SMMU and TZPC/TZASC need to be configured to allow non-secure accesses from Linux world (which runs in EL1 mode). Adding the assembly code for all such IPs in 'setup_el3' function in start.S, will bloat the start.S and also increase the chances of a bug in the assembly code.

Hence, I would like to propose a strategy to shift from EL3 to EL2 to some point in u-boot code after the C Run Time has been initialized (similar to present ARMv7 u-boot code).

Quoted 8 lines

Quoted 6 lines

If you are ok with the same, I can try to send out some RFC patches rebased against your latest v16 code-base.

Please let me know.
Regards,
Bhupesh

Actually, patch v16 did exception level switch in the way as you said. please review the code.
Both master and slaves switch to el2(el1) just before jumping to linux kernel. BTW,if any good conception please feel free to patch it.

How would you handle running U-Boot under a secure firmware, or under a hypervisor? Why not take the Linux approach of running most code in EL1, with exception handlers pointing at code to handle special situations (such as returning to EL2 before OS entry)?

As for bloating start.S, could leaving EL3 be done in early C code rather than in early asm or late C code? Or, bundle U-Boot with a tiny "insecure firmware" that provides the minimum functionality needed with similar APIs that would be used with real secure firmware.

-Scott

Hi, fenghua:
How to get u-boot code with arch/arm/cpu/armv8 directory?
I used "git://www.denx.de/git/u-boot.git " to get latest code, but not find armv8 dir.

Best wishes,

hi Tiger,
Sorry! It's a little late.
Albert has merged arm64 patch set. I have tested and it works fine on Foundation Model. So, you could get it from git tree of u-boot-arm branch.

Regards,
David

Quoted 4 lines

Hi, fenghua:
How to get u-boot code with arch/arm/cpu/armv8 directory?
I used "git://www.denx.de/git/u-boot.git " to get latest code, but not find armv8 dir.

Albert has merged arm64 patch set. I have tested and it works fine

CROSS_COMPILE=/home/lion/ARMv8/gcc-linaro-aarch64/bin/aarch64-linux-gnu-

Dear TigerLiu at viatech.com.cn,

Quoted 2 lines · In message <[email protected]>…

CROSS_COMPILE=/home/lion/ARMv8/gcc-linaro-aarch64/bin/aarch64-linux-gnu-

Side note:

It is always wrong to use an absolute path name for CROSS_COMPILE. You should use "CROSS_COMPILE=aarch64-linux-gnu-" and make sure your PATH is set correctly.

Quoted 4 lines

It is always wrong to use an absolute path name for CROSS_COMPILE. You should use "CROSS_COMPILE=aarch64-linux-gnu-" and make sure your PATH is set correctly.

Actually, I also give the full path name when defining CROSS_COMPILER

variable. This is because I find myself juggling between different compilers, located in different locations for the same build (personal experimentation). Is there some dependency on the PATH variable that I'm missing? Or is this just convention?

From: David Feng <[email protected]>

Changes for v15:
- modify boot process, u-boot will run at the highest exception level until it prepare jump to OS.
- Fix a few bugs in cache.S.These bug is reported by York Sun <[email protected]> and Scott Wood <[email protected]>.
- when booting, slaves will wait on WFI, master wakeup slaves by SGI interrupt.
- add generic_timer.c to utilize the newest timer architecture.
- add gic.S to support gic initialization and interrupt operations, currently only support GICv2.

After changing to u-boot.elf, it could be run in FVP model.

-----Original Message-----
From: TigerLiu at viatech.com.cn [mailto:TigerLiu at viatech.com.cn]
Sent: Monday, January 20, 2014 4:24 PM
To: Wood Scott-B07421; Sharma Bhupesh-B45370
Cc: fenghua at phytium.com.cn; trini at ti.com; u-boot at lists.denx.de
Subject: Re: Re: [U-Boot] how to get u-boot code with arm64: core support

Hi, Scott:

Quoted 1 line

After changing to u-boot.elf, it could be run in FVP model.

If I run "./Foundation_v8 --image ./u-boot.elf --cores=4 --no-secure- memory", Uboot could be run with FVP model.
But no ARM trusted firmware boot info appeared.
Such as:
Booting trusted firmware boot loader stage 1 ......

If I run "./Foundation_v8 --cores=4 --no-secure-memory --no-gicv3 --data="./bl1.bin"@0x0 --nsdata="./u-boot.elf"@0x80000000", ARM trusted firmware boot info could appear, but failed to load and run u-boot.elf.

So, if I want to use ARM trusted firmware to boot u-boot.elf, any ideas?

U-boot doesn't have ARM trusted firmware support as of now. U-boot for

whereas UEFI starts in EL2 as trusted firmware itself is working in

U-boot doesn't have ARM trusted firmware support as of now. U-boot for ARMv8 starts in EL3, whereas UEFI starts in EL2 as trusted firmware itself is working in EL3.

-----Original Message-----
From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On Behalf Of drambo
Sent: Thursday, January 23, 2014 12:32 AM
To: u-boot at lists.denx.de
Subject: Re: [U-Boot] how to get u-boot code with arm64: core support

Hi Bhupesh,

Quoted 3 lines

U-boot doesn't have ARM trusted firmware support as of now. U-boot for ARMv8 starts in EL3, whereas UEFI starts in EL2 as trusted firmware itself is working in EL3.

Since the ATF software doesn't really care whether it is loading uefi or u-boot and since it wants to load non-secure images as EL2 or EL1
(https://github.com/ARM-software/arm-trusted-
firmware/blob/master/docs/user-guide.md
See section "Normal World Software Execution"), why would we want to assume u-boot starts in EL3 mode by default?

If we want to support EL3 execution for convenience to those that don't have ATF setup, that might make sense, but then shouldn't initial EL3 execution and subsequent switching levels be debug CONFIG options? Thanks.

-----Original Message-----
From: TigerLiu at viatech.com.cn [mailto:TigerLiu at viatech.com.cn]
Sent: Thursday, January 23, 2014 1:25 PM
To: Sharma Bhupesh-B45370; drambo at broadcom.com; u-boot at lists.denx.de
Cc: trini at ti.com
Subject: Re: [U-Boot] how to get u-boot code with arm64: core support

Hi, bhupesh and drambo:
I think current uboot ARMv8's start.S could handle EL2/EL1 case. I have tested it on FVP model, let arm trusted firmware boot u- boot.bin.
It seemed ok.
The command I used is:
./Foundation_v8 --cores=4 --no-secure-memory --no-gicv3 --data="./bl1.bin"@0x0 --nsdata="./u-boot.bin"@0x08000000