 arch/arm/cpu/armv7/mx6/soc.c              | 14 +++++++++++---
 arch/arm/imx-common/cpu.c                 |  2 ++
 arch/arm/include/asm/arch-mx5/sys_proto.h |  1 +
 arch/arm/include/asm/arch-mx6/sys_proto.h |  1 +
 4 files changed, 15 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/mx6/soc.c +11 -3

index 0208cba..9acd8c9 100644
@@ -41,14 +41,19 @@ u32 get_cpu_rev(void)
 
 	if (type != MXC_CPU_MX6SL) {
 		reg = readl(&anatop->digprog);
+		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+		u32 cfg = readl(&scu->config) & 3;
 		type = ((reg >> 16) & 0xff);
 		if (type == MXC_CPU_MX6DL) {
-			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-			u32 cfg = readl(&scu->config) & 3;
-
 			if (!cfg)
 				type = MXC_CPU_MX6SOLO;
 		}
+
+		if (type == MXC_CPU_MX6Q) {
+			if (cfg == 1)
+				type = MXC_CPU_MX6D;
+		}
+
 	}
 	reg &= 0xff;		/* mx6 silicon revision */
 	return (type << 12) | (reg + 0x10);

@@ -62,6 +67,9 @@ u32 __weak get_board_rev(void)
 	if (type == MXC_CPU_MX6SOLO)
 		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
 
+	if (type == MXC_CPU_MX6D)
+		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
 	return cpurev;
 }
 #endif

arch/arm/imx-common/cpu.c +2 -0

index 9231649..a77c4de 100644
@@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
 	switch (imxtype) {
 	case MXC_CPU_MX6Q:
 		return "6Q";	/* Quad-core version of the mx6 */
+	case MXC_CPU_MX6D:
+		return "6D";	/* Dual-core version of the mx6 */
 	case MXC_CPU_MX6DL:
 		return "6DL";	/* Dual Lite version of the mx6 */
 	case MXC_CPU_MX6SOLO:

arch/arm/include/asm/arch-mx5/sys_proto.h +1 -0

index 9949ad1..7dacc4c 100644
@@ -14,6 +14,7 @@
 #define MXC_CPU_MX6DL		0x61
 #define MXC_CPU_MX6SOLO		0x62
 #define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);

arch/arm/include/asm/arch-mx6/sys_proto.h +1 -0

index 17125a6..eda779e 100644
@@ -16,6 +16,7 @@
 #define MXC_CPU_MX6DL		0x61
 #define MXC_CPU_MX6SOLO		0x62
 #define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);

Signature · 1 line

1.8.1.2

Stefano Babic

2014-01-26 12:07 UTC #1 lore raw

PATCH v2 1/1 mx6: Distinguish mx6dual from mx6quad

Hi Fabio, hi Otavio,

Quoted 75 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Currently when we boot a mx6dual U-boot reports that it is a mx6quad.

Report it as MX6D instead:

CPU: Freescale i.MX6D rev1.2 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

Tested-by Otavio Salvador <[email protected]>

---
Changes since v1:
- Fix mx5 build error (Otavio)

  arch/arm/cpu/armv7/mx6/soc.c              | 14 +++++++++++---
  arch/arm/imx-common/cpu.c                 |  2 ++
  arch/arm/include/asm/arch-mx5/sys_proto.h |  1 +
  arch/arm/include/asm/arch-mx6/sys_proto.h |  1 +
  4 files changed, 15 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/mx6/soc.c +11 -3

index 0208cba..9acd8c9 100644
@@ -41,14 +41,19 @@ u32 get_cpu_rev(void)
 
  	if (type != MXC_CPU_MX6SL) {
  		reg = readl(&anatop->digprog);
+		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+		u32 cfg = readl(&scu->config) & 3;
  		type = ((reg >> 16) & 0xff);
  		if (type == MXC_CPU_MX6DL) {
-			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
-			u32 cfg = readl(&scu->config) & 3;
-
  			if (!cfg)
  				type = MXC_CPU_MX6SOLO;
  		}
+
+		if (type == MXC_CPU_MX6Q) {
+			if (cfg == 1)
+				type = MXC_CPU_MX6D;
+		}
+
  	}
  	reg &= 0xff;		/* mx6 silicon revision */
  	return (type << 12) | (reg + 0x10);

@@ -62,6 +67,9 @@ u32 __weak get_board_rev(void)
  	if (type == MXC_CPU_MX6SOLO)
  		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
 
+	if (type == MXC_CPU_MX6D)
+		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
  	return cpurev;
  }
  #endif

arch/arm/imx-common/cpu.c +2 -0

index 9231649..a77c4de 100644
@@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
  	switch (imxtype) {
  	case MXC_CPU_MX6Q:
  		return "6Q";	/* Quad-core version of the mx6 */
+	case MXC_CPU_MX6D:
+		return "6D";	/* Dual-core version of the mx6 */
  	case MXC_CPU_MX6DL:
  		return "6DL";	/* Dual Lite version of the mx6 */
  	case MXC_CPU_MX6SOLO:

arch/arm/include/asm/arch-mx5/sys_proto.h +0 -0

index 9949ad1..7dacc4c 100644

arch/arm/include/asm/arch-mx5/sys_proto.h line 18

Quoted 5 lines

arch/arm/include/asm/arch-mx5/sys_proto.h +1 -0

@@ -14,6 +14,7 @@
  #define MXC_CPU_MX6DL		0x61
  #define MXC_CPU_MX6SOLO		0x62
  #define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64

Agree generally with the patch, but it seems to me better, instead of fixing the MX5 here, to move all CPU definitions outside the specific MX5/MX6 files into imx-common. They can be then defined once else in each sys_proto.h.

I have nothing against a new file, maybe cpu.h ?

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Fabio Estevam

author reviewer

2014-01-26 17:09 UTC #2 lore raw

PATCH v2 1/1 mx6: Distinguish mx6dual from mx6quad

Hi Stefano,

Quoted 5 lines · Stefano Babic

Agree generally with the patch, but it seems to me better, instead of fixing the MX5 here, to move all CPU definitions outside the specific MX5/MX6 files into imx-common. They can be then defined once else in each sys_proto.h.
I have nothing against a new file, maybe cpu.h ?

Yes, it looks better by having a common cpu.h. Just sent v4.

Regards,

Fabio Estevam