Powerpc/QE: Add QE support for T1040

PATCH Superseded Zhao Qiang 3 participants 8 messages Jan 24, 2014 – Jan 26, 2014 PowerPC

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Zhao Qiang

author

2014-01-24 09:05 UTC #0 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

T1040 has QE-related addresses different from other boards, modify those addresses value with macro CONFIG_PPC_T1040 and CONFIG_T1040QDS.
Add function qe_board_setup to mux the bus to tdm or uart according to hwconfig.

Signed-off-by Jiucheng Xu <[email protected]>

Signed-off-by Zhao Qiang <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init.c       | 11 +++++++++--
 arch/powerpc/cpu/mpc85xx/qe_io.c          |  2 +-
 arch/powerpc/cpu/mpc85xx/speed.c          |  6 ++++++
 arch/powerpc/cpu/mpc85xx/t1040_ids.c      |  1 +
 arch/powerpc/include/asm/config_mpc85xx.h |  3 +++
 arch/powerpc/include/asm/fsl_liodn.h      |  4 ++++
 arch/powerpc/include/asm/immap_85xx.h     |  9 ++++++++-
 board/freescale/t1040qds/t1040qds.c       | 29 +++++++++++++++++++++++++++++
 drivers/qe/qe.c                           |  4 ++++
 drivers/qe/qe.h                           |  2 ++
 include/configs/T1040QDS.h                |  2 ++
 11 files changed, 69 insertions(+), 4 deletions(-)

arch/powerpc/cpu/mpc85xx/cpu_init.c +9 -2

index b31efb7..4448e04 100644
@@ -33,15 +33,15 @@
 #endif
 
 #include "../../../../drivers/block/fsl_sata.h"
+#include "../../../../drivers/qe/qe.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_QE
+#ifndef CONFIG_PPC_T1040
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
 				int open_drain, int assign);
-extern void qe_init(uint qe_base);
-extern void qe_reset(void);
 
 static void config_qe_ioports(void)
 {

@@ -59,6 +59,7 @@ static void config_qe_ioports(void)
 	}
 }
 #endif
+#endif
 
 #ifdef CONFIG_CPM2
 void config_8560_ioports (volatile ccsr_cpm_t * cpm)

@@ -262,9 +263,11 @@ void cpu_init_f (void)
 	m8560_cpm_reset();
 #endif
 #ifdef CONFIG_QE
+#ifndef CONFIG_PPC_T1040
 	/* Config QE ioports */
 	config_qe_ioports();
 #endif
+#endif
 #if defined(CONFIG_FSL_DMA)
 	dma_init();
 #endif

@@ -736,7 +739,11 @@ int sata_initialize(void)
 void cpu_secondary_init_r(void)
 {
 #ifdef CONFIG_QE
+#ifdef CONFIG_PPC_T1040
+	uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
+#else
 	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
+#endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 	int ret;
 	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;

arch/powerpc/cpu/mpc85xx/qe_io.c +1 -1

index 76c60da..a495080 100644
@@ -12,7 +12,7 @@
 #include "asm/io.h"
 #include "asm/immap_85xx.h"
 
-#if defined(CONFIG_QE)
+#if defined(CONFIG_QE) && !defined(CONFIG_T1040QDS)
 #define	NUM_OF_PINS	32
 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 {

arch/powerpc/cpu/mpc85xx/speed.c +6 -0

index 35867df..634f107 100644
@@ -335,6 +335,12 @@ void get_sys_info(sys_info_t *sys_info)
 
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
+#ifdef CONFIG_QE
+#if defined(CONFIG_PPC_T1040)
+	sys_info->freq_qe =  sys_info->freq_systembus / 2;
+#endif
+#endif
+
 #else /* CONFIG_FSL_CORENET */
 	uint plat_ratio, e500_ratio, half_freq_systembus;
 	int i;

arch/powerpc/cpu/mpc85xx/t1040_ids.c +1 -0

index 32075ce..4984727 100644
@@ -66,6 +66,7 @@ struct liodn_id_table liodn_tbl[] = {
 	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
 
 	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+	SET_QE_LIODN(559),
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);

arch/powerpc/include/asm/config_mpc85xx.h +3 -0

index 54ce2f0..ee994cc 100644
@@ -718,6 +718,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
 
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define CONFIG_E6500

arch/powerpc/include/asm/fsl_liodn.h +4 -0

index 44bc88d..f658bcb 100644
@@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob);
 	SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
 		CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
 
+#define SET_QE_LIODN(liodn) \
+	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
+		CONFIG_SYS_MPC85xx_QE_OFFSET)
+
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
 		CONFIG_SYS_FSL_QMAN_OFFSET, \

arch/powerpc/include/asm/immap_85xx.h +8 -1

index 68c3c82..23525a1 100644
@@ -1871,7 +1871,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 	u32	sata2liodnr;	/* SATA 2 LIODN */
 	u32	sata3liodnr;	/* SATA 3 LIODN */
 	u32	sata4liodnr;	/* SATA 4 LIODN */
-	u8	res22[32];
+	u8      res22[24];
+	u32     qeliodnr;       /* QE LIODN */
+	u8      res_57c[4];
 	u32	dma1liodnr;	/* DMA 1 LIODN */
 	u32	dma2liodnr;	/* DMA 2 LIODN */
 	u32	dma3liodnr;	/* DMA 3 LIODN */

@@ -2843,6 +2845,11 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+
+#ifdef CONFIG_PPC_T1040
+#define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
+#endif
+
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
 	&& !defined(CONFIG_PPC_B4420)

board/freescale/t1040qds/t1040qds.c +29 -0

index de3ea5c..4d18fb5 100644
@@ -18,6 +18,7 @@
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
+#include <hwconfig.h>
 
 #include "../common/qixis.h"
 #include "t1040qds.h"

@@ -89,6 +90,30 @@ int select_i2c_ch_pca9547(u8 ch)
 	return 0;
 }
 
+static void qe_board_setup(void)
+{
+	u8 brdcfg15, brdcfg9;
+
+	if (hwconfig("qe") && hwconfig("tdm")) {
+		brdcfg15 = QIXIS_READ(brdcfg[15]);
+		/*
+		 * TDMRiser uses QE-TDM
+		 * Route QE_TDM signals to TDM Riser slot
+		 */
+		QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
+	} else if (hwconfig("qe") && hwconfig("uart")) {
+		brdcfg15 = QIXIS_READ(brdcfg[15]);
+		brdcfg9 = QIXIS_READ(brdcfg[9]);
+		/*
+		 * Route QE_TDM signals to UCC
+		 * ProfiBus controlled by UCC3
+		 */
+		brdcfg15 &= 0xfc;
+		QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
+		QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
+	}
+}
+
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE

@@ -196,6 +221,10 @@ int misc_init_r(void)
 		}
 	}
 
+#if defined(CONFIG_QE)
+	qe_board_setup();
+#endif
+
 	return 0;
 }

drivers/qe/qe.c +4 -0

index b5ddc4b..63747de 100644
@@ -165,7 +165,11 @@ void qe_init(uint qe_base)
 	/*
 	 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
 	 */
+#ifdef CONFIG_PPC_T1040
+	qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR);
+#else
 	qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+#endif
 
 	/* enable the microcode in IRAM */
 	out_be32(&qe_immr->iram.iready,QE_IRAM_READY);

drivers/qe/qe.h +2 -0

index c82ac7b..2079bf6 100644
@@ -282,5 +282,7 @@ int qe_set_mii_clk_src(int ucc_num);
 int qe_upload_firmware(const struct qe_firmware *firmware);
 struct qe_firmware_info *qe_get_firmware_info(void);
 void ft_qe_setup(void *blob);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
 
 #endif /* __QE_H__ */

include/configs/T1040QDS.h +2 -0

index 91b511b..819e0f1 100644
@@ -572,6 +572,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 
+#define CONFIG_QE
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SPIFLASH)
 /*

@@ -594,6 +595,7 @@ unsigned long get_board_ddr_clk(void);
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_SYS_QE_UCODE_FW_ADDR		0xEFF10000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

Signature · 1 line

1.8.5

Timur Tabi

2014-01-25 15:49 UTC #1 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

drivers/qe/qe.c void qe_init(uint qe_base) · line 172

Quoted 6 lines · Zhao Qiang

drivers/qe/qe.c +4 -0

+#ifdef CONFIG_PPC_T1040
+       qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR);
+#else
        qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+#endif

It's been a while since I looked at the QE code in U-Boot, but this should be unnecessary. CONFIG_SYS_QE_FMAN_FW_ADDR is supposed to point to the QE microcode blob. Why do you need to define CONFIG_SYS_QE_UCODE_FW_ADDR? That's redundant.

qiang.zhao at freescale.com

2014-01-26 03:17 UTC #2 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

Quoted 8 lines · Timur Tabi

-----Original Message-----
From: Timur Tabi [mailto:timur at tabi.org]
Sent: Saturday, January 25, 2014 11:49 PM
To: Zhao Qiang-B45475
Cc: U-Boot Mailing List; Xu Jiucheng-B37781; Xie Xiaobo-R63061
Subject: Re: [U-Boot] [PATCH] Powerpc/QE: Add QE support for T1040
On Fri, Jan 24, 2014 at 3:05 AM, Zhao Qiang <[email protected]> wrote:

Quoted 13 lines

drivers/qe/qe.c void qe_init(uint qe_base) · line 172
Quoted 6 lines
drivers/qe/qe.c +4 -0
+#ifdef CONFIG_PPC_T1040
+       qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR);
+#else
        qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);
+#endif
It's been a while since I looked at the QE code in U-Boot, but this should be unnecessary. CONFIG_SYS_QE_FMAN_FW_ADDR is supposed to point to the QE microcode blob. Why do you need to define CONFIG_SYS_QE_UCODE_FW_ADDR? That's redundant.

CONFIG_SYS_QE_FMAN_FW_ADDR is used for Fman microcode while CONFIG_SYS_QE_UCODE_FW_ADDR used For QE microcode.

Regards,
Zhao Qiang

Timur Tabi

2014-01-26 03:22 UTC #3 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

Quoted 2 lines · qiang.zhao at freescale.com

CONFIG_SYS_QE_FMAN_FW_ADDR is used for Fman microcode while CONFIG_SYS_QE_UCODE_FW_ADDR used For QE microcode.

No, CONFIG_SYS_QE_FMAN_FW_ADDR is used for both QE and Fman microcode. That's why it says "QE_FMAN" in it. This is documented in the README.

qiang.zhao at freescale.com

2014-01-26 03:46 UTC #4 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

Quoted 7 lines · Timur Tabi

-----Original Message-----
From: Timur Tabi [mailto:timur at tabi.org]
Sent: Sunday, January 26, 2014 11:23 AM
To: Zhao Qiang-B45475
Cc: U-Boot Mailing List; Xu Jiucheng-B37781; Xie Xiaobo-R63061
Subject: Re: [U-Boot] [PATCH] Powerpc/QE: Add QE support for T1040

Quoted 7 lines

Quoted 2 lines · qiang.zhao at freescale.com
CONFIG_SYS_QE_FMAN_FW_ADDR is used for Fman microcode while CONFIG_SYS_QE_UCODE_FW_ADDR used For QE microcode.
No, CONFIG_SYS_QE_FMAN_FW_ADDR is used for both QE and Fman microcode. That's why it says "QE_FMAN" in it. This is documented in the README.

Other boards have either Fman or QE, So CONFIG_SYS_QE_FMAN_FW_ADDR can be used either Fman or QE.

But T1040QDS have both Fman and QE.

Regards,
Zhao Qiang

Timur Tabi

2014-01-26 04:36 UTC #5 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

Quoted 4 lines · qiang.zhao at freescale.com

Other boards have either Fman or QE, So CONFIG_SYS_QE_FMAN_FW_ADDR can be used either Fman or QE.
But T1040QDS have both Fman and QE.

Does the T1040QDS have microcode for both Fman and QE? Normally, QE microcode is not needed.

qiang.zhao at freescale.com

2014-01-26 06:05 UTC #6 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

Quoted 7 lines · Timur Tabi

-----Original Message-----
From: Timur Tabi [mailto:timur at tabi.org]
Sent: Sunday, January 26, 2014 12:37 PM
To: Zhao Qiang-B45475
Cc: U-Boot Mailing List; Xu Jiucheng-B37781; Xie Xiaobo-R63061
Subject: Re: [U-Boot] [PATCH] Powerpc/QE: Add QE support for T1040

Quoted 9 lines

Quoted 4 lines · qiang.zhao at freescale.com
Other boards have either Fman or QE, So CONFIG_SYS_QE_FMAN_FW_ADDR can be used either Fman or QE.
But T1040QDS have both Fman and QE.
Does the T1040QDS have microcode for both Fman and QE? Normally, QE microcode is not needed.

T1040QDS has microcode for Fman and another microcode for QE. The two microcodes is different.

QE microcode is needed.

Regards,
Zhao Qiang

Timur Tabi

2014-01-26 14:31 UTC #7 lore raw

PATCH 1/1 Powerpc/QE: Add QE support for T1040

Quoted 4 lines · qiang.zhao at freescale.com

T1040QDS has microcode for Fman and another microcode for QE. The two microcodes is different.
QE microcode is needed.

Then why do you have an #else statement:

+#ifdef CONFIG_PPC_T1040
+ qe_upload_firmware((const void *)CONFIG_SYS_QE_UCODE_FW_ADDR);
+#else

         qe_upload_firmware((const void *)CONFIG_SYS_QE_FMAN_FW_ADDR);

+#endif

On the T1040, you're uploading only the QE firmware.

I think you're going to have to do a lot of work to fix this. "#ifdef CONFIG_PPC_T1040" is not acceptable.

1. Replace CONFIG_SYS_QE_FMAN_FW_ADDR with CONFIG_SYS_QE_FW_ADDR and CONFIG_SYS_FMAN_FW_ADDR. Any board that uses CONFIG_SYS_QE_FMAN_FW_ADDR for QE firmware will use CONFIG_SYS_QE_FW_ADDR instead. Any board that uses CONFIG_SYS_QE_FMAN_FW_ADDR for Fman firmware will use CONFIG_SYS_FMAN_FW_ADDR instead.

2. Modify the QE code to use CONFIG_SYS_QE_FW_ADDR to upload the QE firmware. Modify the Fman code to use CONFIG_SYS_FMAN_FW_ADDR to upload the Fman firmwre. Then you can do this:

#ifdef CONFIG_SYS_QE_FW_ADDR
        qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
#endif
#ifdef CONFIG_SYS_FMAN_FW_ADDR
        qe_upload_firmware((const void *)CONFIG_SYS_FMAN_FW_ADDR);

+#endif

3. Update the README

This way, you can support all SoCs that have QE and/or Fman, without making the code work only on the T1040. Don't forget to test other boards with QE and Fman before posting patches so that you know you didn't break any other boards.