ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI

Allwinner A20/A31 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI.

Signed-off-by Carlo Caione <[email protected]>

---
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-sunxi-nmi.c | 228 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 229 insertions(+)
 create mode 100644 drivers/irqchip/irq-sunxi-nmi.c

drivers/irqchip/Makefile +1 -0

index c60b901..e31d4d6 100644
@@ -11,6 +11,7 @@ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
 obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o
 obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o
+obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi-nmi.o
 obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
 obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o

drivers/irqchip/irq-sunxi-nmi.c new file +59 -0

new file mode 100644
index 0000000..a2b7373
@@ -0,0 +1,228 @@
+/*
+ * Allwinner A20/A31 SoCs NMI IRQ chip driver.
+ *
+ * Carlo Caione <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip/chained_irq.h>
+#include "irqchip.h"
+
+#define SUNXI_NMI_SRC_TYPE_MASK	0x00000003
+
+enum {
+	SUNXI_SRC_TYPE_LEVEL_LOW = 0,
+	SUNXI_SRC_TYPE_EDGE_FALLING,
+	SUNXI_SRC_TYPE_LEVEL_HIGH,
+	SUNXI_SRC_TYPE_EDGE_RISING,
+};
+
+struct sunxi_sc_nmi_reg_offs {
+	u32 ctrl;
+	u32 pend;
+	u32 enable;
+};
+
+static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
+	.ctrl	= 0x00,
+	.pend	= 0x04,
+	.enable	= 0x08,
+};
+
+static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
+	.ctrl	= 0x00,
+	.pend	= 0x04,
+	.enable	= 0x34,
+};
+
+/*
+ * Ack level interrupts right before unmask
+ *
+ * In case of level-triggered interrupt, IRQ line must be acked before it
+ * is unmasked or else a double-interrupt is triggered
+ */
+
+static void sunxi_sc_nmi_ack_and_unmask(struct irq_data *d)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

drivers/irqchip/irq-sunxi-nmi.c new file +126 -0

+static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
+				      u32 val)
+{
+	irq_reg_writel(val, gc->reg_base + off);
+}
+
+static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
+{
+	return irq_reg_readl(gc->reg_base + off);
+}
+
+static void sunxi_sc_nmi_handle_irq(unsigned int irq, struct irq_desc *desc)
+{
+	struct irq_domain *domain = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_get_chip(irq);
+	unsigned int virq = irq_find_mapping(domain, 0);
+
+	chained_irq_enter(chip, desc);
+	generic_handle_irq(virq);
+	chained_irq_exit(chip, desc);
+}
+
+static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
+{
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+	struct irq_chip_type *ct = gc->chip_types;
+	u32 src_type_reg;
+	u32 ctrl_off = ct->regs.type;
+	unsigned int src_type;
+	unsigned int i;
+
+	irq_gc_lock(gc);
+
+	switch (flow_type & IRQF_TRIGGER_MASK) {
+	case IRQ_TYPE_EDGE_FALLING:
+		src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		src_type = SUNXI_SRC_TYPE_EDGE_RISING;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_NONE:
+	case IRQ_TYPE_LEVEL_LOW:
+		src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
+		break;
+	default:
+		irq_gc_unlock(gc);
+		pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
+			__func__, data->irq);
+		return -EBADR;
+	}
+
+	irqd_set_trigger_type(data, flow_type);
+	irq_setup_alt_chip(data, flow_type);
+
+	for (i = 0; i <= gc->num_ct; i++, ct++)
+		if (ct->type & flow_type)
+			ctrl_off = ct->regs.type;
+
+	src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
+	src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
+	src_type_reg |= src_type;
+	sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
+
+	irq_gc_unlock(gc);
+
+	return IRQ_SET_MASK_OK;
+}
+
+static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
+					struct sunxi_sc_nmi_reg_offs *reg_offs)
+{
+	struct irq_domain *domain;
+	struct irq_chip_generic *gc;
+	unsigned int irq;
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+	int ret;
+
+
+	domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
+	if (!domain) {
+		pr_err("%s: Could not register interrupt domain.\n", node->name);
+		return -ENOMEM;
+	}
+
+	ret = irq_alloc_domain_generic_chips(domain, 1, 2, node->name,
+					     handle_level_irq, clr, 0,
+					     IRQ_GC_INIT_MASK_CACHE);
+	if (ret) {
+		 pr_err("%s: Could not allocate generic interrupt chip.\n",
+			 node->name);
+		 goto fail_irqd_remove;
+	}
+
+	irq = irq_of_parse_and_map(node, 0);
+	if (irq <= 0) {
+		pr_err("%s: unable to parse irq\n", node->name);
+		ret = -EINVAL;
+		goto fail_irqd_remove;
+	}
+
+	gc = irq_get_domain_generic_chip(domain, 0);
+	gc->reg_base = of_iomap(node, 0);
+	if (!gc->reg_base) {
+		pr_err("%s: unable to map resource\n", node->name);
+		ret = -ENOMEM;
+		goto fail_irqd_remove;
+	}
+
+	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;
+	gc->chip_types[0].chip.irq_ack		= irq_gc_ack_set_bit;
+	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
+	gc->chip_types[0].chip.irq_unmask	= sunxi_sc_nmi_ack_and_unmask;
+	gc->chip_types[0].chip.irq_set_type	= sunxi_sc_nmi_set_type;
+	gc->chip_types[0].regs.ack		= reg_offs->pend;
+	gc->chip_types[0].regs.mask		= reg_offs->enable;
+	gc->chip_types[0].regs.type		= reg_offs->ctrl;
+
+	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;
+	gc->chip_types[1].chip.name		= gc->chip_types[0].chip.name;
+	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;
+	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
+	gc->chip_types[1].chip.irq_unmask	= sunxi_sc_nmi_ack_and_unmask;
+	gc->chip_types[1].chip.irq_set_type	= sunxi_sc_nmi_set_type;

drivers/irqchip/irq-sunxi-nmi.c new file +5 -0

+
+	return 0;
+
+fail_irqd_remove:
+	irq_domain_remove(domain);

Hi Carlo,

Quoted 94 lines · Carlo Caione

Allwinner A20/A31 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI.

Signed-off-by Carlo Caione <[email protected]>

---
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-sunxi-nmi.c | 228 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 229 insertions(+)
 create mode 100644 drivers/irqchip/irq-sunxi-nmi.c

drivers/irqchip/Makefile +1 -0

index c60b901..e31d4d6 100644
@@ -11,6 +11,7 @@ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)        += irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)            += irq-moxart.o
 obj-$(CONFIG_ORION_IRQCHIP)          += irq-orion.o
 obj-$(CONFIG_ARCH_SUNXI)             += irq-sun4i.o
+obj-$(CONFIG_ARCH_SUNXI)             += irq-sunxi-nmi.o
 obj-$(CONFIG_ARCH_SPEAR3XX)          += spear-shirq.o
 obj-$(CONFIG_ARM_GIC)                        += irq-gic.o
 obj-$(CONFIG_ARM_NVIC)                       += irq-nvic.o

drivers/irqchip/irq-sunxi-nmi.c new file +65 -0

new file mode 100644
index 0000000..a2b7373
@@ -0,0 +1,228 @@
+/*
+ * Allwinner A20/A31 SoCs NMI IRQ chip driver.
+ *
+ * Carlo Caione <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip/chained_irq.h>
+#include "irqchip.h"
+
+#define SUNXI_NMI_SRC_TYPE_MASK      0x00000003
+
+enum {
+     SUNXI_SRC_TYPE_LEVEL_LOW = 0,
+     SUNXI_SRC_TYPE_EDGE_FALLING,
+     SUNXI_SRC_TYPE_LEVEL_HIGH,
+     SUNXI_SRC_TYPE_EDGE_RISING,
+};
+
+struct sunxi_sc_nmi_reg_offs {
+     u32 ctrl;
+     u32 pend;
+     u32 enable;
+};
+
+static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
+     .ctrl   = 0x00,
+     .pend   = 0x04,
+     .enable = 0x08,
+};
+
+static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
+     .ctrl   = 0x00,
+     .pend   = 0x04,
+     .enable = 0x34,
+};
+
+/*
+ * Ack level interrupts right before unmask
+ *
+ * In case of level-triggered interrupt, IRQ line must be acked before it
+ * is unmasked or else a double-interrupt is triggered
+ */
+
+static void sunxi_sc_nmi_ack_and_unmask(struct irq_data *d)
+{
+     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+     struct irq_chip_type *ct = irq_data_get_chip_type(d);
+     u32 mask = d->mask;
+
+     if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
+             ct->chip.irq_ack(d);
+

drivers/irqchip/irq-sunxi-nmi.c line 69

Quoted 4 lines

drivers/irqchip/irq-sunxi-nmi.c new file +4 -0

+     irq_gc_lock(gc);
+     irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
+     irq_gc_unlock(gc);
+}

Hmmm, handle_level_irq seems to be doing exactly that already. It first masks and acks the interrupts, and then unmask it, so we should be fine, don't we?

Quoted 132 lines

drivers/irqchip/irq-sunxi-nmi.c new file +132 -0

+static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
+                                   u32 val)
+{
+     irq_reg_writel(val, gc->reg_base + off);
+}
+
+static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
+{
+     return irq_reg_readl(gc->reg_base + off);
+}
+
+static void sunxi_sc_nmi_handle_irq(unsigned int irq, struct irq_desc *desc)
+{
+     struct irq_domain *domain = irq_desc_get_handler_data(desc);
+     struct irq_chip *chip = irq_get_chip(irq);
+     unsigned int virq = irq_find_mapping(domain, 0);
+
+     chained_irq_enter(chip, desc);
+     generic_handle_irq(virq);
+     chained_irq_exit(chip, desc);
+}
+
+static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
+{
+     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+     struct irq_chip_type *ct = gc->chip_types;
+     u32 src_type_reg;
+     u32 ctrl_off = ct->regs.type;
+     unsigned int src_type;
+     unsigned int i;
+
+     irq_gc_lock(gc);
+
+     switch (flow_type & IRQF_TRIGGER_MASK) {
+     case IRQ_TYPE_EDGE_FALLING:
+             src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
+             break;
+     case IRQ_TYPE_EDGE_RISING:
+             src_type = SUNXI_SRC_TYPE_EDGE_RISING;
+             break;
+     case IRQ_TYPE_LEVEL_HIGH:
+             src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
+             break;
+     case IRQ_TYPE_NONE:
+     case IRQ_TYPE_LEVEL_LOW:
+             src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
+             break;
+     default:
+             irq_gc_unlock(gc);
+             pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
+                     __func__, data->irq);
+             return -EBADR;
+     }
+
+     irqd_set_trigger_type(data, flow_type);
+     irq_setup_alt_chip(data, flow_type);
+
+     for (i = 0; i <= gc->num_ct; i++, ct++)
+             if (ct->type & flow_type)
+                     ctrl_off = ct->regs.type;
+
+     src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
+     src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
+     src_type_reg |= src_type;
+     sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
+
+     irq_gc_unlock(gc);
+
+     return IRQ_SET_MASK_OK;
+}
+
+static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
+                                     struct sunxi_sc_nmi_reg_offs *reg_offs)
+{
+     struct irq_domain *domain;
+     struct irq_chip_generic *gc;
+     unsigned int irq;
+     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+     int ret;
+
+
+     domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
+     if (!domain) {
+             pr_err("%s: Could not register interrupt domain.\n", node->name);
+             return -ENOMEM;
+     }
+
+     ret = irq_alloc_domain_generic_chips(domain, 1, 2, node->name,
+                                          handle_level_irq, clr, 0,
+                                          IRQ_GC_INIT_MASK_CACHE);
+     if (ret) {
+              pr_err("%s: Could not allocate generic interrupt chip.\n",
+                      node->name);
+              goto fail_irqd_remove;
+     }
+
+     irq = irq_of_parse_and_map(node, 0);
+     if (irq <= 0) {
+             pr_err("%s: unable to parse irq\n", node->name);
+             ret = -EINVAL;
+             goto fail_irqd_remove;
+     }
+
+     gc = irq_get_domain_generic_chip(domain, 0);
+     gc->reg_base = of_iomap(node, 0);
+     if (!gc->reg_base) {
+             pr_err("%s: unable to map resource\n", node->name);
+             ret = -ENOMEM;
+             goto fail_irqd_remove;
+     }
+
+     gc->chip_types[0].type                  = IRQ_TYPE_LEVEL_MASK;
+     gc->chip_types[0].chip.irq_ack          = irq_gc_ack_set_bit;
+     gc->chip_types[0].chip.irq_mask         = irq_gc_mask_clr_bit;
+     gc->chip_types[0].chip.irq_unmask       = sunxi_sc_nmi_ack_and_unmask;
+     gc->chip_types[0].chip.irq_set_type     = sunxi_sc_nmi_set_type;
+     gc->chip_types[0].regs.ack              = reg_offs->pend;
+     gc->chip_types[0].regs.mask             = reg_offs->enable;
+     gc->chip_types[0].regs.type             = reg_offs->ctrl;
+
+     gc->chip_types[1].type                  = IRQ_TYPE_EDGE_BOTH;
+     gc->chip_types[1].chip.name             = gc->chip_types[0].chip.name;
+     gc->chip_types[1].chip.irq_ack          = irq_gc_ack_set_bit;
+     gc->chip_types[1].chip.irq_mask         = irq_gc_mask_clr_bit;
+     gc->chip_types[1].chip.irq_unmask       = sunxi_sc_nmi_ack_and_unmask;
+     gc->chip_types[1].chip.irq_set_type     = sunxi_sc_nmi_set_type;
+     gc->chip_types[1].regs.ack              = reg_offs->pend;
+     gc->chip_types[1].regs.mask             = reg_offs->enable;
+     gc->chip_types[1].regs.type             = reg_offs->ctrl;
+     gc->chip_types[1].handler               = handle_edge_irq;
+
+     irq_set_handler_data(irq, domain);

drivers/irqchip/irq-sunxi-nmi.c line 206

Quoted 4 lines

drivers/irqchip/irq-sunxi-nmi.c new file +4 -0

+     irq_set_chained_handler(irq, sunxi_sc_nmi_handle_irq);
+
+     sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
+     sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);

I really wonder whether it makes sense to have a generic chip here. It seems to be much more complicated than it should. It's only about a single interrupt interrupt chip here.

Quoted 9 lines

drivers/irqchip/irq-sunxi-nmi.c new file +9 -0

+
+     return 0;
+
+fail_irqd_remove:
+     irq_domain_remove(domain);
+
+     return ret;
+}
+

drivers/irqchip/irq-sunxi-nmi.c line 221

Quoted 6 lines

drivers/irqchip/irq-sunxi-nmi.c new file +6 -0

+static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+     return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs);
+}
+IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-sc-nmi", sun6i_sc_nmi_irq_init);

I'm curious, where did you get these infos on the A31? :)

drivers/irqchip/irq-sunxi-nmi.c line 228

Quoted 7 lines

drivers/irqchip/irq-sunxi-nmi.c new file +6 -0

+static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+     return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
+}
+IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-sc-nmi", sun7i_sc_nmi_irq_init);

The compatibles should be sun6i-a31-* and sun7i-a20-*.

Quoted 16 lines

Quoted 16 lines

drivers/irqchip/irq-sunxi-nmi.c new file +16 -0

+/*
+ * Ack level interrupts right before unmask
+ *
+ * In case of level-triggered interrupt, IRQ line must be acked before it
+ * is unmasked or else a double-interrupt is triggered
+ */
+
+static void sunxi_sc_nmi_ack_and_unmask(struct irq_data *d)
+{
+     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+     struct irq_chip_type *ct = irq_data_get_chip_type(d);
+     u32 mask = d->mask;
+
+     if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
+             ct->chip.irq_ack(d);
+

Quoted 8 lines

drivers/irqchip/irq-sunxi-nmi.c line 69

Quoted 4 lines

drivers/irqchip/irq-sunxi-nmi.c new file +4 -0

+     irq_gc_lock(gc);
+     irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
+     irq_gc_unlock(gc);
+}

Hmmm, handle_level_irq seems to be doing exactly that already. It first masks and acks the interrupts, and then unmask it, so we should be fine, don't we?

We don't, or at least handle_level_irq doesn't work for all the cases.

Let's say (i.e. this is the cubieboard2 case) that to the irqchip is connected to the IRQ line of a PMIC accessed by I2C. In this case we cannot mask/ack the interrupt on the originating device in the hard interrupt handler (in which handle_level_irq is) since we need to access the I2C bus in an non-interrupt context.

ACKing the IRQ in handle_level_irq at this point is pretty much useless since we still have to ACK the IRQs on the originating device and this will be done in a IRQ thread started after the hard IRQ handler.

sunxi_sc_nmi_ack_and_unmask is therefore called (by irq_finalize_oneshot) after the IRQ thread has been executed. After the IRQ thread has ACKed the IRQs on the originating device we can finally ACK and unmask again the NMI.

Quoted 133 lines

Quoted 133 lines

drivers/irqchip/irq-sunxi-nmi.c new file +132 -0

+static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
+                                   u32 val)
+{
+     irq_reg_writel(val, gc->reg_base + off);
+}
+
+static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
+{
+     return irq_reg_readl(gc->reg_base + off);
+}
+
+static void sunxi_sc_nmi_handle_irq(unsigned int irq, struct irq_desc *desc)
+{
+     struct irq_domain *domain = irq_desc_get_handler_data(desc);
+     struct irq_chip *chip = irq_get_chip(irq);
+     unsigned int virq = irq_find_mapping(domain, 0);
+
+     chained_irq_enter(chip, desc);
+     generic_handle_irq(virq);
+     chained_irq_exit(chip, desc);
+}
+
+static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
+{
+     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+     struct irq_chip_type *ct = gc->chip_types;
+     u32 src_type_reg;
+     u32 ctrl_off = ct->regs.type;
+     unsigned int src_type;
+     unsigned int i;
+
+     irq_gc_lock(gc);
+
+     switch (flow_type & IRQF_TRIGGER_MASK) {
+     case IRQ_TYPE_EDGE_FALLING:
+             src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
+             break;
+     case IRQ_TYPE_EDGE_RISING:
+             src_type = SUNXI_SRC_TYPE_EDGE_RISING;
+             break;
+     case IRQ_TYPE_LEVEL_HIGH:
+             src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
+             break;
+     case IRQ_TYPE_NONE:
+     case IRQ_TYPE_LEVEL_LOW:
+             src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
+             break;
+     default:
+             irq_gc_unlock(gc);
+             pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
+                     __func__, data->irq);
+             return -EBADR;
+     }
+
+     irqd_set_trigger_type(data, flow_type);
+     irq_setup_alt_chip(data, flow_type);
+
+     for (i = 0; i <= gc->num_ct; i++, ct++)
+             if (ct->type & flow_type)
+                     ctrl_off = ct->regs.type;
+
+     src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
+     src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
+     src_type_reg |= src_type;
+     sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
+
+     irq_gc_unlock(gc);
+
+     return IRQ_SET_MASK_OK;
+}
+
+static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
+                                     struct sunxi_sc_nmi_reg_offs *reg_offs)
+{
+     struct irq_domain *domain;
+     struct irq_chip_generic *gc;
+     unsigned int irq;
+     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+     int ret;
+
+
+     domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
+     if (!domain) {
+             pr_err("%s: Could not register interrupt domain.\n", node->name);
+             return -ENOMEM;
+     }
+
+     ret = irq_alloc_domain_generic_chips(domain, 1, 2, node->name,
+                                          handle_level_irq, clr, 0,
+                                          IRQ_GC_INIT_MASK_CACHE);
+     if (ret) {
+              pr_err("%s: Could not allocate generic interrupt chip.\n",
+                      node->name);
+              goto fail_irqd_remove;
+     }
+
+     irq = irq_of_parse_and_map(node, 0);
+     if (irq <= 0) {
+             pr_err("%s: unable to parse irq\n", node->name);
+             ret = -EINVAL;
+             goto fail_irqd_remove;
+     }
+
+     gc = irq_get_domain_generic_chip(domain, 0);
+     gc->reg_base = of_iomap(node, 0);
+     if (!gc->reg_base) {
+             pr_err("%s: unable to map resource\n", node->name);
+             ret = -ENOMEM;
+             goto fail_irqd_remove;
+     }
+
+     gc->chip_types[0].type                  = IRQ_TYPE_LEVEL_MASK;
+     gc->chip_types[0].chip.irq_ack          = irq_gc_ack_set_bit;
+     gc->chip_types[0].chip.irq_mask         = irq_gc_mask_clr_bit;
+     gc->chip_types[0].chip.irq_unmask       = sunxi_sc_nmi_ack_and_unmask;
+     gc->chip_types[0].chip.irq_set_type     = sunxi_sc_nmi_set_type;
+     gc->chip_types[0].regs.ack              = reg_offs->pend;
+     gc->chip_types[0].regs.mask             = reg_offs->enable;
+     gc->chip_types[0].regs.type             = reg_offs->ctrl;
+
+     gc->chip_types[1].type                  = IRQ_TYPE_EDGE_BOTH;
+     gc->chip_types[1].chip.name             = gc->chip_types[0].chip.name;
+     gc->chip_types[1].chip.irq_ack          = irq_gc_ack_set_bit;
+     gc->chip_types[1].chip.irq_mask         = irq_gc_mask_clr_bit;
+     gc->chip_types[1].chip.irq_unmask       = sunxi_sc_nmi_ack_and_unmask;
+     gc->chip_types[1].chip.irq_set_type     = sunxi_sc_nmi_set_type;
+     gc->chip_types[1].regs.ack              = reg_offs->pend;
+     gc->chip_types[1].regs.mask             = reg_offs->enable;
+     gc->chip_types[1].regs.type             = reg_offs->ctrl;
+     gc->chip_types[1].handler               = handle_edge_irq;
+
+     irq_set_handler_data(irq, domain);

Quoted 8 lines

drivers/irqchip/irq-sunxi-nmi.c line 206

Quoted 4 lines

drivers/irqchip/irq-sunxi-nmi.c new file +4 -0

+     irq_set_chained_handler(irq, sunxi_sc_nmi_handle_irq);
+
+     sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
+     sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);

I really wonder whether it makes sense to have a generic chip here. It seems to be much more complicated than it should. It's only about a single interrupt interrupt chip here.

I agree but is there any other way to manage the NMI without the driver of the device connected to NMI having to worry about acking/masking/unmasking/ etc..?

Quoted 6 lines

Quoted 4 lines

Quoted 2 lines

+/* + * Ack level interrupts right before unmask + * + * In case of level-triggered interrupt, IRQ line must be acked before it + * is unmasked or else a double-interrupt is triggered + */ + +static void sunxi_sc_nmi_ack_and_unmask(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct irq_chip_type *ct = irq_data_get_chip_type(d); + u32 mask = d->mask; + + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) + ct->chip.irq_ack(d); + + irq_gc_lock(gc); + irq_reg_writel(mask, gc->reg_base + ct->regs.mask); +
irq_gc_unlock(gc); +}

Hmmm, handle_level_irq seems to be doing exactly that already. It first masks and acks the interrupts, and then unmask it, so we should be fine, don't we?

We don't, or at least handle_level_irq doesn't work for all the cases.

This is what I find weird :)

Quoted 1 line

Let's say (i.e. this is the cubieboard2 case) that to the irqchip is connected to the IRQ line of a PMIC accessed by I2C. In this case we cannot mask/ack the interrupt on the originating device in the hard interrupt handler (in which handle_level_irq is) since we need to access the I2C bus in an non-interrupt context.

We agree here.

Quoted 1 line

ACKing the IRQ in handle_level_irq at this point is pretty much useless since we still have to ACK the IRQs on the originating device and this will be done in a IRQ thread started after the hard IRQ handler.

Ok, so what you're saying is that you want to adress this case:

handle_level_irq | device device | mask ack handler irq acked unmask | | | | | | v v v v v v

NMI -> GIC: +--------+ +----------------- ---------------+ +-----+

PMIC -> NMI: +-+ +-+ ------------+ +-----------+ +--------------------

Right?

handle_level_irq | device device | mask ack handler irq acked unmask | | | | | | v v v v v v

NMI -> GIC: +------------------------------+ ---------------+ +--

PMIC -> NMI: +-------------------------+ ------------+ +----------

But in this case, you would have two events coming from your device (the two rising edges), so you'd expect two interrupts. And in the case of a level triggered interrupt, the device would keep the interrupt line active until it's unmasked, so we wouldn't end up with this either.

Quoted 1 line

sunxi_sc_nmi_ack_and_unmask is therefore called (by irq_finalize_oneshot) after the IRQ thread has been executed. After the IRQ thread has ACKed the IRQs on the originating device we can finally ACK and unmask again the NMI.

And what happens if you get a new interrupt right between the end of the handler and the unmask?

Quoted 3 lines

Quoted 1 line

I really wonder whether it makes sense to have a generic chip here. It seems to be much more complicated than it should. It's only about a single interrupt interrupt chip here.

I agree but is there any other way to manage the NMI without the driver of the device connected to NMI having to worry about acking/masking/unmasking/ etc..?

Yes, just declare a "raw" irqchip. Pretty much like we do on irq-sun4i for example.

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi,

On 01/28/2014 11:40 AM, Maxime Ripard wrote:

Jumping in here to try and clarify things, or so I hope at least :)

No, the IRQ from the PMIC is a level sensitive IRQ, so it would look like this:

The PMIC irq line won't go low until an i2c write to its irq status registers write-clears all status bits for which the corresponding bit in the irq-mask register is set.

And the only reason the NMI -> GIC also goes low is because the unmask operation writes a second ack to the NMI controller in the unmask callback of the NMI controller driver.

Note that we cannot use edge triggered interrupts here because the PMIC has the typical setup with multiple irq status bits driving a single irq line, so the irq handler does read irq-status, handle stuff, write-clear irq-status. And if any other irq-status bits get set between the read and write-clear the PMIC -> NMI line will stay high, as it should since there are more interrupts to handle.

Quoted 11 lines

But in this case, you would have two events coming from your device (the two rising edges), so you'd expect two interrupts. And in the case of a level triggered interrupt, the device would keep the interrupt line active until it's unmasked, so we wouldn't end up with this either.

Quoted 4 lines

sunxi_sc_nmi_ack_and_unmask is therefore called (by irq_finalize_oneshot) after the IRQ thread has been executed. After the IRQ thread has ACKed the IRQs on the originating device we can finally ACK and unmask again the NMI.

Quoted 2 lines

And what happens if you get a new interrupt right between the end of the handler and the unmask?

The implicit ack done by the unmask will be ignored if the NMI line is still high, just like the initial ack is ignored (which is why we need the mask), and when the unmask completes the irq will immediately retrigger, as it should.

Quoted 8 lines

Quoted 7 lines

Quoted 3 lines

I really wonder whether it makes sense to have a generic chip here. It seems to be much more complicated than it should. It's only about a single interrupt interrupt chip here.

I agree but is there any other way to manage the NMI without the driver of the device connected to NMI having to worry about acking/masking/unmasking/ etc..?

Quoted 2 lines

Yes, just declare a "raw" irqchip. Pretty much like we do on irq-sun4i for example.

Hmm, I'm not going to say that using a raw irqchip here is a bad idea, it sounds like it would be better.

But I don't think this will solve the need the mask / umask. The problem is we need to do an i2c write to clear the interrupt source, which needs to be done from a thread / workqueue. So when the interrupt handler finishes the source won't be cleared yet, and AFAIK then only way to deal with this is to mask the interrupt until we've cleared the interrupt source.

Hi,

Quoted 8 lines · Hans de Goede

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi,

On 01/28/2014 11:40 AM, Maxime Ripard wrote:

Jumping in here to try and clarify things, or so I hope at least :)

Sure :)

Quoted 2 lines

No, the IRQ from the PMIC is a level sensitive IRQ, so it would look like this:

Hmm, your mailer seems to have mangled your drawing :(

Quoted 3 lines

The PMIC irq line won't go low until an i2c write to its irq status registers write-clears all status bits for which the corresponding bit in the irq-mask register is set.

Which makes sense too

Quoted 3 lines

And the only reason the NMI -> GIC also goes low is because the unmask operation writes a second ack to the NMI controller in the unmask callback of the NMI controller driver.

Yes, and this is exactly what I don't understand. You shouldn't need that ack in first place, since it's been done already right after the unmask.

Quoted 6 lines

Note that we cannot use edge triggered interrupts here because the PMIC has the typical setup with multiple irq status bits driving a single irq line, so the irq handler does read irq-status, handle stuff, write-clear irq-status. And if any other irq-status bits get set between the read and write-clear the PMIC -> NMI line will stay high, as it should since there are more interrupts to handle.

Yep, the edge-thing was just the only case I could think of where it could lead to troubles.

In what you're saying, which makes total sense, if we don't do the ack, as soon as the irq will be unmasked, since the level is high, the handler will be called again, treat the new interrupts, and so on. I don't see how this is an issue actually.

Quoted 11 lines

Quoted 11 lines

But in this case, you would have two events coming from your device (the two rising edges), so you'd expect two interrupts. And in the case of a level triggered interrupt, the device would keep the interrupt line active until it's unmasked, so we wouldn't end up with this either.

Quoted 4 lines

sunxi_sc_nmi_ack_and_unmask is therefore called (by irq_finalize_oneshot) after the IRQ thread has been executed. After the IRQ thread has ACKed the IRQs on the originating device we can finally ACK and unmask again the NMI.

Quoted 7 lines

Quoted 2 lines

And what happens if you get a new interrupt right between the end of the handler and the unmask?

The implicit ack done by the unmask will be ignored if the NMI line is still high, just like the initial ack is ignored (which is why we need the mask), and when the unmask completes the irq will immediately retrigger, as it should.

Yeah, but why do we need the ack in the first place? I can't think of a case where the ACK would be doing something useful. Either:
- there is no new interrupts between the mask/ack and the unmask, so there's no interrupt to ack.
- There's a new interrupt between the mask/ack and the unmask. There's two more cases here:
* The interrupt came before the device handler kicked in, and the handler will treat it/ack it: No issue
* The interrupt comes right after the handler has been acking its interrupt, the level stays high, your handler is called once again, you can treat it: No issue

Quoted 8 lines

Quoted 8 lines

Quoted 7 lines

Quoted 3 lines

I really wonder whether it makes sense to have a generic chip here. It seems to be much more complicated than it should. It's only about a single interrupt interrupt chip here.

I agree but is there any other way to manage the NMI without the driver of the device connected to NMI having to worry about acking/masking/unmasking/ etc..?

Quoted 5 lines

Quoted 2 lines

Yes, just declare a "raw" irqchip. Pretty much like we do on irq-sun4i for example.

Hmm, I'm not going to say that using a raw irqchip here is a bad idea, it sounds like it would be better.

There's none. It was a separate comment :)

Quoted 6 lines

But I don't think this will solve the need the mask / umask. The problem is we need to do an i2c write to clear the interrupt source, which needs to be done from a thread / workqueue. So when the interrupt handler finishes the source won't be cleared yet, and AFAIK then only way to deal with this is to mask the interrupt until we've cleared the interrupt source.

Yes, but the interrupt is still masked during the time between the "hard" handler and the thread, so there's no way you can get an interrupt flood during that time.

Hi,

Quoted 25 lines · Maxime Ripard

Hi,

Quoted 8 lines · Hans de Goede

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi,

On 01/28/2014 11:40 AM, Maxime Ripard wrote:

Jumping in here to try and clarify things, or so I hope at least :)

Sure :)

Quoted 2 lines

No, the IRQ from the PMIC is a level sensitive IRQ, so it would look like this:

Hmm, your mailer seems to have mangled your drawing :(

Quoted 3 lines

The PMIC irq line won't go low until an i2c write to its irq status registers write-clears all status bits for which the corresponding bit in the irq-mask register is set.

Which makes sense too

Quoted 7 lines

Quoted 3 lines

And the only reason the NMI -> GIC also goes low is because the unmask operation writes a second ack to the NMI controller in the unmask callback of the NMI controller driver.

Yes, and this is exactly what I don't understand. You shouldn't need that ack in first place, since it's been done already right after the unmask.

But the first ack is ignored since the IRQ line is still maintained asserted by PMIC.

Quoted 7 lines

Quoted 6 lines

Note that we cannot use edge triggered interrupts here because the PMIC has the typical setup with multiple irq status bits driving a single irq line, so the irq handler does read irq-status, handle stuff, write-clear irq-status. And if any other irq-status bits get set between the read and write-clear the PMIC -> NMI line will stay high, as it should since there are more interrupts to handle.

Quoted 7 lines

Yep, the edge-thing was just the only case I could think of where it could lead to troubles.

In what you're saying, which makes total sense, if we don't do the ack, as soon as the irq will be unmasked, since the level is high, the handler will be called again, treat the new interrupts, and so on. I don't see how this is an issue actually.

This is exactly why in unmask callback we first ACK and then unmask. So, if the line is still maintained up by PMIC then a new interrupt is raised otherwise nothing happens.

Quoted 19 lines

Quoted 11 lines

Quoted 11 lines

But in this case, you would have two events coming from your device (the two rising edges), so you'd expect two interrupts. And in the case of a level triggered interrupt, the device would keep the interrupt line active until it's unmasked, so we wouldn't end up with this either.

Quoted 4 lines

sunxi_sc_nmi_ack_and_unmask is therefore called (by irq_finalize_oneshot) after the IRQ thread has been executed. After the IRQ thread has ACKed the IRQs on the originating device we can finally ACK and unmask again the NMI.

Quoted 7 lines

Quoted 2 lines

And what happens if you get a new interrupt right between the end of the handler and the unmask?

The implicit ack done by the unmask will be ignored if the NMI line is still high, just like the initial ack is ignored (which is why we need the mask), and when the unmask completes the irq will immediately retrigger, as it should.

Quoted 11 lines

Yeah, but why do we need the ack in the first place? I can't think of a case where the ACK would be doing something useful. Either:
- there is no new interrupts between the mask/ack and the unmask, so there's no interrupt to ack.
- There's a new interrupt between the mask/ack and the unmask. There's two more cases here:
* The interrupt came before the device handler kicked in, and the handler will treat it/ack it: No issue
* The interrupt comes right after the handler has been acking its interrupt, the level stays high, your handler is called once again, you can treat it: No issue

AFAIU the problem here is that the only ACK that is able to assert the line NMI -> GIC is the ACK by the unmask callback. All the others ACKs before that one are ignored by the NMI controller since the line PMIC -> NMI is still asserted.

So, to sum things up, what you see is something like:

handle_level_irq
| device device
| mask ack handler irq acked unmask
| | | | | |
v v v v v v

NMI -> GIC:

               +--------+     +---------------------
---------------+        +-----+

PMIC -> NMI:

            +-------------------------+
------------+                         +-------------

And you get a "rogue" retrigger because the NMI -> GIC level went up again.

I'm not exactly sure on how to fix this. Maybe by adding a call to the irqchip's ack just before the unmask in irq_finalize_oneshot?

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi,

On 01/28/2014 11:40 AM, Maxime Ripard wrote:

Jumping in here to try and clarify things, or so I hope at least :)

The PMIC irq line won't go low until an i2c write to its irq status registers write-clears all status bits for which the corresponding bit in the irq-mask register is set.

And the only reason the NMI -> GIC also goes low is because the unmask operation writes a second ack to the NMI controller in the unmask callback of the NMI controller driver.

Hmm, I'm not going to say that using a raw irqchip here is a bad idea, it sounds like it would be better.

But I don't think this will solve the need the mask / umask. The problem is we need to do an i2c write to clear the interrupt source, which needs to be done from a thread / workqueue. So when the interrupt handler finishes the source won't be cleared yet, and AFAIK then only way to deal with this is to mask the interrupt until we've cleared the interrupt source.

Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.

Changes since v1:
- added binding document

Changes since v2:
- fixed trigger type in DTS
- new explanations in binding documentation
- added support for A31 (sun6i)