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ARM: tegra: use 2 address cells for Tegra124 DT

PATCH New Stephen Warren 1 participant 2 messages Mar 4, 2014 – Mar 5, 2014

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PATCH 1/1 ARM: tegra: use 2 address cells for Tegra124 DT

From: Stephen Warren <[email protected]>

Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space.

(I think this was suggested by Olof Johansson, but I'm not 100% sure)

---
 arch/arm/boot/dts/tegra124-venice2.dts |  54 ++++-----
 arch/arm/boot/dts/tegra124.dtsi        | 215 +++++++++++++++++----------------
 2 files changed, 137 insertions(+), 132 deletions(-)
arch/arm/boot/dts/tegra124-venice2.dts +27 -27
index 1ad686154286..86536d919ed2 100644
@@ -8,29 +8,29 @@
 	compatible = "nvidia,venice2", "nvidia,tegra124";
 
 	aliases {
-		rtc0 = "/i2c at 7000d000/pmic at 40";
-		rtc1 = "/rtc at 7000e000";
+		rtc0 = "/i2c at 0,7000d000/pmic at 40";
+		rtc1 = "/rtc at 0,7000e000";
 	};
 
 	memory {
-		reg = <0x80000000 0x80000000>;
+		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
 
-	host1x at 50000000 {
-		sor at 54540000 {
+	host1x at 0,50000000 {
+		sor at 0,54540000 {
 			status = "okay";
 
 			nvidia,dpaux = <&dpaux>;
 			nvidia,panel = <&panel>;
 		};
 
-		dpaux: dpaux at 545c0000 {
+		dpaux: dpaux at 0,545c0000 {
 			vdd-supply = <&vdd_3v3_panel>;
 			status = "okay";
 		};
 	};
 
-	pinmux: pinmux at 70000868 {
+	pinmux: pinmux at 0,70000868 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinmux_default>;
 
@@ -578,15 +578,15 @@
 		};
 	};
 
-	serial at 70006000 {
+	serial at 0,70006000 {
 		status = "okay";
 	};
 
-	pwm: pwm at 7000a000 {
+	pwm: pwm at 0,7000a000 {
 		status = "okay";
 	};
 
-	i2c at 7000c000 {
+	i2c at 0,7000c000 {
 		status = "okay";
 		clock-frequency = <100000>;
 
@@ -598,22 +598,22 @@
 		};
 	};
 
-	i2c at 7000c400 {
+	i2c at 0,7000c400 {
 		status = "okay";
 		clock-frequency = <100000>;
 	};
 
-	i2c at 7000c500 {
+	i2c at 0,7000c500 {
 		status = "okay";
 		clock-frequency = <100000>;
 	};
 
-	i2c at 7000c700 {
+	i2c at 0,7000c700 {
 		status = "okay";
 		clock-frequency = <100000>;
 	};
 
-	i2c at 7000d000 {
+	i2c at 0,7000d000 {
 		status = "okay";
 		clock-frequency = <400000>;
 
@@ -808,7 +808,7 @@
 		};
 	};
 
-	spi at 7000d400 {
+	spi at 0,7000d400 {
 		status = "okay";
 
 		cros-ec at 0 {
@@ -914,7 +914,7 @@
 		};
 	};
 
-	spi at 7000da00 {
+	spi at 0,7000da00 {
 		status = "okay";
 		spi-max-frequency = <25000000>;
 		spi-flash at 0 {
@@ -924,7 +924,7 @@
 		};
 	};
 
-	pmc at 7000e400 {
+	pmc at 0,7000e400 {
 		nvidia,invert-interrupt;
 		nvidia,suspend-mode = <1>;
 		nvidia,cpu-pwr-good-time = <500>;
@@ -935,7 +935,7 @@
 		nvidia,sys-clock-req-active-high;
 	};
 
-	sdhci at 700b0400 {
+	sdhci at 0,700b0400 {
 		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
 		status = "okay";
@@ -943,40 +943,40 @@
 		vmmc-supply = <&vddio_sdmmc3>;
 	};
 
-	sdhci at 700b0600 {
+	sdhci at 0,700b0600 {
 		status = "okay";
 		bus-width = <8>;
 	};
 
-	ahub at 70300000 {
-		i2s at 70301100 {
+	ahub at 0,70300000 {
+		i2s at 0,70301100 {
 			status = "okay";
 		};
 	};
 
-	usb at 7d000000 {
+	usb at 0,7d000000 {
 		status = "okay";
 	};
 
-	usb-phy at 7d000000 {
+	usb-phy at 0,7d000000 {
 		status = "okay";
 		vbus-supply = <&vdd_usb1_vbus>;
 	};
 
-	usb at 7d004000 {
+	usb at 0,7d004000 {
 		status = "okay";
 	};
 
-	usb-phy at 7d004000 {
+	usb-phy at 0,7d004000 {
 		status = "okay";
 		vbus-supply = <&vdd_run_cam>;
 	};
 
-	usb at 7d008000 {
+	usb at 0,7d008000 {
 		status = "okay";
 	};
 
-	usb-phy at 7d008000 {
+	usb-phy at 0,7d008000 {
 		status = "okay";
 		vbus-supply = <&vdd_usb3_vbus>;
 	};
arch/arm/boot/dts/tegra124.dtsi +110 -105

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#1 lore raw

PATCH 1/1 ARM: tegra: use 2 address cells for Tegra124 DT

Quoted 8 lines · Stephen Warren

From: Stephen Warren <[email protected]>

Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space.

(I think this was suggested by Olof Johansson, but I'm not 100% sure)

I've applied this to Tegra's for-3.15/dt branch.