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clk: exynos: add support for exynos5260 SoC

PATCH Superseded Rahul Sharma 3 participants 12 messages Mar 4, 2014 – Mar 10, 2014

Subsystems (4)
Device tree bindings Common clk Arm Samsung Exynos Samsung SoC clock drivers

v4 of 8 Superseded Latest is v8 →

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Rahul Sharma

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#0 lore raw

v4 cover clk: exynos: add support for exynos5260 SoC

From: Rahul Sharma <[email protected]>

Add clock support for exynos5260 SoC.

This series is based on Kukjin's for-next and
Mike's clk-next branches.

V4:
1) Rework clock file as per Tomasz review comments at
http://www.spinics.net/lists/arm-kernel/msg310116.html.

V3:
1) Removed "samsung,exynos5260-clock" property from clock files.
2) Replaced "__SPIN_LOCK_UNLOCKED(lock)" with spin_lock_init.
3) Removed '(' and ')' around numeric constants in macros.

V2:
1) Move suspend resume handling to Exynos5410 Clock file.
2) Removed Unused Macros and Condition checks for Exynos5260.
3) Add spin lock to clock provider context.
4) Add clock provider context for Exynos5410.
5) Uniform implementation for callbacks for PLL2550xx.
6) Split Exynos5260 clock file patch to bring it under 100 Kb limit.
7) Replace aclk/pclk/hclk gates with combined gates.
8) Remove CLK_IGNORE_UNUSED flag for gate clocks.
Pankaj Dubey (1):
clk/samsung: add support for pll2550xx

Rahul Sharma (4):
clk/samsung: add support for multiple clock providers clk/samsung: add support for pll2650xx clk/exynos5260: add macros and documentation for exynos5260 clk/exynos5260: add clock file for exynos5260

 .../devicetree/bindings/clock/exynos5260-clock.txt |   55 +
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos4.c                  |   47 +-
 drivers/clk/samsung/clk-exynos5250.c               |   25 +-
 drivers/clk/samsung/clk-exynos5260.c               | 1933 ++++++++++++++++++++
 drivers/clk/samsung/clk-exynos5260.h               |  448 +++++
 drivers/clk/samsung/clk-exynos5420.c               |   24 +-
 drivers/clk/samsung/clk-exynos5440.c               |   18 +-
 drivers/clk/samsung/clk-pll.c                      |  222 ++-
 drivers/clk/samsung/clk-pll.h                      |    2 +
 drivers/clk/samsung/clk-s3c64xx.c                  |   44 +-
 drivers/clk/samsung/clk.c                          |  115 +-
 drivers/clk/samsung/clk.h                          |   72 +-
 include/dt-bindings/clk/exynos5260-clk.h           |  233 +++
 14 files changed, 3090 insertions(+), 149 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
 create mode 100644 drivers/clk/samsung/clk-exynos5260.c
 create mode 100644 drivers/clk/samsung/clk-exynos5260.h
 create mode 100644 include/dt-bindings/clk/exynos5260-clk.h
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v4 1/5 clk/samsung: add support for multiple clock providers

Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer.

This layer is modified accordingly to enable the support.

Clock file for exynos4, exynos5250, exynos5420, exynos5440 and S3c64xx are also modified as per changed helper functions.

Signed-off-by Rahul Sharma <[email protected]>
---
 drivers/clk/samsung/clk-exynos4.c    |   47 +++++++-------
 drivers/clk/samsung/clk-exynos5250.c |   25 +++++---
 drivers/clk/samsung/clk-exynos5420.c |   24 ++++---
 drivers/clk/samsung/clk-exynos5440.c |   18 +++---
 drivers/clk/samsung/clk-pll.c        |   14 +++--
 drivers/clk/samsung/clk-s3c64xx.c    |   44 +++++++------
 drivers/clk/samsung/clk.c            |  115 +++++++++++++++++++---------------
 drivers/clk/samsung/clk.h            |   72 ++++++++++++++-------
 8 files changed, 210 insertions(+), 149 deletions(-)
drivers/clk/samsung/clk-exynos4.c +25 -22
index b4f9672..57ed5a8 100644
@@ -1043,7 +1043,7 @@ static unsigned long exynos4_get_xom(void)
 	return xom;
 }
 
-static void __init exynos4_clk_register_finpll(void)
+static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
 {
 	struct samsung_fixed_rate_clock fclk;
 	struct clk *clk;

@@ -1066,7 +1066,7 @@ static void __init exynos4_clk_register_finpll(void)
 	fclk.parent_name = NULL;
 	fclk.flags = CLK_IS_ROOT;
 	fclk.fixed_rate = finpll_f;
-	samsung_clk_register_fixed_rate(&fclk, 1);
+	samsung_clk_register_fixed_rate(ctx, &fclk, 1);
 
 }
 

@@ -1176,22 +1176,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
 static void __init exynos4_clk_init(struct device_node *np,
 				    enum exynos4_soc soc)
 {
+	struct samsung_clk_provider *ctx;
 	exynos4_soc = soc;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base)
 		panic("%s: failed to map registers\n", __func__);
 
-	samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
 
-	samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
 			ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
 			ext_clk_match);
 
-	exynos4_clk_register_finpll();
+	exynos4_clk_register_finpll(ctx);
 
 	if (exynos4_soc == EXYNOS4210) {
-		samsung_clk_register_mux(exynos4210_mux_early,
+		samsung_clk_register_mux(ctx, exynos4210_mux_early,
 					ARRAY_SIZE(exynos4210_mux_early));
 
 		if (_get_rate("fin_pll") == 24000000) {

@@ -1205,7 +1208,7 @@ static void __init exynos4_clk_init(struct device_node *np,
 			exynos4210_plls[vpll].rate_table =
 							exynos4210_vpll_rates;
 
-		samsung_clk_register_pll(exynos4210_plls,
+		samsung_clk_register_pll(ctx, exynos4210_plls,
 					ARRAY_SIZE(exynos4210_plls), reg_base);
 	} else {
 		if (_get_rate("fin_pll") == 24000000) {

@@ -1217,42 +1220,42 @@ static void __init exynos4_clk_init(struct device_node *np,
 							exynos4x12_vpll_rates;
 		}
 
-		samsung_clk_register_pll(exynos4x12_plls,
+		samsung_clk_register_pll(ctx, exynos4x12_plls,
 					ARRAY_SIZE(exynos4x12_plls), reg_base);
 	}
 
-	samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
 			ARRAY_SIZE(exynos4_fixed_rate_clks));
-	samsung_clk_register_mux(exynos4_mux_clks,
+	samsung_clk_register_mux(ctx, exynos4_mux_clks,
 			ARRAY_SIZE(exynos4_mux_clks));
-	samsung_clk_register_div(exynos4_div_clks,
+	samsung_clk_register_div(ctx, exynos4_div_clks,
 			ARRAY_SIZE(exynos4_div_clks));
-	samsung_clk_register_gate(exynos4_gate_clks,
+	samsung_clk_register_gate(ctx, exynos4_gate_clks,
 			ARRAY_SIZE(exynos4_gate_clks));
 
 	if (exynos4_soc == EXYNOS4210) {
-		samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+		samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
 			ARRAY_SIZE(exynos4210_fixed_rate_clks));
-		samsung_clk_register_mux(exynos4210_mux_clks,
+		samsung_clk_register_mux(ctx, exynos4210_mux_clks,
 			ARRAY_SIZE(exynos4210_mux_clks));
-		samsung_clk_register_div(exynos4210_div_clks,
+		samsung_clk_register_div(ctx, exynos4210_div_clks,
 			ARRAY_SIZE(exynos4210_div_clks));
-		samsung_clk_register_gate(exynos4210_gate_clks,
+		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
 			ARRAY_SIZE(exynos4210_gate_clks));
-		samsung_clk_register_alias(exynos4210_aliases,
+		samsung_clk_register_alias(ctx, exynos4210_aliases,
 			ARRAY_SIZE(exynos4210_aliases));
 	} else {
-		samsung_clk_register_mux(exynos4x12_mux_clks,
+		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
 			ARRAY_SIZE(exynos4x12_mux_clks));
-		samsung_clk_register_div(exynos4x12_div_clks,
+		samsung_clk_register_div(ctx, exynos4x12_div_clks,
 			ARRAY_SIZE(exynos4x12_div_clks));
-		samsung_clk_register_gate(exynos4x12_gate_clks,
+		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
 			ARRAY_SIZE(exynos4x12_gate_clks));
-		samsung_clk_register_alias(exynos4x12_aliases,
+		samsung_clk_register_alias(ctx, exynos4x12_aliases,
 			ARRAY_SIZE(exynos4x12_aliases));
 	}
 
-	samsung_clk_register_alias(exynos4_aliases,
+	samsung_clk_register_alias(ctx, exynos4_aliases,
 			ARRAY_SIZE(exynos4_aliases));
 
 	exynos4_clk_sleep_init();
drivers/clk/samsung/clk-exynos5250.c +15 -10
index e7ee442..e549e86 100644
@@ -686,6 +686,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
 /* register exynox5250 clocks */
 static void __init exynos5250_clk_init(struct device_node *np)
 {
+	struct samsung_clk_provider *ctx;
+
 	if (np) {
 		reg_base = of_iomap(np, 0);
 		if (!reg_base)

@@ -694,11 +696,13 @@ static void __init exynos5250_clk_init(struct device_node *np)
 		panic("%s: unable to determine soc\n", __func__);
 	}
 
-	samsung_clk_init(np, reg_base, CLK_NR_CLKS);
-	samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
+	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
+	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
 			ext_clk_match);
-	samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
 				ARRAY_SIZE(exynos5250_pll_pmux_clks));
 
 	if (_get_rate("fin_pll") == 24 * MHZ) {

@@ -709,17 +713,18 @@ static void __init exynos5250_clk_init(struct device_node *np)
 	if (_get_rate("mout_vpllsrc") == 24 * MHZ)
 		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;
 
-	samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
-					reg_base);
-	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
+	samsung_clk_register_pll(ctx, exynos5250_plls,
+			ARRAY_SIZE(exynos5250_plls),
+			reg_base);
+	samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
 			ARRAY_SIZE(exynos5250_fixed_rate_clks));
-	samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
+	samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
 			ARRAY_SIZE(exynos5250_fixed_factor_clks));
-	samsung_clk_register_mux(exynos5250_mux_clks,
+	samsung_clk_register_mux(ctx, exynos5250_mux_clks,
 			ARRAY_SIZE(exynos5250_mux_clks));
-	samsung_clk_register_div(exynos5250_div_clks,
+	samsung_clk_register_div(ctx, exynos5250_div_clks,
 			ARRAY_SIZE(exynos5250_div_clks));
-	samsung_clk_register_gate(exynos5250_gate_clks,
+	samsung_clk_register_gate(ctx, exynos5250_gate_clks,
 			ARRAY_SIZE(exynos5250_gate_clks));
 
 	exynos5250_clk_sleep_init();
drivers/clk/samsung/clk-exynos5420.c +15 -9
index 60b2681..c3e0894 100644
@@ -778,6 +778,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
 /* register exynos5420 clocks */
 static void __init exynos5420_clk_init(struct device_node *np)
 {
+	struct samsung_clk_provider *ctx;
+
 	if (np) {
 		reg_base = of_iomap(np, 0);
 		if (!reg_base)

@@ -786,21 +788,25 @@ static void __init exynos5420_clk_init(struct device_node *np)
 		panic("%s: unable to determine soc\n", __func__);
 	}
 
-	samsung_clk_init(np, reg_base, CLK_NR_CLKS);
-	samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
+	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
+
+	samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks,
 			ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
 			ext_clk_match);
-	samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
-					reg_base);
-	samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
+	samsung_clk_register_pll(ctx, exynos5420_plls,
+			ARRAY_SIZE(exynos5420_plls),
+			reg_base);
+	samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks,
 			ARRAY_SIZE(exynos5420_fixed_rate_clks));
-	samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
+	samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks,
 			ARRAY_SIZE(exynos5420_fixed_factor_clks));
-	samsung_clk_register_mux(exynos5420_mux_clks,
+	samsung_clk_register_mux(ctx, exynos5420_mux_clks,
 			ARRAY_SIZE(exynos5420_mux_clks));
-	samsung_clk_register_div(exynos5420_div_clks,
+	samsung_clk_register_div(ctx, exynos5420_div_clks,
 			ARRAY_SIZE(exynos5420_div_clks));
-	samsung_clk_register_gate(exynos5420_gate_clks,
+	samsung_clk_register_gate(ctx, exynos5420_gate_clks,
 			ARRAY_SIZE(exynos5420_gate_clks));
 
 	exynos5420_clk_sleep_init();
drivers/clk/samsung/clk-exynos5440.c +11 -7
index 2bfad5a..aeb76d1 100644
@@ -93,6 +93,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
 static void __init exynos5440_clk_init(struct device_node *np)
 {
 	void __iomem *reg_base;
+	struct samsung_clk_provider *ctx;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {

@@ -101,22 +102,25 @@ static void __init exynos5440_clk_init(struct device_node *np)
 		return;
 	}
 
-	samsung_clk_init(np, reg_base, CLK_NR_CLKS);
-	samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
+	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+	if (!ctx)
+		panic("%s: unable to allocate context.\n", __func__);
+
+	samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
 		ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
 
 	samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
 	samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
 
-	samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
+	samsung_clk_register_fixed_rate(ctx, eexynos5440_fixed_rate_clks,
 			ARRAY_SIZE(exynos5440_fixed_rate_clks));
-	samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
+	samsung_clk_register_fixed_factor(ctx, eexynos5440_fixed_factor_clks,
 			ARRAY_SIZE(exynos5440_fixed_factor_clks));
-	samsung_clk_register_mux(exynos5440_mux_clks,
+	samsung_clk_register_mux(ctx, eexynos5440_mux_clks,
 			ARRAY_SIZE(exynos5440_mux_clks));
-	samsung_clk_register_div(exynos5440_div_clks,
+	samsung_clk_register_div(ctx, eexynos5440_div_clks,
 			ARRAY_SIZE(exynos5440_div_clks));
-	samsung_clk_register_gate(exynos5440_gate_clks,
+	samsung_clk_register_gate(ctx, exynos5440_gate_clks,
 			ARRAY_SIZE(exynos5440_gate_clks));
 
 	pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
drivers/clk/samsung/clk-pll.c +8 -6
index 7fb0a28..1f310be 100644
@@ -947,8 +947,9 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
 	return clk;
 }
 
-static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
-						void __iomem *base)
+static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+				struct samsung_pll_clock *pll_clk,
+				void __iomem *base)
 {
 	struct samsung_clk_pll *pll;
 	struct clk *clk;

@@ -1066,7 +1067,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
 		return;
 	}
 
-	samsung_clk_add_lookup(clk, pll_clk->id);
+	samsung_clk_add_lookup(ctx, clk, pll_clk->id);
 
 	if (!pll_clk->alias)
 		return;

@@ -1077,11 +1078,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
 			__func__, pll_clk->name, ret);
 }
 
-void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
-				unsigned int nr_pll, void __iomem *base)
+void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
+			struct samsung_pll_clock *pll_list,
+			unsigned int nr_pll, void __iomem *base)
 {
 	int cnt;
 
 	for (cnt = 0; cnt < nr_pll; cnt++)
-		_samsung_clk_register_pll(&pll_list[cnt], base);
+		_samsung_clk_register_pll(ctx, &pll_list[cnt], base);
 }
drivers/clk/samsung/clk-s3c64xx.c +25 -19

91 lines not on this page · raw message

drivers/clk/samsung/clk.c +63 -52

246 lines not on this page · raw message

drivers/clk/samsung/clk.h +48 -24

94 lines not on this page · raw message

Signature · 1 line
1.7.9.5
#2 lore raw

PATCH v4 1/5 clk/samsung: add support for multiple clock providers

Hi Rahul,

Quoted 12 lines · Rahul Sharma

Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer.

This layer is modified accordingly to enable the support.

Clock file for exynos4, exynos5250, exynos5420, exynos5440 and S3c64xx are also modified as per changed helper functions.

Signed-off-by Rahul Sharma <[email protected]>
Quoted 10 lines
---
  drivers/clk/samsung/clk-exynos4.c    |   47 +++++++-------
  drivers/clk/samsung/clk-exynos5250.c |   25 +++++---
  drivers/clk/samsung/clk-exynos5420.c |   24 ++++---
  drivers/clk/samsung/clk-exynos5440.c |   18 +++---
  drivers/clk/samsung/clk-pll.c        |   14 +++--
  drivers/clk/samsung/clk-s3c64xx.c    |   44 +++++++------
  drivers/clk/samsung/clk.c            |  115 +++++++++++++++++++---------------
  drivers/clk/samsung/clk.h            |   72 ++++++++++++++-------
  8 files changed, 210 insertions(+), 149 deletions(-)

This patch looks good. However in the meantime two series adding s3c2412 and s3c2416 clock drivers have been merged through Kgene's tree and this patch should be rebased on top of this. I have pulled those drivers to my tree as well, to samsung-next branch.

Best regards,
Tomasz

#3 lore raw

PATCH v4 1/5 clk/samsung: add support for multiple clock providers

Quoted 30 lines · Tomasz Figa

Hi Rahul,

Quoted 13 lines · Rahul Sharma

Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer.

This layer is modified accordingly to enable the support.

Clock file for exynos4, exynos5250, exynos5420, exynos5440 and S3c64xx are also modified as per changed helper functions.

Signed-off-by Rahul Sharma <[email protected]>
Quoted 11 lines
---
  drivers/clk/samsung/clk-exynos4.c    |   47 +++++++-------
  drivers/clk/samsung/clk-exynos5250.c |   25 +++++---
  drivers/clk/samsung/clk-exynos5420.c |   24 ++++---
  drivers/clk/samsung/clk-exynos5440.c |   18 +++---
  drivers/clk/samsung/clk-pll.c        |   14 +++--
  drivers/clk/samsung/clk-s3c64xx.c    |   44 +++++++------
  drivers/clk/samsung/clk.c            |  115
+++++++++++++++++++---------------
  drivers/clk/samsung/clk.h            |   72 ++++++++++++++-------
  8 files changed, 210 insertions(+), 149 deletions(-)
Quoted 5 lines

This patch looks good. However in the meantime two series adding s3c2412 and s3c2416 clock drivers have been merged through Kgene's tree and this patch should be rebased on top of this. I have pulled those drivers to my tree as well, to samsung-next branch.

Sure. I will add similar changes for these 2 SoCs and repost v5.

Regards,
Rahul Sharma

Quoted 2 lines

Best regards,
Tomasz

author
#4 lore raw

PATCH v4 2/5 clk/samsung: add support for pll2550xx

In reply to Rahul Sharma

From: Pankaj Dubey <[email protected]>

exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here.

Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Arun Kumar K <[email protected]>
---
 drivers/clk/samsung/clk-pll.c |  107 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-pll.h |    1 +
 2 files changed, 108 insertions(+)
drivers/clk/samsung/clk-pll.c +107 -0
index 1f310be..3eb2788 100644
@@ -947,6 +947,108 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
 	return clk;
 }
 
+/*
+ * PLL2550xx Clock Type
+ */
+
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL2550XX_LOCK_FACTOR 270
+
+#define PLL2550XX_M_MASK		0x3FF
+#define PLL2550XX_P_MASK		0x3F
+#define PLL2550XX_S_MASK		0x7
+#define PLL2550XX_LOCK_STAT_MASK	0x1
+#define PLL2550XX_M_SHIFT		9
+#define PLL2550XX_P_SHIFT		3
+#define PLL2550XX_S_SHIFT		0
+#define PLL2550XX_LOCK_STAT_SHIFT	21
+
+static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 mdiv, pdiv, sdiv, pll_con;
+	u64 fvco = parent_rate;
+
+	pll_con = __raw_readl(pll->con_reg);
+	mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+	pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+	sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
+
+	fvco *= mdiv;
+	do_div(fvco, (pdiv << sdiv));
+
+	return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+	u32 old_mdiv, old_pdiv;
+
+	old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
+	old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
+
+	return mdiv != old_mdiv || pdiv != old_pdiv;
+}
+
+static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long prate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	const struct samsung_pll_rate_table *rate;
+	u32 tmp;
+
+	/* Get required rate settings from table */
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	tmp = __raw_readl(pll->con_reg);
+
+	if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+		/* If only s change, change just s value only*/
+		tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
+		tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
+		__raw_writel(tmp, pll->con_reg);
+
+		return 0;
+	}
+
+	/* Set PLL lock time. */
+	__raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
+
+	/* Change PLL PMS values */
+	tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
+			(PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
+			(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
+	tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
+			(rate->pdiv << PLL2550XX_P_SHIFT) |
+			(rate->sdiv << PLL2550XX_S_SHIFT);
+	__raw_writel(tmp, pll->con_reg);
+
+	/* wait_lock_time */
+	do {
+		cpu_relax();
+		tmp = __raw_readl(pll->con_reg);
+	} while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
+			<< PLL2550XX_LOCK_STAT_SHIFT)));
+
+	return 0;
+}
+
+static const struct clk_ops samsung_pll2550xx_clk_ops = {
+	.recalc_rate = samsung_pll2550xx_recalc_rate,
+	.round_rate = samsung_pll_round_rate,
+	.set_rate = samsung_pll2550xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
+	.recalc_rate = samsung_pll2550xx_recalc_rate,
+};
+
 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 				struct samsung_pll_clock *pll_clk,
 				void __iomem *base)

@@ -1048,6 +1150,11 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 			init.ops = &samsung_s3c2440_mpll_clk_min_ops;
 		else
 			init.ops = &samsung_s3c2440_mpll_clk_ops;
+	case pll_2550xx:
+		if (!pll->rate_table)
+			init.ops = &samsung_pll2550xx_clk_min_ops;
+		else
+			init.ops = &samsung_pll2550xx_clk_ops;
 		break;
 	default:
 		pr_warn("%s: Unknown pll type for pll clk %s\n",
drivers/clk/samsung/clk-pll.h +1 -0
index 6428bcc..ec4bc1d 100644
@@ -31,6 +31,7 @@ enum samsung_pll_type {
 	pll_s3c2410_mpll,
 	pll_s3c2410_upll,
 	pll_s3c2440_mpll,
+	pll_2550xx,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
Signature · 1 line
1.7.9.5
#5 lore raw

PATCH v4 2/5 clk/samsung: add support for pll2550xx

Quoted 6 lines · Rahul Sharma

From: Pankaj Dubey <[email protected]>

exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here.

Quoted 7 lines
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Arun Kumar K <[email protected]>
---
  drivers/clk/samsung/clk-pll.c |  107 +++++++++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-pll.h |    1 +
  2 files changed, 108 insertions(+)
Acked-by Tomasz Figa <[email protected]>

Best regards,
Tomasz

author
#6 lore raw

PATCH v4 3/5 clk/samsung: add support for pll2650xx

In reply to Rahul Sharma

Add support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1.

Aud_pll in Exynos5260 is pll2650xx and uses this code.

Signed-off-by Rahul Sharma <[email protected]>
---
 drivers/clk/samsung/clk-pll.c |  101 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-pll.h |    1 +
 2 files changed, 102 insertions(+)
drivers/clk/samsung/clk-pll.c +101 -0
index 3eb2788..e251605 100644
@@ -1049,6 +1049,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
 	.recalc_rate = samsung_pll2550xx_recalc_rate,
 };
 
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR 3000
+
+#define PLL2650XX_MDIV_SHIFT		9
+#define PLL2650XX_PDIV_SHIFT		3
+#define PLL2650XX_SDIV_SHIFT		0
+#define PLL2650XX_KDIV_SHIFT		0
+#define PLL2650XX_MDIV_MASK		0x1ff
+#define PLL2650XX_PDIV_MASK		0x3f
+#define PLL2650XX_SDIV_MASK		0x7
+#define PLL2650XX_KDIV_MASK		0xffff
+#define PLL2650XX_PLL_ENABLE_SHIFT	23
+#define PLL2650XX_PLL_LOCKTIME_SHIFT	21
+#define PLL2650XX_PLL_FOUTMASK_SHIFT	31
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+	s16 kdiv;
+	u64 fvco = parent_rate;
+
+	pll_con0 = __raw_readl(pll->con_reg);
+	pll_con2 = __raw_readl(pll->con_reg + 8);
+	mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+	kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+	fvco *= (mdiv << 16) + kdiv;
+	do_div(fvco, (pdiv << sdiv));
+	fvco >>= 16;
+
+	return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 tmp, pll_con0, pll_con2;
+	const struct samsung_pll_rate_table *rate;
+
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	pll_con0 = __raw_readl(pll->con_reg);
+	pll_con2 = __raw_readl(pll->con_reg + 8);
+
+	 /* Change PLL PMS values */
+	pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+			PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+			PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+	pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+	pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+	pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+	pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+	pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+	pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+	pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+			<< PLL2650XX_KDIV_SHIFT;
+
+	/* Set PLL lock time. */
+	__raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+	__raw_writel(pll_con0, pll->con_reg);
+	__raw_writel(pll_con2, pll->con_reg + 8);
+
+	do {
+		tmp = __raw_readl(pll->con_reg);
+	} while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+	return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+	.recalc_rate = samsung_pll2650xx_recalc_rate,
+	.set_rate = samsung_pll2650xx_set_rate,
+	.round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+	.recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 				struct samsung_pll_clock *pll_clk,
 				void __iomem *base)

@@ -1156,6 +1251,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 		else
 			init.ops = &samsung_pll2550xx_clk_ops;
 		break;
+	case pll_2650xx:
+		if (!pll->rate_table)
+			init.ops = &samsung_pll2650xx_clk_min_ops;
+		else
+			init.ops = &samsung_pll2650xx_clk_ops;
+		break;
 	default:
 		pr_warn("%s: Unknown pll type for pll clk %s\n",
 			__func__, pll_clk->name);
drivers/clk/samsung/clk-pll.h +1 -0
index ec4bc1d..c0ed4d4 100644
@@ -32,6 +32,7 @@ enum samsung_pll_type {
 	pll_s3c2410_upll,
 	pll_s3c2440_mpll,
 	pll_2550xx,
+	pll_2650xx,
 };
 
 #define PLL_35XX_RATE(_rate, _m, _p, _s)			\
Signature · 1 line
1.7.9.5
#7 lore raw

PATCH v4 3/5 clk/samsung: add support for pll2650xx

Quoted 10 lines · Rahul Sharma

Add support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1.

Aud_pll in Exynos5260 is pll2650xx and uses this code.

Signed-off-by Rahul Sharma <[email protected]>
---
  drivers/clk/samsung/clk-pll.c |  101 +++++++++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-pll.h |    1 +
  2 files changed, 102 insertions(+)
Acked-by Tomasz Figa <[email protected]>

Best regards,
Tomasz

author
#8 lore raw

PATCH v4 4/5 clk/exynos5260: add macros and documentation for exynos5260

In reply to Rahul Sharma

Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.

Signed-off-by Rahul Sharma <[email protected]>
---
 .../devicetree/bindings/clock/exynos5260-clock.txt |   55 +++++
 include/dt-bindings/clk/exynos5260-clk.h           |  233 ++++++++++++++++++++
 2 files changed, 288 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
 create mode 100644 include/dt-bindings/clk/exynos5260-clk.h
Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +55 -0
new file mode 100644
index 0000000..4128892
@@ -0,0 +1,55 @@
+* Samsung Exynos5260 Clock Controller
+
+The Exynos5260 clock controller encapsulate all CMUs which are
+instantiaited independently from the device-tree. As a whole, these
+CMUs generates and supplies clocks to various controllers within
+the Exynos5260 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+	"exynos5260-clock-top"
+	"exynos5260-clock-peri"
+	"exynos5260-clock-egl"
+	"exynos5260-clock-kfc"
+	"exynos5260-clock-g2d"
+	"exynos5260-clock-mif"
+	"exynos5260-clock-mfc"
+	"exynos5260-clock-g3d"
+	"exynos5260-clock-fsys"
+	"exynos5260-clock-aud"
+	"exynos5260-clock-isp"
+	"exynos5260-clock-gscl"
+	"exynos5260-clock-disp"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the each controller. Each
+clock is assigned a MACRO constant. These constants are defined in
+"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to
+specify the clock which they consume.
+
+Example 1: An example of a clock controller node is listed below.
+
+	cmu_disp: clock-controller at 0x14550000 {
+		compatible = "exynos5260-clock-disp";
+		reg = <0x14550000 0x10000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the
+		peri clock controller. Refer to the standard clock bindings for
+		information about 'clocks' and 'clock-names' property.
+
+	serial at 12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 146 0>;
+		clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
include/dt-bindings/clk/exynos5260-clk.h new file +233 -0

233 lines not on this page · raw message

Signature · 1 line
1.7.9.5
#9 lore raw

PATCH v4 4/5 clk/exynos5260: add macros and documentation for exynos5260

Hi Rahul,

Please see some minor comments below.

Quoted 10 lines · Rahul Sharma

Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.

Signed-off-by Rahul Sharma <[email protected]>
---
  .../devicetree/bindings/clock/exynos5260-clock.txt |   55 +++++
  include/dt-bindings/clk/exynos5260-clk.h           |  233 ++++++++++++++++++++
  2 files changed, 288 insertions(+)

create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 include/dt-bindings/clk/exynos5260-clk.h

[snip]

include/dt-bindings/clk/exynos5260-clk.h

Quoted 5 lines
include/dt-bindings/clk/exynos5260-clk.h new file +0 -0
new file mode 100644
index 0000000..4dc20a8

Please use dt-bindings/clock directory.

include/dt-bindings/clk/exynos5260-clk.h line 9

Quoted 10 lines
include/dt-bindings/clk/exynos5260-clk.h new file +9 -0
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/

nit: Misaligned star.

include/dt-bindings/clk/exynos5260-clk.h line 17

Quoted 8 lines
include/dt-bindings/clk/exynos5260-clk.h new file +8 -0
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/*
+ * Clock names: XXXXXX_YYYYY_ZZZZZ
+ *                    |------| |----| |----|
+ *                       cmu       type      IP

The alignment looks wrong. Also tabs should be used.

include/dt-bindings/clk/exynos5260-clk.h line 18

Quoted 1 line
include/dt-bindings/clk/exynos5260-clk.h new file +1 -0
+*/

nit: Misaligned star.

include/dt-bindings/clk/exynos5260-clk.h line 20

Quoted 2 lines
include/dt-bindings/clk/exynos5260-clk.h new file +2 -0
+
+/* list of clocks for CMU_TOP */

nit: Please properly capitalize comments and end them with a dot, e.g.

/* List of clocks for CMU_TOP. */

include/dt-bindings/clk/exynos5260-clk.h line 21

Quoted 1 line
include/dt-bindings/clk/exynos5260-clk.h new file +1 -0
+#define	FIN_PLL			1

nit: No tabs between #define and DEF_NAME, please.

Best regards,
Tomasz

#10 lore raw

PATCH v4 4/5 clk/exynos5260: add macros and documentation for exynos5260

Quoted 74 lines · Tomasz Figa

Hi Rahul,

Please see some minor comments below.

Quoted 13 lines · Rahul Sharma

Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.

Signed-off-by Rahul Sharma <[email protected]>
---
  .../devicetree/bindings/clock/exynos5260-clock.txt |   55 +++++
  include/dt-bindings/clk/exynos5260-clk.h           |  233
++++++++++++++++++++
  2 files changed, 288 insertions(+)

create mode 100644
Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 include/dt-bindings/clk/exynos5260-clk.h

[snip]

include/dt-bindings/clk/exynos5260-clk.h

Quoted 6 lines
include/dt-bindings/clk/exynos5260-clk.h new file +0 -0
new file mode 100644
index 0000000..4dc20a8

Please use dt-bindings/clock directory.

include/dt-bindings/clk/exynos5260-clk.h line 9

Quoted 10 lines
include/dt-bindings/clk/exynos5260-clk.h new file +9 -0
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/

nit: Misaligned star.

include/dt-bindings/clk/exynos5260-clk.h line 17

Quoted 8 lines
include/dt-bindings/clk/exynos5260-clk.h new file +8 -0
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/*
+ * Clock names: XXXXXX_YYYYY_ZZZZZ
+ *                    |------| |----| |----|
+ *                       cmu       type      IP

The alignment looks wrong. Also tabs should be used.

include/dt-bindings/clk/exynos5260-clk.h line 18

Quoted 1 line
include/dt-bindings/clk/exynos5260-clk.h new file +1 -0
+*/

nit: Misaligned star.

include/dt-bindings/clk/exynos5260-clk.h line 20

Quoted 2 lines
include/dt-bindings/clk/exynos5260-clk.h new file +2 -0
+
+/* list of clocks for CMU_TOP */

nit: Please properly capitalize comments and end them with a dot, e.g.

Quoted 7 lines

/* List of clocks for CMU_TOP. */

include/dt-bindings/clk/exynos5260-clk.h line 21

Quoted 1 line
include/dt-bindings/clk/exynos5260-clk.h new file +1 -0
+#define        FIN_PLL                 1

nit: No tabs between #define and DEF_NAME, please.

I will fix them in v5.

Regards,
Rahul Sharma.

Quoted 2 lines

Best regards,
Tomasz

author
#11 lore raw

PATCH v4 5/5 clk/exynos5260: add clock file for exynos5260

In reply to Rahul Sharma

Add support for exynos5260 clocks in clock driver.

Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Pankaj Dubey <[email protected]>
---
 drivers/clk/samsung/Makefile         |    1 +
 drivers/clk/samsung/clk-exynos5260.c | 1933 ++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-exynos5260.h |  448 ++++++++
 3 files changed, 2382 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-exynos5260.c
 create mode 100644 drivers/clk/samsung/clk-exynos5260.h
drivers/clk/samsung/Makefile +1 -0
index 77313e2..56e7d38 100644
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
drivers/clk/samsung/clk-exynos5260.c new file +1933 -0

1,933 lines not on this page · raw message

drivers/clk/samsung/clk-exynos5260.h new file +448 -0

448 lines not on this page · raw message

Signature · 1 line
1.7.9.5