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ARM: dts: Better support for Gumstix Overo (for 3.15?)

PATCH New Florian Vaussard 3 participants 18 messages Mar 7, 2014 – Mar 13, 2014 Device tree bindings

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Florian Vaussard

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#0 lore raw

v4 cover ARM: dts: Better support for Gumstix Overo (for 3.15?)

Hello Tony, Benoit,

This is the fourth version of my Overo series. Compared to v3, I reorganized a bit the include files (omap3-overo.dtsi -> omap3-overo-base.dtsi and created SoC-specific omap3-overo.dtsi and omap3-overo-storm.dtsi). This was necessary to correctly define the pinmux for the processor board's pins belonging to the omap3_pmx_core2 pinctrl. For details, see the discussion on the v3 [1].

Most patches are pretty obvious. Patch 6 adds some specific timings for LAN9221 into a generic file. By using shorter timing, it is possible to double the Ethernet bandwidth. Thus is may interest people using a similar chip.

I tested this series with both the OMAP35xx Overo and the OMAP36xx Overo. Wifi and Bluetooth are functional, HSUSB works.

Note: I hope that this can go into 3.15, since the patches were first posted before the 3.14 merge window. They add a number of useful peripherals, so this would be much appreciated.

Regards,
Florian

[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/111143

Florian Vaussard (9):
ARM: dts: overo: reorganize include files
ARM: dts: omap3-tobi: Add missing pinctrl
ARM: dts: omap3-overo: Add missing pinctrl
ARM: dts: omap3-overo: Enable WiFi/BT combo
ARM: dts: omap3-overo: Add HSUSB PHY
ARM: dts: omap: Add common file for SMSC9221
ARM: dts: omap3-tobi: Use include file omap-gpmc-smsc9221
ARM: dts: omap3-tobi: Add AT24C01 EEPROM
ARM: dts: overo: Push uart3 pinmux down to expansion board

 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi      |  58 +++++++
 arch/arm/boot/dts/omap3-overo-base.dtsi        | 221 +++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm-tobi.dts   |   2 +-
 arch/arm/boot/dts/omap3-overo-storm.dtsi       |  35 ++++
 arch/arm/boot/dts/omap3-overo-tobi-common.dtsi |  67 ++++----
 arch/arm/boot/dts/omap3-overo-tobi.dts         |   2 +-
 arch/arm/boot/dts/omap3-overo.dtsi             |  97 +++--------
 7 files changed, 365 insertions(+), 117 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-overo-base.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-overo-storm.dtsi
Signature · 1 line
1.8.3.2
author
#1 lore raw

PATCH v4 1/9 ARM: dts: overo: reorganize include files

Currently, overo-related include files are organized as follow:

                     omap3-overo.dtsi
                             |
                             |
omap34xx.dtsi   omap3-overo-tobi-common.dtsi   omap36xx.dtsi
      |              |                 |             |
      ---------------                  ---------------
              |                                |
    omap3-overo-tobi.dts          omap3-overo-storm-tobi.dts

This is unpractical when one has to deal with SoC-specific pinmux belonging to the omap3_pmx_core2 (defined in omap34xx/omap36xx), for pins related to the processor board. With the current hierarchy, such pinmux has to be defined in the expansion board's .dts, which is not logical.

This patches reorganizes the files to add (yet another) abstraction layer between the processor and the expansion boards.

omap34xx.dtsi omap3-overo-base.dtsi omap36xx.dtsi

      |              |                 |             |
      ---------------                  ---------------
              |                                |
      omap3-overo.dtsi               omap3-overo-storm.dtsi
              |                                |
      --------                                  ------
      |         omap3-overo-tobi-common.dtsi         |
      |              |                 |             |
      ---------------                  ---------------
              |                                |
    omap3-overo-tobi.dts          omap3-overo-storm-tobi.dts
Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi        | 94 ++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm-tobi.dts   |  2 +-
 arch/arm/boot/dts/omap3-overo-storm.dtsi       | 11 +++
 arch/arm/boot/dts/omap3-overo-tobi-common.dtsi |  2 -
 arch/arm/boot/dts/omap3-overo-tobi.dts         |  2 +-
 arch/arm/boot/dts/omap3-overo.dtsi             | 89 +-----------------------
 6 files changed, 110 insertions(+), 90 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap3-overo-base.dtsi
 create mode 100644 arch/arm/boot/dts/omap3-overo-storm.dtsi
arch/arm/boot/dts/omap3-overo-base.dtsi new file +94 -0
new file mode 100644
index 0000000..5970999
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The Gumstix Overo must be combined with an expansion board.
+ */
+
+/ {
+	pwmleds {
+		compatible = "pwm-leds";
+
+		overo {
+			label = "overo:blue:COM";
+			pwms = <&twl_pwmled 1 7812500>;
+			max-brightness = <127>;
+			linux,default-trigger = "mmc0";
+		};
+	};
+
+	sound {
+		compatible = "ti,omap-twl4030";
+		ti,model = "overo";
+
+		ti,mcbsp = <&mcbsp2>;
+		ti,codec = <&twl_audio>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl at 48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+
+		twl_audio: audio {
+			compatible = "ti,twl4030-audio";
+			codec {
+			};
+		};
+	};
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+/* i2c2 pins are used for gpio */
+&i2c2 {
+	status = "disabled";
+};
+
+/* on board microSD slot */
+&mmc1 {
+	vmmc-supply = <&vmmc1>;
+	bus-width = <4>;
+};
+
+/* optional on board WiFi */
+&mmc2 {
+	bus-width = <4>;
+};
+
+&twl_gpio {
+	ti,use-leds;
+};
+
+&usb_otg_hs {
+	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
+	phys = <&usb2_phy>;
+	phy-names = "usb2-phy";
+	mode = <3>;
+	power = <50>;
+};
+
+&omap3_pmx_core {
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+			0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+		>;
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
arch/arm/boot/dts/omap3-overo-storm-tobi.dts +1 -1
index 966b5c9..879383a 100644
@@ -12,7 +12,7 @@
 
 /dts-v1/;
 
-#include "omap36xx.dtsi"
+#include "omap3-overo-storm.dtsi"
 #include "omap3-overo-tobi-common.dtsi"
 
 / {
arch/arm/boot/dts/omap3-overo-storm.dtsi new file +11 -0
new file mode 100644
index 0000000..c30efb3
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap36xx.dtsi"
+#include "omap3-overo-base.dtsi"
+
arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +0 -2
index 4edc013..9b4a6d2 100644
@@ -10,8 +10,6 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-#include "omap3-overo.dtsi"
-
 / {
 	leds {
 		compatible = "gpio-leds";
arch/arm/boot/dts/omap3-overo-tobi.dts +1 -1
index de5653e..fd6400e 100644
@@ -12,7 +12,7 @@
 
 /dts-v1/;
 
-#include "omap34xx.dtsi"
+#include "omap3-overo.dtsi"
 #include "omap3-overo-tobi-common.dtsi"
 
 / {
arch/arm/boot/dts/omap3-overo.dtsi +3 -86

97 lines not on this page · raw message

Signature · 1 line
1.8.3.2
author
#2 lore raw

PATCH v4 2/9 ARM: dts: omap3-tobi: Add missing pinctrl

In reply to Florian Vaussard

Add missing pinctrl entries:
- i2c3

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-tobi-common.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)
arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +11 -0
index 9b4a6d2..7375cda 100644
@@ -33,6 +33,15 @@
 	};
 };
 
+&omap3_pmx_core {
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl.i2c3_scl */
+			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda.i2c3_sda */
+		>;
+	};
+};
+
 &gpmc {
 	ranges = <5 0 0x2c000000 0x1000000>;	/* CS5 */
 

@@ -70,6 +79,8 @@
 };
 
 &i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
 	clock-frequency = <100000>;
 };
Signature · 1 line
1.8.3.2
author
#3 lore raw

PATCH v4 3/9 ARM: dts: omap3-overo: Add missing pinctrl

In reply to Florian Vaussard

Add missing pinctrl entries for:
- i2c1
- mmc1

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi | 40 +++++++++++++++++++++++++--------
 1 file changed, 31 insertions(+), 9 deletions(-)
arch/arm/boot/dts/omap3-overo-base.dtsi +31 -9
index 5970999..aea64c0 100644
@@ -31,7 +31,36 @@
 	};
 };
 
+&omap3_pmx_core {
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0)	/* uart3_rx_irrx.uart3_rx_irrx */
+			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)		/* i2c1_scl.i2c1_scl */
+			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)		/* i2c1_sda.i2c1_sda */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_clk.sdmmc1_clk */
+			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_cmd.sdmmc1_cmd */
+			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat0.sdmmc1_dat0 */
+			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat1.sdmmc1_dat1 */
+			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat2.sdmmc1_dat2 */
+			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat3.sdmmc1_dat3 */
+		>;
+	};
+};
+
 &i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
 	clock-frequency = <2600000>;
 
 	twl: twl at 48 {

@@ -57,6 +86,8 @@
 
 /* on board microSD slot */
 &mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
 	vmmc-supply = <&vmmc1>;
 	bus-width = <4>;
 };

@@ -79,15 +110,6 @@
 	power = <50>;
 };
 
-&omap3_pmx_core {
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
-			0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
-		>;
-	};
-};
-
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_pins>;
Signature · 1 line
1.8.3.2
author
#4 lore raw

PATCH v4 4/9 ARM: dts: omap3-overo: Enable WiFi/BT combo

In reply to Florian Vaussard

MMC2 is used by the on-board WiFi module populated on some boards (based on Marvell Libertas 8688 SDIO). The Bluetooth is connected to UART2.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi  | 72 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm.dtsi |  8 ++++
 arch/arm/boot/dts/omap3-overo.dtsi       |  8 ++++
 3 files changed, 88 insertions(+)
arch/arm/boot/dts/omap3-overo-base.dtsi +72 -0
index aea64c0..edac70e 100644
@@ -29,9 +29,50 @@
 		ti,mcbsp = <&mcbsp2>;
 		ti,codec = <&twl_audio>;
 	};
+
+	/* Regulator to trigger the nPoweron signal of the Wifi module */
+	w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-w3cbw003c-npoweron";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>;		/* gpio_54: nPoweron */
+		enable-active-high;
+	};
+
+	/* Regulator to trigger the nReset signal of the Wifi module */
+	w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset {
+		pinctrl-names = "default";
+		pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-w3cbw003c-wifi-nreset";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;		/* gpio_16: WiFi nReset */
+		startup-delay-us = <10000>;
+	};
+
+	/* Regulator to trigger the nReset signal of the Bluetooth module */
+	w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset {
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-w3cbw003c-bt-nreset";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;		/* gpio_164: BT nReset */
+		startup-delay-us = <10000>;
+	};
 };
 
 &omap3_pmx_core {
+	uart2_pins: pinmux_uart2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */
+			OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_dr.uart2_rts */
+			OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_clk.uart2_tx */
+			OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)	/* mcbsp3_fsx.uart2_rx */
+		>;
+	};
+
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0)	/* uart3_rx_irrx.uart3_rx_irrx */

@@ -56,6 +97,25 @@
 			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_dat3.sdmmc1_dat3 */
 		>;
 	};
+
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_clk.sdmmc2_clk */
+			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_cmd.sdmmc2_cmd */
+			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat0.sdmmc2_dat0 */
+			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat1.sdmmc2_dat1 */
+			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat2.sdmmc2_dat2 */
+			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc2_dat3.sdmmc2_dat3 */
+		>;
+	};
+
+	/* WiFi/BT combo */
+	w3cbw003c_pins: pinmux_w3cbw003c_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4)		/* gpmc_ncs3.gpio_54 */
+			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -94,7 +154,14 @@
 
 /* optional on board WiFi */
 &mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&w3cbw003c_npoweron>;
+	vqmmc-supply = <&w3cbw003c_bt_nreset>;
+	vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
 	bus-width = <4>;
+	cap-sdio-irq;
+	non-removable;
 };
 
 &twl_gpio {

@@ -110,6 +177,11 @@
 	power = <50>;
 };
 
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_pins>;
arch/arm/boot/dts/omap3-overo-storm.dtsi +8 -0
index c30efb3..c235ae8 100644
@@ -9,3 +9,11 @@
 #include "omap36xx.dtsi"
 #include "omap3-overo-base.dtsi"
 
+&omap3_pmx_core2 {
+	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
+		>;
+	};
+};
+
arch/arm/boot/dts/omap3-overo.dtsi +8 -0
index 7bbda68..95c59b2 100644
@@ -9,3 +9,11 @@
 #include "omap34xx.dtsi"
 #include "omap3-overo-base.dtsi"
 
+&omap3_pmx_core2 {
+	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
+		pinctrl-single,pins = <
+			OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
+		>;
+	};
+};
+
Signature · 1 line
1.8.3.2
author
#5 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

In reply to Florian Vaussard

Add the High-Speed USB PHY.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi  | 44 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm.dtsi | 16 ++++++++++++
 arch/arm/boot/dts/omap3-overo.dtsi       | 16 ++++++++++++
 3 files changed, 76 insertions(+)
arch/arm/boot/dts/omap3-overo-base.dtsi +44 -0
index edac70e..13d1ad2 100644
@@ -30,6 +30,24 @@
 		ti,codec = <&twl_audio>;
 	};
 
+	/* HS USB Port 2 Power */
+	hsusb2_power: hsusb2_power_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "hsusb2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio6 8 0>;				/* gpio_168: vbus enable */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	/* HS USB Host PHY on PORT 2 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;	/* gpio_183 */
+		vcc-supply = <&hsusb2_power>;
+	};
+
 	/* Regulator to trigger the nPoweron signal of the Wifi module */
 	w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
 		compatible = "regulator-fixed";

@@ -64,6 +82,11 @@
 };
 
 &omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_pins
+	>;
+
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */

@@ -116,6 +139,19 @@
 			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
 		>;
 	};
+
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)		/* i2c2_scl.gpio_168 */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4)		/* i2c2_sda.gpio_183 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -177,6 +213,14 @@
 	power = <50>;
 };
 
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
arch/arm/boot/dts/omap3-overo-storm.dtsi +16 -0
index c235ae8..6cb418b 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+
 	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
 		pinctrl-single,pins = <
 			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
arch/arm/boot/dts/omap3-overo.dtsi +16 -0
index 95c59b2..c37b130 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+
 	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
 		pinctrl-single,pins = <
 			OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
Signature · 1 line
1.8.3.2
#6 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

Hi Florian,

Quoted 96 lines · Florian Vaussard

Add the High-Speed USB PHY.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi  | 44 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm.dtsi | 16 ++++++++++++
 arch/arm/boot/dts/omap3-overo.dtsi       | 16 ++++++++++++
 3 files changed, 76 insertions(+)
arch/arm/boot/dts/omap3-overo-base.dtsi +44 -0
index edac70e..13d1ad2 100644
@@ -30,6 +30,24 @@
 		ti,codec = <&twl_audio>;
 	};
 
+	/* HS USB Port 2 Power */
+	hsusb2_power: hsusb2_power_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "hsusb2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio6 8 0>;				/* gpio_168: vbus enable */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	/* HS USB Host PHY on PORT 2 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;	/* gpio_183 */
+		vcc-supply = <&hsusb2_power>;
+	};
+
 	/* Regulator to trigger the nPoweron signal of the Wifi module */
 	w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
 		compatible = "regulator-fixed";

@@ -64,6 +82,11 @@
 };
 
 &omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_pins
+	>;
+
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */

@@ -116,6 +139,19 @@
 			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
 		>;
 	};
+
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)		/* i2c2_scl.gpio_168 */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4)		/* i2c2_sda.gpio_183 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -177,6 +213,14 @@
 	power = <50>;
 };
 
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
arch/arm/boot/dts/omap3-overo-storm.dtsi +3 -0
index c235ae8..6cb418b 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins

arch/arm/boot/dts/omap3-overo-storm.dtsi line 25

Quoted 10 lines
arch/arm/boot/dts/omap3-overo-storm.dtsi +10 -0
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */

If you don't use the OMAP3x30_CORE2_IOPAD() macro then these definitions can fit in omap3-overo-base.dtsi. The offsets will be taken care of if you place them within &omap3_pmx_core2 {} . e.g.

+                       0x50 (PIN_OUTPUT | MUX_MODE3)           /* etk_d10.hsusb2_clk */
+                       0x52 (PIN_OUTPUT | MUX_MODE3)           /* etk_d11.hsusb2_stp */
+                       0x54 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d12.hsusb2_dir */
+                       0x56 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d13.hsusb2_nxt */
+                       0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d14.hsusb2_data0 */
+                       0x5a (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d15.hsusb2_data1 */

Do you think this is better?

cheers,
-roger

Quoted 34 lines
arch/arm/boot/dts/omap3-overo-storm.dtsi +3 -0
+		>;
+	};
+
 	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
 		pinctrl-single,pins = <
 			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
arch/arm/boot/dts/omap3-overo.dtsi +16 -0
index 95c59b2..c37b130 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+
 	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
 		pinctrl-single,pins = <
 			OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
author
#7 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

Hi Roger,

Quoted 120 lines · Roger Quadros

Hi Florian,

Quoted 96 lines · Florian Vaussard

Add the High-Speed USB PHY.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi  | 44 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm.dtsi | 16 ++++++++++++
 arch/arm/boot/dts/omap3-overo.dtsi       | 16 ++++++++++++
 3 files changed, 76 insertions(+)
arch/arm/boot/dts/omap3-overo-base.dtsi +44 -0
index edac70e..13d1ad2 100644
@@ -30,6 +30,24 @@
 		ti,codec = <&twl_audio>;
 	};
 
+	/* HS USB Port 2 Power */
+	hsusb2_power: hsusb2_power_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "hsusb2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio6 8 0>;				/* gpio_168: vbus enable */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	/* HS USB Host PHY on PORT 2 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;	/* gpio_183 */
+		vcc-supply = <&hsusb2_power>;
+	};
+
 	/* Regulator to trigger the nPoweron signal of the Wifi module */
 	w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
 		compatible = "regulator-fixed";

@@ -64,6 +82,11 @@
 };
 
 &omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_pins
+	>;
+
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */

@@ -116,6 +139,19 @@
 			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
 		>;
 	};
+
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)		/* i2c2_scl.gpio_168 */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4)		/* i2c2_sda.gpio_183 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -177,6 +213,14 @@
 	power = <50>;
 };
 
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
arch/arm/boot/dts/omap3-overo-storm.dtsi +3 -0
index c235ae8..6cb418b 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins

arch/arm/boot/dts/omap3-overo-storm.dtsi line 25

Quoted 10 lines
arch/arm/boot/dts/omap3-overo-storm.dtsi +10 -0
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */

If you don't use the OMAP3x30_CORE2_IOPAD() macro then these definitions can fit in omap3-overo-base.dtsi. The offsets will be taken care of if you place them within &omap3_pmx_core2 {} . e.g.

(quoted diff) +6 -0
+                       0x50 (PIN_OUTPUT | MUX_MODE3)           /* etk_d10.hsusb2_clk */
+                       0x52 (PIN_OUTPUT | MUX_MODE3)           /* etk_d11.hsusb2_stp */
+                       0x54 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d12.hsusb2_dir */
+                       0x56 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d13.hsusb2_nxt */
+                       0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d14.hsusb2_data0 */
+                       0x5a (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d15.hsusb2_data1 */
Quoted 2 lines

Do you think this is better?

I do not think that this could work. Let's take for example hsusb2_clk et let's do the math. Here, 0x50 is the offset inside omap3_pmx_core2 pinctrl, so:

hsusb2_clk omap3_pmx_core2 hsusb2_clk
offset base addr. PADCONF addr.
---- ---------- ----------
OMAP34xx: 0x50 0x480025d8 0x48002628 *NO*
OMAP36xx: 0x50 0x480025a0 0x480025F0 *ok*

Looking at the TRM, the PADCONF address for hsusb2_clk is 0x480025F0 in both cases. Thus we will be wrong on OMAP34xx (offset should be 0x18 instead of 0x50). Thus so far, I do not see any magical solution apart putting the omap3_pmx_core2 pins in a SoC-dependant .dtsi file.

I already expressed my concerns [1] about having a different base address for omap3_pmx_core2 depending on the SoC (although I do understand the rational behind). This makes cross-SoC platforms more difficult to maintain.

Regards,
Florian

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/289874

#8 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

Quoted 30 lines · Florian Vaussard
Quoted 11 lines · Roger Quadros

If you don't use the OMAP3x30_CORE2_IOPAD() macro then these definitions can fit in omap3-overo-base.dtsi. The offsets will be taken care of if you place them within &omap3_pmx_core2 {} . e.g.

(quoted diff) +6 -0
+                       0x50 (PIN_OUTPUT | MUX_MODE3)           /* etk_d10.hsusb2_clk */
+                       0x52 (PIN_OUTPUT | MUX_MODE3)           /* etk_d11.hsusb2_stp */
+                       0x54 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d12.hsusb2_dir */
+                       0x56 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d13.hsusb2_nxt */
+                       0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d14.hsusb2_data0 */
+                       0x5a (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d15.hsusb2_data1 */
Quoted 2 lines

Do you think this is better?

I do not think that this could work. Let's take for example hsusb2_clk et let's do the math. Here, 0x50 is the offset inside omap3_pmx_core2 pinctrl, so:

hsusb2_clk omap3_pmx_core2 hsusb2_clk
offset base addr. PADCONF addr.
---- ---------- ----------
OMAP34xx: 0x50 0x480025d8 0x48002628 *NO*
OMAP36xx: 0x50 0x480025a0 0x480025F0 *ok*

Looking at the TRM, the PADCONF address for hsusb2_clk is 0x480025F0 in both cases. Thus we will be wrong on OMAP34xx (offset should be 0x18 instead of 0x50). Thus so far, I do not see any magical solution apart putting the omap3_pmx_core2 pins in a SoC-dependant .dtsi file.

Quoted 4 lines

I already expressed my concerns [1] about having a different base address for omap3_pmx_core2 depending on the SoC (although I do understand the rational behind). This makes cross-SoC platforms more difficult to maintain.

Yeah the muxing should always be possible to do at board level.

Just the use of external pulls for some boards will make it hard to have anything common. If you want something common, you can have something like omap36xx-usb-xyz.dtsi as long as it's always wired up the same way.

Regards,

Tony

Quoted 2 lines

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/289874

author
#9 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

Quoted 36 lines · Tony Lindgren
Quoted 30 lines · Florian Vaussard
Quoted 11 lines · Roger Quadros

If you don't use the OMAP3x30_CORE2_IOPAD() macro then these definitions can fit in omap3-overo-base.dtsi. The offsets will be taken care of if you place them within &omap3_pmx_core2 {} . e.g.

(quoted diff) +6 -0
+                       0x50 (PIN_OUTPUT | MUX_MODE3)           /* etk_d10.hsusb2_clk */
+                       0x52 (PIN_OUTPUT | MUX_MODE3)           /* etk_d11.hsusb2_stp */
+                       0x54 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d12.hsusb2_dir */
+                       0x56 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d13.hsusb2_nxt */
+                       0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d14.hsusb2_data0 */
+                       0x5a (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d15.hsusb2_data1 */
Quoted 2 lines

Do you think this is better?

I do not think that this could work. Let's take for example hsusb2_clk et let's do the math. Here, 0x50 is the offset inside omap3_pmx_core2 pinctrl, so:

hsusb2_clk omap3_pmx_core2 hsusb2_clk
offset base addr. PADCONF addr.
---- ---------- ----------
OMAP34xx: 0x50 0x480025d8 0x48002628 *NO*
OMAP36xx: 0x50 0x480025a0 0x480025F0 *ok*

Looking at the TRM, the PADCONF address for hsusb2_clk is 0x480025F0 in both cases. Thus we will be wrong on OMAP34xx (offset should be 0x18 instead of 0x50). Thus so far, I do not see any magical solution apart putting the omap3_pmx_core2 pins in a SoC-dependant .dtsi file.

Quoted 4 lines

I already expressed my concerns [1] about having a different base address for omap3_pmx_core2 depending on the SoC (although I do understand the rational behind). This makes cross-SoC platforms more difficult to maintain.

Quoted 7 lines

Yeah the muxing should always be possible to do at board level.

Just the use of external pulls for some boards will make it hard to have anything common. If you want something common, you can have something like omap36xx-usb-xyz.dtsi as long as it's always wired up the same way.

This is why I put the muxing in a file that will be shared by all Overo expansion boards. Looking at the other .dts, only omap3-beagle.dts / omap3-beagle-xm.dts define the pinmux for hsusb2_*, so for now I do not think it is worth the effort to create a pinmux file common to all omap3 .dts.

Regards,
Florian

#10 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

In reply to Florian Vaussard
Quoted 141 lines · Florian Vaussard

Hi Roger,

Quoted 120 lines · Roger Quadros

Hi Florian,

Quoted 96 lines · Florian Vaussard

Add the High-Speed USB PHY.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi  | 44 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm.dtsi | 16 ++++++++++++
 arch/arm/boot/dts/omap3-overo.dtsi       | 16 ++++++++++++
 3 files changed, 76 insertions(+)
arch/arm/boot/dts/omap3-overo-base.dtsi +44 -0
index edac70e..13d1ad2 100644
@@ -30,6 +30,24 @@
 		ti,codec = <&twl_audio>;
 	};
 
+	/* HS USB Port 2 Power */
+	hsusb2_power: hsusb2_power_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "hsusb2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio6 8 0>;				/* gpio_168: vbus enable */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	/* HS USB Host PHY on PORT 2 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;	/* gpio_183 */
+		vcc-supply = <&hsusb2_power>;
+	};
+
 	/* Regulator to trigger the nPoweron signal of the Wifi module */
 	w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
 		compatible = "regulator-fixed";

@@ -64,6 +82,11 @@
 };
 
 &omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_pins
+	>;
+
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */

@@ -116,6 +139,19 @@
 			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
 		>;
 	};
+
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)		/* i2c2_scl.gpio_168 */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4)		/* i2c2_sda.gpio_183 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -177,6 +213,14 @@
 	power = <50>;
 };
 
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
arch/arm/boot/dts/omap3-overo-storm.dtsi +3 -0
index c235ae8..6cb418b 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins

arch/arm/boot/dts/omap3-overo-storm.dtsi line 25

Quoted 10 lines
arch/arm/boot/dts/omap3-overo-storm.dtsi +10 -0
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */

If you don't use the OMAP3x30_CORE2_IOPAD() macro then these definitions can fit in omap3-overo-base.dtsi. The offsets will be taken care of if you place them within &omap3_pmx_core2 {} . e.g.

(quoted diff) +6 -0
+                       0x50 (PIN_OUTPUT | MUX_MODE3)           /* etk_d10.hsusb2_clk */
+                       0x52 (PIN_OUTPUT | MUX_MODE3)           /* etk_d11.hsusb2_stp */
+                       0x54 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d12.hsusb2_dir */
+                       0x56 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d13.hsusb2_nxt */
+                       0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d14.hsusb2_data0 */
+                       0x5a (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* etk_d15.hsusb2_data1 */
Quoted 2 lines

Do you think this is better?

I do not think that this could work. Let's take for example hsusb2_clk et let's do the math. Here, 0x50 is the offset inside omap3_pmx_core2 pinctrl, so:

hsusb2_clk omap3_pmx_core2 hsusb2_clk
offset base addr. PADCONF addr.
---- ---------- ----------
OMAP34xx: 0x50 0x480025d8 0x48002628 *NO*
OMAP36xx: 0x50 0x480025a0 0x480025F0 *ok*

Looking at the TRM, the PADCONF address for hsusb2_clk is 0x480025F0 in both cases. Thus we will be wrong on OMAP34xx (offset should be 0x18 instead of 0x50). Thus so far, I do not see any magical solution apart putting the omap3_pmx_core2 pins in a SoC-dependant .dtsi file.

Quoted 4 lines

I already expressed my concerns [1] about having a different base address for omap3_pmx_core2 depending on the SoC (although I do understand the rational behind). This makes cross-SoC platforms more difficult to maintain.

Any sane design would maintain register offsets but it doesn't seem so with omap34xx vs omap36xx. So my assumption was wrong.

I'll ack this patch.

cheers,
-roger

#11 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

Quoted 5 lines · Roger Quadros

Any sane design would maintain register offsets but it doesn't seem so with omap34xx vs omap36xx. So my assumption was wrong.

I'll ack this patch.

OK thanks, I'll apply the whole series with your ack to omap-for-v3.15/dt-overo.

Regards,

Tony

author
#12 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

Quoted 9 lines · Tony Lindgren
Quoted 5 lines · Roger Quadros

Any sane design would maintain register offsets but it doesn't seem so with omap34xx vs omap36xx. So my assumption was wrong.

I'll ack this patch.

OK thanks, I'll apply the whole series with your ack to omap-for-v3.15/dt-overo.

Thanks!

Florian

#13 lore raw

PATCH v4 5/9 ARM: dts: omap3-overo: Add HSUSB PHY

In reply to Florian Vaussard
Quoted 3 lines · Florian Vaussard

Add the High-Speed USB PHY.

Signed-off-by Florian Vaussard <[email protected]>
Acked-by Roger Quadros <[email protected]>

cheers,
-roger

Quoted 137 lines
---
 arch/arm/boot/dts/omap3-overo-base.dtsi  | 44 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap3-overo-storm.dtsi | 16 ++++++++++++
 arch/arm/boot/dts/omap3-overo.dtsi       | 16 ++++++++++++
 3 files changed, 76 insertions(+)
arch/arm/boot/dts/omap3-overo-base.dtsi +44 -0
index edac70e..13d1ad2 100644
@@ -30,6 +30,24 @@
 		ti,codec = <&twl_audio>;
 	};
 
+	/* HS USB Port 2 Power */
+	hsusb2_power: hsusb2_power_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "hsusb2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio6 8 0>;				/* gpio_168: vbus enable */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	/* HS USB Host PHY on PORT 2 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;	/* gpio_183 */
+		vcc-supply = <&hsusb2_power>;
+	};
+
 	/* Regulator to trigger the nPoweron signal of the Wifi module */
 	w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
 		compatible = "regulator-fixed";

@@ -64,6 +82,11 @@
 };
 
 &omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_pins
+	>;
+
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */

@@ -116,6 +139,19 @@
 			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
 		>;
 	};
+
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)		/* i2c2_scl.gpio_168 */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4)		/* i2c2_sda.gpio_183 */
+		>;
+	};
 };
 
 &i2c1 {

@@ -177,6 +213,14 @@
 	power = <50>;
 };
 
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
arch/arm/boot/dts/omap3-overo-storm.dtsi +16 -0
index c235ae8..6cb418b 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+
 	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
 		pinctrl-single,pins = <
 			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
arch/arm/boot/dts/omap3-overo.dtsi +16 -0
index 95c59b2..c37b130 100644
@@ -10,6 +10,22 @@
 #include "omap3-overo-base.dtsi"
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+
 	w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
 		pinctrl-single,pins = <
 			OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)		/* etk_d2.gpio_16 */
author
#14 lore raw

PATCH v4 6/9 ARM: dts: omap: Add common file for SMSC9221

In reply to Florian Vaussard

Some devices (SMSC9217, SMSC9218 and SMSC9221 at least) have better timings, allowing a higher transfer speed. Create a common file with these timings.

Performance results with iperf:

- omap-gpmc-smsc911x.dtsi => 54.9 Mbps
- omap-gpmc-smsc9221.dtsi => 92.7 Mbps

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi | 58 +++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi new file +58 -0
new file mode 100644
index 0000000..73e272f
@@ -0,0 +1,58 @@
+/*
+ * Common file for GPMC connected smsc9221 on omaps
+ *
+ * Compared to smsc911x, smsc9221 (and others like smsc9217
+ * or smsc 9218) has faster timings, leading to higher
+ * bandwidth.
+ *
+ * Note that the board specifc DTS file needs to specify
+ * ranges, pinctrl, reg, interrupt parent and interrupts.
+ */
+
+/ {
+	vddvario: regulator-vddvario {
+		  compatible = "regulator-fixed";
+		  regulator-name = "vddvario";
+		  regulator-always-on;
+	};
+
+	vdd33a: regulator-vdd33a {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd33a";
+		regulator-always-on;
+	};
+};
+
+&gpmc {
+	ethernet at gpmc {
+		compatible = "smsc,lan9221","smsc,lan9115";
+		bank-width = <2>;
+
+		gpmc,mux-add-data;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <42>;
+		gpmc,cs-wr-off-ns = <36>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <12>;
+		gpmc,adv-wr-off-ns = <12>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <42>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <36>;
+		gpmc,rd-cycle-ns = <60>;
+		gpmc,wr-cycle-ns = <54>;
+		gpmc,access-ns = <36>;
+		gpmc,page-burst-access-ns = <0>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <18>;
+		gpmc,wr-access-ns = <42>;
+		gpmc,cycle2cycle-samecsen;
+		gpmc,cycle2cycle-diffcsen;
+
+		vddvario-supply = <&vddvario>;
+		vdd33a-supply = <&vdd33a>;
+		reg-io-width = <4>;
+		smsc,save-mac-address;
+	};
+};
Signature · 1 line
1.8.3.2
author
#15 lore raw

PATCH v4 7/9 ARM: dts: omap3-tobi: Use include file omap-gpmc-smsc9221

In reply to Florian Vaussard

Use the timings provided by omap-gpmc-smsc9221. This does not change the timings, but it avoids code duplication.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-tobi-common.dtsi | 42 ++------------------------
 1 file changed, 3 insertions(+), 39 deletions(-)
arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +3 -39
index 7375cda..e7f2ac7 100644
@@ -19,18 +19,6 @@
 			linux,default-trigger = "heartbeat";
 		};
 	};
-
-	vddvario: regulator-vddvario {
-		  compatible = "regulator-fixed";
-		  regulator-name = "vddvario";
-		  regulator-always-on;
-	};
-
-	vdd33a: regulator-vdd33a {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd33a";
-		regulator-always-on;
-	};
 };
 
 &omap3_pmx_core {

@@ -42,39 +30,15 @@
 	};
 };
 
+#include "omap-gpmc-smsc9221.dtsi"
+
 &gpmc {
 	ranges = <5 0 0x2c000000 0x1000000>;	/* CS5 */
 
-	ethernet at 5,0 {
-		compatible = "smsc,lan9221", "smsc,lan9115";
+	ethernet at gpmc {
 		reg = <5 0 0xff>;
-		bank-width = <2>;
-
-		gpmc,mux-add-data;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <42>;
-		gpmc,cs-wr-off-ns = <36>;
-		gpmc,adv-on-ns = <6>;
-		gpmc,adv-rd-off-ns = <12>;
-		gpmc,adv-wr-off-ns = <12>;
-		gpmc,oe-on-ns = <0>;
-		gpmc,oe-off-ns = <42>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <36>;
-		gpmc,rd-cycle-ns = <60>;
-		gpmc,wr-cycle-ns = <54>;
-		gpmc,access-ns = <36>;
-		gpmc,page-burst-access-ns = <0>;
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,wr-data-mux-bus-ns = <18>;
-		gpmc,wr-access-ns = <42>;
-		gpmc,cycle2cycle-samecsen;
-		gpmc,cycle2cycle-diffcsen;
-
 		interrupt-parent = <&gpio6>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;	/* GPIO 176 */
-		reg-io-width = <4>;
 	};
 };
Signature · 1 line
1.8.3.2
author
#16 lore raw

PATCH v4 8/9 ARM: dts: omap3-tobi: Add AT24C01 EEPROM

In reply to Florian Vaussard

Add the AT24C01 EEPROM node populated on most Gumstix expansion board.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-tobi-common.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +7 -0
index e7f2ac7..0312d22 100644
@@ -46,6 +46,13 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c3_pins>;
 	clock-frequency = <100000>;
+
+	/* optional 1K EEPROM with revision information */
+	eeprom at 51 {
+		compatible = "atmel,24c01";
+		reg = <0x51>;
+		pagesize = <8>;
+	};
 };
 
 &mmc3 {
Signature · 1 line
1.8.3.2
author
#17 lore raw

PATCH v4 9/9 ARM: dts: overo: Push uart3 pinmux down to expansion board

In reply to Florian Vaussard

UART3 is used by expansion boards to get a tty console. Thus, the pinmux should be defined by expansion boards, instead of being imposed by the processor board.

Signed-off-by Florian Vaussard <[email protected]>
---
 arch/arm/boot/dts/omap3-overo-base.dtsi        | 11 -----------
 arch/arm/boot/dts/omap3-overo-tobi-common.dtsi | 13 +++++++++++++
 2 files changed, 13 insertions(+), 11 deletions(-)
arch/arm/boot/dts/omap3-overo-base.dtsi +0 -11
index 13d1ad2..d36bf02 100644
@@ -96,13 +96,6 @@
 		>;
 	};
 
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0)	/* uart3_rx_irrx.uart3_rx_irrx */
-			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
-		>;
-	};
-
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)		/* i2c1_scl.i2c1_scl */

@@ -226,7 +219,3 @@
 	pinctrl-0 = <&uart2_pins>;
 };
 
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins>;
-};
arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +13 -0
index 0312d22..384e87d 100644
@@ -28,6 +28,13 @@
 			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda.i2c3_sda */
 		>;
 	};
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0)	/* uart3_rx_irrx.uart3_rx_irrx */
+			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
+		>;
+	};
 };
 
 #include "omap-gpmc-smsc9221.dtsi"

@@ -58,3 +65,9 @@
 &mmc3 {
 	status = "disabled";
 };
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
Signature · 1 line
1.8.3.2