clockevents : new material for 3.15
Subsystems (11)
Hi Thomas, Ingo,
here it the pull request for 3.15:
* Ezequiel Garcia used the atomic access for shared register for orion
and armada-370-xp. It allows to use the watchdog which shares the register
* Ivan Khoronzhuk added the keystone driver
* Linus Walleij moved the u300 driver into the clocksource directory
* Magnus Damm re-ordered the Kconfig options for CMT, TMU and STI in
order to move them in the clocksource drivers' Kconfig file
* Matthias Brugger removes an useless variable for keystone
* Maxime Ripard added some new compatibles in the DT
* Soren Brinkmann added the cpufreq support for zynq. The patchset has
been floating around since a while now. I reviewed the patchset, it seems ok for me but may be more experimented eyes should have a look at the "Overhaul clocksource frequency adjustment" patch
* Stephen Boyd added the dynamic irq affinity for the arch timer
The following changes since commit f9a8a0abc3138a623895dcb6c2575ca31ca3da34:
[14/1841]
Merge branch 'fortglx/3.15/time' ofgit://git.linaro.org/people/john.stultz/linux into timers/core (2014-03-10 19:53:09 +0100)
are available in the git repository at:
git://git.linaro.org/people/daniel.lezcano/linux.git clockevents/next
for you to fetch changes up to 09e15176ded1faa7bd685b3b5b1213cf0240566e:
clocksource: exynos_mct: silence a static checker warning (2014-03-11
23:13:23 +0100)
----------------------------------------------------------------
Dan Carpenter (1):
clocksource: exynos_mct: silence a static checker warning
Ezequiel Garcia (2):
clocksource: orion: Use atomic access for shared registers
clocksource: armada-370-xp: Use atomic access for shared registers
Ivan Khoronzhuk (2):
clocksource: keystone: add bindings for keystone timer
clocksource: timer-keystone: introduce clocksource driver for
Keystone
Linus Walleij (1):
ARM: u300: move timer driver to clocksource
Magnus Damm (3):
ARM: shmobile: Remove CMT, TMU and STI Kconfig entries
sh: Remove Kconfig entries for TMU, CMT and MTU2
clocksource: Add Kconfig entries for CMT, MTU2, TMU and STI
Matthias Brugger (1):
clocksource: timer-keystone: Delete unnecessary variable
Maxime Ripard (2):
clocksource: sunxi: Add new compatibles
ARM: sunxi: dt: Convert to the new clocksource compatible
Soren Brinkmann (4):
clocksource/cadence_ttc: Call clockevents_update_freq() with IRQs
enabled
clocksource/cadence_ttc: Overhaul clocksource frequency adjustment
arm: zynq: Don't use arm_global_timer with cpufreq
arm: zynq: Add support for cpufreq
Stephen Boyd (1):
clocksource: arch_timer: Set dynamic irq affinity on mmio clockevent
.../bindings/timer/allwinner,sun4i-timer.txt | 4 +- .../bindings/timer/ti,keystone-timer.txt | 29 +++ MAINTAINERS | 1 + arch/arm/boot/dts/sun4i-a10.dtsi | 2 +- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- arch/arm/boot/dts/zynq-7000.dtsi | 6 + arch/arm/mach-shmobile/Kconfig | 36 +-- arch/arm/mach-u300/Makefile | 2 +- arch/arm/mach-zynq/Kconfig | 4 +- arch/arm/mach-zynq/common.c | 3 + arch/sh/Kconfig | 76 ++---- drivers/clocksource/Kconfig | 44 ++++ drivers/clocksource/Makefile | 2 + drivers/clocksource/arm_arch_timer.c | 1 + drivers/clocksource/cadence_ttc_timer.c | 121 +++++++--- drivers/clocksource/exynos_mct.c | 2 +- drivers/clocksource/sun4i_timer.c | 2 +- drivers/clocksource/time-armada-370-xp.c | 12 +- drivers/clocksource/time-orion.c | 28 +-- drivers/clocksource/timer-keystone.c | 241 ++++++++++++++++++++ .../timer.c => drivers/clocksource/timer-u300.c | 4 - 24 files changed, 481 insertions(+), 147 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/ti,keystone-timer.txt create mode 100644 drivers/clocksource/timer-keystone.c rename arch/arm/mach-u300/timer.c => drivers/clocksource/timer-u300.c
(99%)
Signature · 5 lines
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PATCH 1/17 clocksource: arch_timer: Set dynamic irq affinity on mmio clockevent
From: Stephen Boyd <[email protected]>
Set the CLOCK_EVT_FEAT_DYNIRQ flag on the memory mapped clockevent so that we save power by waking up the CPU with the next event when this timer is used in broadcast mode.
--- drivers/clocksource/arm_arch_timer.c | 1 + 1 file changed, 1 insertion(+)
drivers/clocksource/arm_arch_timer.c +1 -0
@@ -277,6 +277,7 @@ static void __arch_timer_setup(unsigned type, clk->set_next_event = arch_timer_set_next_event_phys; } }else { + clk->features |=CLOCK_EVT_FEAT_DYNIRQ ; clk->name ="arch_mem_timer" ; clk->rating =400 ; clk->cpumask = cpu_all_mask;
Signature · 1 line
1.7.9.5
PATCH 2/17 ARM: u300: move timer driver to clocksource
From: Linus Walleij <[email protected]>
Move the U300 timer driver down to the clocksource driver subsystem and keep arch/arm clean.
--- MAINTAINERS | 1 + arch/arm/mach-u300/Makefile | 2 +- arch/arm/mach-u300/timer.c | 451 -------------------------------------- drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-u300.c | 447 +++++++++++++++++++++++++++++++++++++ 5 files changed, 450 insertions(+), 452 deletions(-) delete mode 100644 arch/arm/mach-u300/timer.c create mode 100644 drivers/clocksource/timer-u300.c
MAINTAINERS +1 -0
@@ -1319,6 +1319,7 @@ M: Linus Walleij <[email protected]> L: [email protected] (moderated for non-subscribers) S: Supported F: arch/arm/mach-u300/ +F: drivers/clocksource/timer-u300.c F: drivers/i2c/busses/i2c-stu300.c F: drivers/rtc/rtc-coh901331.c F: drivers/watchdog/coh901327_wdt.c
arch/arm/mach-u300/Makefile +1 -1
@@ -2,7 +2,7 @@ # Makefile for the linux kernel, U300 machine. # -obj-y := core.o timer.o +obj-y := core.o obj-m := obj-n := obj- :=
arch/arm/mach-u300/timer.c deleted +0 -451
451 lines not on this page · raw message
drivers/clocksource/Makefile +1 -0
@@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_MARCO) += timer-marco.o obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o obj-$(CONFIG_ARCH_MXS) += mxs_timer.o obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o +obj-$(CONFIG_ARCH_U300) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
drivers/clocksource/timer-u300.c new file +447 -0
447 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 3/17 clocksource: sunxi: Add new compatibles
In reply to Daniel LezcanoFrom: Maxime Ripard <[email protected]>
The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the timer driver for consistency, and keep the older one for backward compatibility.
--- .../bindings/timer/allwinner,sun4i-timer.txt | 4 ++-- drivers/clocksource/sun4i_timer.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt +2 -2
@@ -2,7 +2,7 @@ Allwinner A1X SoCs Timer Controller Required properties: -- compatible : should be "allwinner,sun4i-timer" +- compatible : should be "allwinner,sun4i-a10-timer" - reg : Specifies base physical address and size of the registers. - interrupts : The interrupt of the first timer - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
@@ -10,7 +10,7 @@ Required properties: Example: timer { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x400>; interrupts = <22>; clocks = <&osc>;
drivers/clocksource/sun4i_timer.c +1 -1
@@ -196,5 +196,5 @@ static void __init sun4i_timer_init(struct device_node *node)clockevents_config_and_register (&sun4i_clockevent, rate,TIMER_SYNC_TICKS ,0xffffffff ); } -CLOCKSOURCE_OF_DECLARE (sun4i,"allwinner,sun4i-timer" , +CLOCKSOURCE_OF_DECLARE (sun4i,"allwinner,sun4i-a10-timer" , sun4i_timer_init);
Signature · 1 line
1.7.9.5
PATCH 4/17 ARM: sunxi: dt: Convert to the new clocksource compatible
In reply to Daniel LezcanoFrom: Maxime Ripard <[email protected]>
Switch the device tree to the new compatibles introduced in the timer driver to have a common pattern accross all Allwinner SoCs.
--- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-)
arch/arm/boot/dts/sun4i-a10.dtsi +1 -1
@@ -403,7 +403,7 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>;
arch/arm/boot/dts/sun5i-a10s.dtsi +1 -1
@@ -366,7 +366,7 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>;
arch/arm/boot/dts/sun5i-a13.dtsi +1 -1
@@ -329,7 +329,7 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <22>; clocks = <&osc24M>;
arch/arm/boot/dts/sun6i-a31.dtsi +1 -1
@@ -231,7 +231,7 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <0 18 4>, <0 19 4>,
arch/arm/boot/dts/sun7i-a20.dtsi +1 -1
@@ -435,7 +435,7 @@ }; timer@01c20c00 { - compatible = "allwinner,sun4i-timer"; + compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0x90>; interrupts = <0 22 4>, <0 23 4>,
Signature · 1 line
1.7.9.5
PATCH 5/17 clocksource: keystone: add bindings for keystone timer
In reply to Daniel LezcanoFrom: Ivan Khoronzhuk <[email protected]>
This patch provides bindings for the 64-bit timer in the KeyStone architecture devices. The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other.
It is global timer is a free running up-counter and can generate interrupt when the counter reaches preset counter values.
Documentation:
http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
--- .../bindings/timer/ti,keystone-timer.txt | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
Documentation/devicetree/bindings/timer/ti,keystone-timer.txt new file +29 -0
@@ -0,0 +1,29 @@ +* Device tree bindings for Texas instruments Keystone timer + +This document provides bindings for the 64-bit timer in the KeyStone +architecture devices. The timer can be configured as a general-purpose 64-bit +timer, dual general-purpose 32-bit timers. When configured as dual 32-bit +timers, each half can operate in conjunction (chain mode) or independently +(unchained mode) of each other. + +It is global timer is a free running up-counter and can generate interrupt +when the counter reaches preset counter values. + +Documentation: +http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf + +Required properties: + +- compatible : should be "ti,keystone-timer". +- reg : specifies base physical address and count of the registers. +- interrupts : interrupt generated by the timer. +- clocks : the clock feeding the timer clock. + +Example: + +timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; + clocks = <&clktimer15>; +};
Signature · 1 line
1.7.9.5
PATCH 6/17 clocksource: timer-keystone: introduce clocksource driver for Keystone
In reply to Daniel LezcanoFrom: Ivan Khoronzhuk <[email protected]>
Add broadcast clock-event device for the Keystone arch.
The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other.
--- drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-keystone.c | 244 ++++++++++++++++++++++++++++++++++ 2 files changed, 245 insertions(+) create mode 100644 drivers/clocksource/timer-keystone.c
drivers/clocksource/Makefile +1 -0
@@ -38,3 +38,4 @@ obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o +obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o
drivers/clocksource/timer-keystone.c new file +244 -0
244 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 7/17 clocksource: timer-keystone: Delete unnecessary variable
In reply to Daniel LezcanoFrom: Matthias Brugger <[email protected]>
Commit 438e0bff5257 added the timer-keystone device driver but make use of an unnecessary variable in the init function. This patch deletes this variable.
--- drivers/clocksource/timer-keystone.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/clocksource/timer-keystone.c +1 -4
@@ -164,7 +164,6 @@ static void __init keystone_timer_init(struct device_node *np)unsigned long rate;struct clk *clk;int irq, error; -u32 tgcr; irq =irq_of_parse_and_map (np,0 );if (irq ==NO_IRQ ) {
@@ -199,12 +198,10 @@ static void __init keystone_timer_init(struct device_node *np)keystone_timer_barrier ();/* reset timer as 64-bit, no pre-scaler, plus features are disabled */ - tgcr =0 ;keystone_timer_writel (0 ,TGCR );/* unreset timer */ - tgcr |=TGCR_TIM_UNRESET_MASK ; -keystone_timer_writel (tgcr,TGCR ); +keystone_timer_writel (TGCR_TIM_UNRESET_MASK ,TGCR );/* init counter to zero */ keystone_timer_writel (0 ,TIM12 );
Signature · 1 line
1.7.9.5
PATCH 8/17 clocksource: orion: Use atomic access for shared registers
In reply to Daniel LezcanoFrom: Ezequiel Garcia <[email protected]>
Replace the driver-specific thread-safe shared register API by the recently introduced atomic_io_clear_set().
--- drivers/clocksource/time-orion.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-)
drivers/clocksource/time-orion.c +10 -18
@@ -35,20 +35,6 @@#define ORION_ONESHOT_MAX 0xfffffffestatic void __iomem *timer_base; -static DEFINE_SPINLOCK (timer_ctrl_lock); - -/* -* Thread-safe access to TIMER_CTRL register -* (shared with watchdog timer) -*/ -void orion_timer_ctrl_clrset (u32 clr,u32 set) -{ -spin_lock (&timer_ctrl_lock); -writel ((readl (timer_base +TIMER_CTRL ) & ~clr) | set, - timer_base +TIMER_CTRL ); -spin_unlock (&timer_ctrl_lock); -} -EXPORT_SYMBOL (orion_timer_ctrl_clrset);/* * Free-running clocksource handling.
@@ -68,7 +54,8 @@ static int orion_clkevt_next_event(unsigned long delta, {/* setup and enable one-shot timer */ writel (delta, timer_base +TIMER1_VAL ); -orion_timer_ctrl_clrset (TIMER1_RELOAD_EN ,TIMER1_EN ); +atomic_io_modify (timer_base +TIMER_CTRL , +TIMER1_RELOAD_EN |TIMER1_EN ,TIMER1_EN );return 0 ; }
@@ -80,10 +67,13 @@ static void orion_clkevt_mode(enum clock_event_mode mode,/* setup and enable periodic timer at 1/HZ intervals */ writel (ticks_per_jiffy -1 , timer_base +TIMER1_RELOAD );writel (ticks_per_jiffy -1 , timer_base +TIMER1_VAL ); -orion_timer_ctrl_clrset (0 ,TIMER1_RELOAD_EN |TIMER1_EN ); +atomic_io_modify (timer_base +TIMER_CTRL , +TIMER1_RELOAD_EN |TIMER1_EN , +TIMER1_RELOAD_EN |TIMER1_EN ); }else {/* disable timer */ -orion_timer_ctrl_clrset (TIMER1_RELOAD_EN |TIMER1_EN ,0 ); +atomic_io_modify (timer_base +TIMER_CTRL , +TIMER1_RELOAD_EN |TIMER1_EN ,0 ); } }
@@ -131,7 +121,9 @@ static void __init orion_timer_init(struct device_node *np)/* setup timer0 as free-running clocksource */ writel (~0 , timer_base +TIMER0_VAL );writel (~0 , timer_base +TIMER0_RELOAD ); -orion_timer_ctrl_clrset (0 ,TIMER0_RELOAD_EN |TIMER0_EN ); +atomic_io_modify (timer_base +TIMER_CTRL , +TIMER0_RELOAD_EN |TIMER0_EN , +TIMER0_RELOAD_EN |TIMER0_EN );clocksource_mmio_init (timer_base +TIMER0_VAL ,"orion_clocksource" ,clk_get_rate (clk),300 ,32 , clocksource_mmio_readl_down);
Signature · 1 line
1.7.9.5
PATCH 9/17 clocksource: armada-370-xp: Use atomic access for shared registers
In reply to Daniel LezcanoFrom: Ezequiel Garcia <[email protected]>
Replace the driver-specific thread-safe shared register API by the recently introduced atomic_io_clear_set().
--- drivers/clocksource/time-armada-370-xp.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-)
drivers/clocksource/time-armada-370-xp.c +4 -8
@@ -85,12 +85,6 @@ static u32 ticks_per_jiffy;static struct clock_event_device __percpu *armada_370_xp_evt; -static void timer_ctrl_clrset (u32 clr,u32 set) -{ -writel ((readl (timer_base +TIMER_CTRL_OFF ) & ~clr) | set, - timer_base +TIMER_CTRL_OFF ); -} -static void local_timer_ctrl_clrset (u32 clr,u32 set) { writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
@@ -245,7 +239,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np) clr =TIMER0_25MHZ ; enable_mask =TIMER0_EN |TIMER0_DIV (TIMER_DIVIDER_SHIFT ); } -timer_ctrl_clrset (clr, set); +atomic_io_modify (timer_base +TIMER_CTRL_OFF , clr | set, set);local_timer_ctrl_clrset (clr, set);/*
@@ -263,7 +257,9 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)writel (0xffffffff , timer_base +TIMER0_VAL_OFF );writel (0xffffffff , timer_base +TIMER0_RELOAD_OFF ); -timer_ctrl_clrset (0 ,TIMER0_RELOAD_EN | enable_mask); +atomic_io_modify (timer_base +TIMER_CTRL_OFF , +TIMER0_RELOAD_EN | enable_mask, +TIMER0_RELOAD_EN | enable_mask);/* * Set scale and timer for sched_clock.
Signature · 1 line
1.7.9.5
PATCH 10/17 ARM: shmobile: Remove CMT, TMU and STI Kconfig entries
In reply to Daniel LezcanoFrom: Magnus Damm <[email protected]>
Now when drivers/clocksource/Kconfig has been updated with entires for CMT, TMU, MTU2, and STI it is safe to remove these from mach-shmobile.
Also select timers per SoC via SYS_SUPPORTS_xxx.
--- arch/arm/mach-shmobile/Kconfig | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-)
arch/arm/mach-shmobile/Kconfig +18 -18
@@ -24,17 +24,21 @@ comment "Renesas ARM SoCs System Type" config ARCH_EMEV2 bool "Emma Mobile EV2" + select SYS_SUPPORTS_EM_STI config ARCH_R7S72100 bool "RZ/A1H (R7S72100)" + select SYS_SUPPORTS_SH_MTU2 config ARCH_R8A7790 bool "R-Car H2 (R8A77900)" select RENESAS_IRQC + select SYS_SUPPORTS_SH_CMT config ARCH_R8A7791 bool "R-Car M2 (R8A77910)" select RENESAS_IRQC + select SYS_SUPPORTS_SH_CMT comment "Renesas ARM SoCs Board Type"
@@ -68,6 +72,8 @@ config ARCH_SH7372 select ARM_CPU_SUSPEND if PM || CPU_IDLE select CPU_V7 select SH_CLK_CPG + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_TMU config ARCH_SH73A0 bool "SH-Mobile AG5 (R8A73A00)"
@@ -77,6 +83,8 @@ config ARCH_SH73A0 select I2C select SH_CLK_CPG select RENESAS_INTC_IRQPIN + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_TMU config ARCH_R8A73A4 bool "R-Mobile APE6 (R8A73A40)"
@@ -87,6 +95,8 @@ config ARCH_R8A73A4 select RENESAS_IRQC select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_TMU config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)"
@@ -95,6 +105,8 @@ config ARCH_R8A7740 select CPU_V7 select SH_CLK_CPG select RENESAS_INTC_IRQPIN + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_TMU config ARCH_R8A7778 bool "R-Car M1A (R8A77781)"
@@ -104,6 +116,7 @@ config ARCH_R8A7778 select ARM_GIC select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI + select SYS_SUPPORTS_SH_TMU config ARCH_R8A7779 bool "R-Car H1 (R8A77790)"
@@ -114,6 +127,7 @@ config ARCH_R8A7779 select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI select RENESAS_INTC_IRQPIN + select SYS_SUPPORTS_SH_TMU config ARCH_R8A7790 bool "R-Car H2 (R8A77900)"
@@ -123,6 +137,7 @@ config ARCH_R8A7790 select MIGHT_HAVE_PCI select SH_CLK_CPG select RENESAS_IRQC + select SYS_SUPPORTS_SH_CMT config ARCH_R8A7791 bool "R-Car M2 (R8A77910)"
@@ -132,6 +147,7 @@ config ARCH_R8A7791 select MIGHT_HAVE_PCI select SH_CLK_CPG select RENESAS_IRQC + select SYS_SUPPORTS_SH_CMT config ARCH_EMEV2 bool "Emma Mobile EV2"
@@ -141,6 +157,7 @@ config ARCH_EMEV2 select MIGHT_HAVE_PCI select USE_OF select AUTO_ZRELADDR + select SYS_SUPPORTS_EM_STI config ARCH_R7S72100 bool "RZ/A1H (R7S72100)"
@@ -148,6 +165,7 @@ config ARCH_R7S72100 select ARM_GIC select CPU_V7 select SH_CLK_CPG + select SYS_SUPPORTS_SH_MTU2 comment "Renesas ARM SoCs Board Type"
@@ -321,24 +339,6 @@ config SHMOBILE_TIMER_HZ want to select a HZ value such as 128 that can evenly divide RCLK. A HZ value that does not divide evenly may cause timer drift. -config SH_TIMER_CMT - bool "CMT timer driver" - default y - help - This enables build of the CMT timer driver. - -config SH_TIMER_TMU - bool "TMU timer driver" - default y - help - This enables build of the TMU timer driver. - -config EM_TIMER_STI - bool "STI timer driver" - default y - help - This enables build of the STI timer driver. - endmenu endif
Signature · 1 line
1.7.9.5
PATCH 11/17 sh: Remove Kconfig entries for TMU, CMT and MTU2
In reply to Daniel LezcanoFrom: Magnus Damm <[email protected]>
Now when drivers/clocksource/Kconfig has been updated with entires for CMT, TMU and MTU2
it is safe to remove these from SH.
--- arch/sh/Kconfig | 76 +++++++++++++++++-------------------------------------- 1 file changed, 23 insertions(+), 53 deletions(-)
arch/sh/Kconfig +23 -53
@@ -123,15 +123,6 @@ config SYS_SUPPORTS_NUMA config SYS_SUPPORTS_PCI bool -config SYS_SUPPORTS_CMT - bool - -config SYS_SUPPORTS_MTU2 - bool - -config SYS_SUPPORTS_TMU - bool - config STACKTRACE_SUPPORT def_bool y
@@ -191,14 +182,14 @@ config CPU_SH3 bool select CPU_HAS_INTEVT select CPU_HAS_SR_RB - select SYS_SUPPORTS_TMU + select SYS_SUPPORTS_SH_TMU config CPU_SH4 bool select CPU_HAS_INTEVT select CPU_HAS_SR_RB select CPU_HAS_FPU if !CPU_SH4AL_DSP - select SYS_SUPPORTS_TMU + select SYS_SUPPORTS_SH_TMU select SYS_SUPPORTS_HUGETLBFS if MMU config CPU_SH4A
@@ -213,7 +204,7 @@ config CPU_SH4AL_DSP config CPU_SH5 bool select CPU_HAS_FPU - select SYS_SUPPORTS_TMU + select SYS_SUPPORTS_SH_TMU select SYS_SUPPORTS_HUGETLBFS if MMU config CPU_SHX2
@@ -250,7 +241,7 @@ choice config CPU_SUBTYPE_SH7619 bool "Support SH7619 processor" select CPU_SH2 - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT # SH-2A Processor Support
@@ -258,50 +249,50 @@ config CPU_SUBTYPE_SH7201 bool "Support SH7201 processor" select CPU_SH2A select CPU_HAS_FPU - select SYS_SUPPORTS_MTU2 + select SYS_SUPPORTS_SH_MTU2 config CPU_SUBTYPE_SH7203 bool "Support SH7203 processor" select CPU_SH2A select CPU_HAS_FPU - select SYS_SUPPORTS_CMT - select SYS_SUPPORTS_MTU2 + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 select ARCH_WANT_OPTIONAL_GPIOLIB select PINCTRL config CPU_SUBTYPE_SH7206 bool "Support SH7206 processor" select CPU_SH2A - select SYS_SUPPORTS_CMT - select SYS_SUPPORTS_MTU2 + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 config CPU_SUBTYPE_SH7263 bool "Support SH7263 processor" select CPU_SH2A select CPU_HAS_FPU - select SYS_SUPPORTS_CMT - select SYS_SUPPORTS_MTU2 + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 config CPU_SUBTYPE_SH7264 bool "Support SH7264 processor" select CPU_SH2A select CPU_HAS_FPU - select SYS_SUPPORTS_CMT - select SYS_SUPPORTS_MTU2 + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 select PINCTRL config CPU_SUBTYPE_SH7269 bool "Support SH7269 processor" select CPU_SH2A select CPU_HAS_FPU - select SYS_SUPPORTS_CMT - select SYS_SUPPORTS_MTU2 + select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_MTU2 select PINCTRL config CPU_SUBTYPE_MXG bool "Support MX-G processor" select CPU_SH2A - select SYS_SUPPORTS_MTU2 + select SYS_SUPPORTS_SH_MTU2 help Select MX-G if running on an R8A03022BG part.
@@ -354,7 +345,7 @@ config CPU_SUBTYPE_SH7720 bool "Support SH7720 processor" select CPU_SH3 select CPU_HAS_DSP - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT select ARCH_WANT_OPTIONAL_GPIOLIB select USB_ARCH_HAS_OHCI select USB_OHCI_SH if USB_OHCI_HCD
@@ -366,7 +357,7 @@ config CPU_SUBTYPE_SH7721 bool "Support SH7721 processor" select CPU_SH3 select CPU_HAS_DSP - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT select USB_ARCH_HAS_OHCI select USB_OHCI_SH if USB_OHCI_HCD help
@@ -422,7 +413,7 @@ config CPU_SUBTYPE_SH7723 select CPU_SHX2 select ARCH_SHMOBILE select ARCH_SPARSEMEM_ENABLE - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT select ARCH_WANT_OPTIONAL_GPIOLIB select PINCTRL help
@@ -434,7 +425,7 @@ config CPU_SUBTYPE_SH7724 select CPU_SHX2 select ARCH_SHMOBILE select ARCH_SPARSEMEM_ENABLE - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT select ARCH_WANT_OPTIONAL_GPIOLIB select PINCTRL help
@@ -514,7 +505,7 @@ config CPU_SUBTYPE_SH7343 bool "Support SH7343 processor" select CPU_SH4AL_DSP select ARCH_SHMOBILE - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT config CPU_SUBTYPE_SH7722 bool "Support SH7722 processor"
@@ -523,7 +514,7 @@ config CPU_SUBTYPE_SH7722 select ARCH_SHMOBILE select ARCH_SPARSEMEM_ENABLE select SYS_SUPPORTS_NUMA - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT select ARCH_WANT_OPTIONAL_GPIOLIB select PINCTRL
@@ -534,7 +525,7 @@ config CPU_SUBTYPE_SH7366 select ARCH_SHMOBILE select ARCH_SPARSEMEM_ENABLE select SYS_SUPPORTS_NUMA - select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_SH_CMT endchoice
@@ -567,27 +558,6 @@ source "arch/sh/boards/Kconfig" menu "Timer and clock configuration" -config SH_TIMER_TMU - bool "TMU timer driver" - depends on SYS_SUPPORTS_TMU - default y - help - This enables the build of the TMU timer driver. - -config SH_TIMER_CMT - bool "CMT timer driver" - depends on SYS_SUPPORTS_CMT - default y - help - This enables build of the CMT timer driver. - -config SH_TIMER_MTU2 - bool "MTU2 timer driver" - depends on SYS_SUPPORTS_MTU2 - default y - help - This enables build of the MTU2 timer driver. - config SH_PCLK_FREQ int "Peripheral clock frequency (in Hz)" depends on SH_CLK_CPG_LEGACY
Signature · 1 line
1.7.9.5
PATCH 12/17 clocksource: Add Kconfig entries for CMT, MTU2, TMU and STI
In reply to Daniel LezcanoFrom: Magnus Damm <[email protected]>
Add Kconfig entries for CMT, MTU2, TMU and STI to drivers/clocksource/Kconfig. This will allow us to get rid of duplicated entires in architecture code such as arch/sh and arch/arm/mach-shmobile.
--- drivers/clocksource/Kconfig | 44 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)
drivers/clocksource/Kconfig +44 -0
@@ -140,3 +140,47 @@ config VF_PIT_TIMER bool help Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. + +config SYS_SUPPORTS_SH_CMT + bool + +config SYS_SUPPORTS_SH_MTU2 + bool + +config SYS_SUPPORTS_SH_TMU + bool + +config SYS_SUPPORTS_EM_STI + bool + +config SH_TIMER_CMT + bool "Renesas CMT timer driver" if COMPILE_TEST + default SYS_SUPPORTS_SH_CMT + help + This enables build of a clocksource and clockevent driver for + the Compare Match Timer (CMT) hardware available in 16/32/48-bit + variants on a wide range of Mobile and Automotive SoCs from Renesas. + +config SH_TIMER_MTU2 + bool "Renesas MTU2 timer driver" if COMPILE_TEST + default SYS_SUPPORTS_SH_MTU2 + help + This enables build of a clockevent driver for the Multi-Function + Timer Pulse Unit 2 (TMU2) hardware available on SoCs from Renesas. + This hardware comes with 16 bit-timer registers. + +config SH_TIMER_TMU + bool "Renesas TMU timer driver" if COMPILE_TEST + default SYS_SUPPORTS_SH_TMU + help + This enables build of a clocksource and clockevent driver for + the 32-bit Timer Unit (TMU) hardware available on a wide range + SoCs from Renesas. + +config EM_TIMER_STI + bool "Renesas STI timer driver" if COMPILE_TEST + default SYS_SUPPORTS_EM_STI + help + This enables build of a clocksource and clockevent driver for + the 48-bit System Timer (STI) hardware available on a SoCs + such as EMEV2 from former NEC Electronics.
Signature · 1 line
1.7.9.5
PATCH 13/17 clocksource/cadence_ttc: Call clockevents_update_freq() with IRQs enabled
In reply to Daniel LezcanoFrom: Soren Brinkmann <[email protected]>
The timer core takes care of serialization and IRQs. Hence the driver is no longer required to disable interrupts when calling clockevents_update_freq().
--- drivers/clocksource/cadence_ttc_timer.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-)
drivers/clocksource/cadence_ttc_timer.c +2 -15
@@ -321,25 +321,12 @@ static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,switch (event) {case POST_RATE_CHANGE : - { -unsigned long flags; - -/* -* clockevents_update_freq should be called with IRQ disabled on -* the CPU the timer provides events for. The timer we use is -* common to both CPUs, not sure if we need to run on both -* cores. -*/ -local_irq_save (flags); -clockevents_update_freq (&ttcce->ce, - ndata->new_rate /PRESCALE ); -local_irq_restore (flags); -/* update cached frequency */ ttc->freq = ndata->new_rate; +clockevents_update_freq (&ttcce->ce, ndata->new_rate /PRESCALE ); +/* fall through */ - }case PRE_RATE_CHANGE :case ABORT_RATE_CHANGE :default :
Signature · 1 line
1.7.9.5
PATCH 14/17 clocksource/cadence_ttc: Overhaul clocksource frequency adjustment
In reply to Daniel LezcanoFrom: Soren Brinkmann <[email protected]>
The currently used method adjusting the clocksource to a changing input frequency does not work on kernels from 3.11 on.
The new approach is to keep the timer frequency as constant as possible. I.e.
- due to the TTC's prescaler limitations, allow frequency changes only if the frequency scales by a power of 2
- adjust the counter's divider on the fly when a frequency change occurs
This limits cpufreq to scale by certain factors only.
But we may keep the time base somewhat constant, so that sleep() & co keep working as expected, while supporting cpufreq.
--- drivers/clocksource/cadence_ttc_timer.c | 104 +++++++++++++++++++++++++------ 1 file changed, 84 insertions(+), 20 deletions(-)
drivers/clocksource/cadence_ttc_timer.c +84 -20
@@ -16,6 +16,7 @@*/ #include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/interrupt.h> #include <linux/clockchips.h> #include <linux/of_address.h>
@@ -52,6 +53,8 @@#define TTC_CNT_CNTRL_DISABLE_MASK 0x1#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5)/* clock source */ +#define TTC_CLK_CNTRL_PSV_MASK 0x1e +#define TTC_CLK_CNTRL_PSV_SHIFT 1/* * Setup the timers to use pre-scaling, using a fixed value for now that will
@@ -63,6 +66,8 @@#define CLK_CNTRL_PRESCALE_EN 1#define CNT_CNTRL_RESET (1 << 4) +#define MAX_F_ERR 50 +/** * struct ttc_timer - This definition defines local timer structure *
@@ -82,6 +87,8 @@ struct ttc_timer { container_of(x, struct ttc_timer, clk_rate_change_nb)struct ttc_timer_clocksource { +u32 scale_clk_ctrl_reg_old; +u32 scale_clk_ctrl_reg_new;struct ttc_timer ttc;struct clocksource cs; };
@@ -229,32 +236,89 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, struct ttc_timer_clocksource, ttc);switch (event) { -case POST_RATE_CHANGE : +case PRE_RATE_CHANGE : + { +u32 psv; +unsigned long factor, rate_low, rate_high; + +if (ndata->new_rate > ndata->old_rate) { + factor =DIV_ROUND_CLOSEST (ndata->new_rate, + ndata->old_rate); + rate_low = ndata->old_rate; + rate_high = ndata->new_rate; + }else { + factor =DIV_ROUND_CLOSEST (ndata->old_rate, + ndata->new_rate); + rate_low = ndata->new_rate; + rate_high = ndata->old_rate; + } + +if (!is_power_of_2 (factor)) +return NOTIFY_BAD ; + +if (abs (rate_high - (factor * rate_low)) >MAX_F_ERR ) +return NOTIFY_BAD ; + + factor =__ilog2_u32 (factor); +/* -* Do whatever is necessary to maintain a proper time base -* -* I cannot find a way to adjust the currently used clocksource -* to the new frequency. __clocksource_updatefreq_hz() sounds -* good, but does not work. Not sure what's that missing. -* -* This approach works, but triggers two clocksource switches. -* The first after unregister to clocksource jiffies. And -* another one after the register to the newly registered timer. -* -* Alternatively we could 'waste' another HW timer to ping pong -* between clock sources. That would also use one register and -* one unregister call, but only trigger one clocksource switch -* for the cost of another HW timer used by the OS. +* store timer clock ctrl register so we can restore it in case +* of an abort. */ -clocksource_unregister (&ttccs->cs); -clocksource_register_hz (&ttccs->cs, - ndata->new_rate /PRESCALE ); -/* fall through */ -case PRE_RATE_CHANGE : + ttccs->scale_clk_ctrl_reg_old = +__raw_readl (ttccs->ttc.base_addr + +TTC_CLK_CNTRL_OFFSET ); + + psv = (ttccs->scale_clk_ctrl_reg_old & +TTC_CLK_CNTRL_PSV_MASK ) >> +TTC_CLK_CNTRL_PSV_SHIFT ; +if (ndata->new_rate < ndata->old_rate) + psv -= factor; +else + psv += factor; + +/* prescaler within legal range? */ +if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >>TTC_CLK_CNTRL_PSV_SHIFT )) +return NOTIFY_BAD ; + + ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old & + ~TTC_CLK_CNTRL_PSV_MASK ; + ttccs->scale_clk_ctrl_reg_new |= psv <<TTC_CLK_CNTRL_PSV_SHIFT ; + + +/* scale down: adjust divider in post-change notification */ +if (ndata->new_rate < ndata->old_rate) +return NOTIFY_DONE ; + +/* scale up: adjust divider now - before frequency change */ +__raw_writel (ttccs->scale_clk_ctrl_reg_new, + ttccs->ttc.base_addr +TTC_CLK_CNTRL_OFFSET ); +break ; + } +case POST_RATE_CHANGE : +/* scale up: pre-change notification did the adjustment */ +if (ndata->new_rate > ndata->old_rate) +return NOTIFY_OK ; + +/* scale down: adjust divider now - after frequency change */ +__raw_writel (ttccs->scale_clk_ctrl_reg_new, + ttccs->ttc.base_addr +TTC_CLK_CNTRL_OFFSET ); +break ; +case ABORT_RATE_CHANGE : +/* we have to undo the adjustment in case we scale up */ +if (ndata->new_rate < ndata->old_rate) +return NOTIFY_OK ; + +/* restore original register value */ +__raw_writel (ttccs->scale_clk_ctrl_reg_old, + ttccs->ttc.base_addr +TTC_CLK_CNTRL_OFFSET ); +/* fall through */ default :return NOTIFY_DONE ; } + +return NOTIFY_DONE ; }static void __init ttc_setup_clocksource (struct clk *clk,void __iomem *base)
Signature · 1 line
1.7.9.5
PATCH 15/17 arm: zynq: Don't use arm_global_timer with cpufreq
In reply to Daniel LezcanoFrom: Soren Brinkmann <[email protected]>
The timer frequency of the arm_global_timer depends on the CPU frequency. With cpufreq altering that frequency the arm_global_timer does not maintain a stable time base. Therefore don't enable that timer in case cpufreq is enabled.
--- arch/arm/mach-zynq/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-zynq/Kconfig +1 -1
@@ -13,6 +13,6 @@ config ARCH_ZYNQ select HAVE_SMP select SPARSE_IRQ select CADENCE_TTC_TIMER - select ARM_GLOBAL_TIMER + select ARM_GLOBAL_TIMER if !CPU_FREQ help Support for Xilinx Zynq ARM Cortex A9 Platform
Signature · 1 line
1.7.9.5
PATCH 16/17 arm: zynq: Add support for cpufreq
In reply to Daniel LezcanoFrom: Soren Brinkmann <[email protected]>
The generic cpufreq-cpu0 driver can scale the CPU frequency on Zynq SOCs. Add the required platform device to the BSP and appropriate OPPs to the dts.
--- arch/arm/boot/dts/zynq-7000.dtsi | 6 ++++++ arch/arm/mach-zynq/Kconfig | 2 ++ arch/arm/mach-zynq/common.c | 3 +++ 3 files changed, 11 insertions(+)
arch/arm/boot/dts/zynq-7000.dtsi +6 -0
@@ -24,6 +24,12 @@ device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + 222223 1000000 + >; }; cpu@1 {
arch/arm/mach-zynq/Kconfig +2 -0
@@ -2,6 +2,8 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7 select ARM_AMBA select ARM_GIC + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS
arch/arm/mach-zynq/common.c +3 -0
@@ -51,6 +51,8 @@ static struct platform_device zynq_cpuidle_device = {*/ static void __init zynq_init_machine (void ) { +struct platform_device_info devinfo = { .name ="cpufreq-cpu0" , }; +/* * 64KB way size, 8-way associativity, parity disabled */
@@ -59,6 +61,7 @@ static void __init zynq_init_machine(void)of_platform_populate (NULL , of_default_bus_match_table,NULL ,NULL );platform_device_register (&zynq_cpuidle_device); +platform_device_register_full (&devinfo); }static void __init zynq_timer_init (void )
Signature · 1 line
1.7.9.5
PATCH 17/17 clocksource: exynos_mct: silence a static checker warning
In reply to Daniel LezcanoFrom: Dan Carpenter <[email protected]>
My guess is we aren't going to have a 2 digit cpuid here any time soon but the static checkers don't know that and complain that the snprintf() could overflow.
--- drivers/clocksource/exynos_mct.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clocksource/exynos_mct.c +1 -1
@@ -410,7 +410,7 @@ static int exynos4_local_timer_setup(struct clock_event_device *evt) mevt = container_of(evt, struct mct_clock_event_device, evt); mevt->base =EXYNOS4_MCT_L_BASE (cpu); -sprintf (mevt->name,"mct_tick%d" , cpu); +snprintf (mevt->name,sizeof (mevt->name),"mct_tick%d" , cpu); evt->name = mevt->name; evt->cpumask =cpumask_of (cpu);
Signature · 1 line
1.7.9.5