arm64: add new support Samsung GH7 SoC and SSDK board
Subsystems (4)
v2 cover arm64: add new support Samsung GH7 SoC and SSDK board
This adds support for Samsung ARMv8 core based GH7 SoC and its evaluation SSDK board.
Changes since v1:
- remove model and compatible in dtsi
- remove inclusion /dts-v1/ in dtsi
- add aliase for serial0
- remove compatible cortex-a9-gic for gic
- remove clock-frequncy for timer
- change number of address-cells and size-cells to 2
- enable ARCH_GH7 in single defconfig for arm64
There were many comments for SoC vendor's Kconfig entry but now I have no choice except adding ARCH_GH7 and enabling it in current single defconfig for arm64 by default.
[PATCH v2 1/3] arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board [PATCH v2 2/3] arm64: defconfig: Enable ARCH_GH7 by default
[PATCH v2 3/3] Documentation: DT: add new entry for Samsung GH7 SoC and SSDK board
PATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
--- arch/arm64/boot/dts/samsung-gh7.dtsi | 106 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/samsung-ssdk-gh7.dts | 26 ++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm64/boot/dts/samsung-gh7.dtsi create mode 100644 arch/arm64/boot/dts/samsung-ssdk-gh7.dts
arch/arm64/boot/dts/samsung-gh7.dtsi new file +106 -0
@@ -0,0 +1,106 @@ +/* + * SAMSUNG GH7 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/memreserve/ 0x80000000 0x0C400000; + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = "/amba/uart at 12c00000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu at 000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 003 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + gic: interrupt-controller at 1C000000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1C001000 0 0x1000>, /* GIC Dist */ + <0x0 0x1C002000 0 0x1000>, /* GIC CPU */ + <0x0 0x1C004000 0 0x2000>, /* GIC VCPU Control */ + <0x0 0x1C006000 0 0x2000>; /* GIC VCPU */ + interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, /* Secure Phys IRQ */ + <1 14 0xff01>, /* Non-secure Phys IRQ */ + <1 11 0xff01>, /* Virt IRQ */ + <1 10 0xff01>; /* Hyp IRQ */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 294 0>, + <0 295 0>, + <0 296 0>, + <0 297 0>, + <0 298 0>, + <0 299 0>, + <0 300 0>, + <0 301 0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial at 12c00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c00000 0 0x10000>; + interrupts = <0 418 0>; + }; + + serial at 12c20000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c20000 0 0x10000>; + interrupts = <0 420 0>; + }; + }; +};
arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +26 -0
@@ -0,0 +1,26 @@ +/* + * SAMSUNG SSDK-GH7 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "samsung-gh7.dtsi" + +/ { + model = "SAMSUNG SSDK-GH7 board based on GH7 SoC"; + compatible = "samsung,ssdk-gh7", "samsung,gh7"; + + chosen { + }; + + memory at 80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + }; +};
Signature · 1 line
1.8.2.1.339.g52a3e01
Catalin Marinas
maintainerPATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
Quoted 3 lines · Kukjin Kim
Signed-off-by Kukjin Kim <[email protected]>Reviewed-by Thomas Abraham <[email protected]>Cc Catalin Marinas <[email protected]>
This patch should go to the devicetree list as well to get some reviews/acks from the DT maintainers.
Signature · 1 line
Catalin
Mark Rutland
reviewerPATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
In reply to Kukjin KimQuoted 18 lines · Kukjin Kim
Signed-off-by Kukjin Kim <[email protected]>Reviewed-by Thomas Abraham <[email protected]>Cc Catalin Marinas <[email protected]>--- arch/arm64/boot/dts/samsung-gh7.dtsi | 106 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/samsung-ssdk-gh7.dts | 26 ++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm64/boot/dts/samsung-gh7.dtsi create mode 100644 arch/arm64/boot/dts/samsung-ssdk-gh7.dtsarch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0@@ -0,0 +1,106 @@ +/* + * SAMSUNG GH7 SoC device tree source
arch/arm64/boot/dts/samsung-gh7.dtsi line 12
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +10
-0+ * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/memreserve/ 0x80000000 0x0C400000;
Please have a comment as to what this memreserve is intended to protect. This is very large, and we don't want pointless memreserves.
What address does the kernel end up getting loaded at on this board?
Quoted 7 lines
arch/arm64/boot/dts/samsung-gh7.dtsi new file +7
-0+ +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases {
arch/arm64/boot/dts/samsung-gh7.dtsi line 29
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +10
-0+ serial0 = "/amba/uart at 12c00000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu at 000 { + device_type = "cpu"; + compatible = "arm,armv8";
The "arm,armv8" should be a fallback rather than the only entry. The precise core should be first (see arch/arm64/boot/dts/apm-storm.dtsi for an example).
arch/arm64/boot/dts/samsung-gh7.dtsi line 30
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +1
-0+ reg = <0x0 0x000>;
Any reason for padding these to three hexadecimal digits (in both the reg and unit-address)?
Quoted 18 lines
arch/arm64/boot/dts/samsung-gh7.dtsi new file +18
-0+ enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 003 {
arch/arm64/boot/dts/samsung-gh7.dtsi line 58
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +10
-0+ device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + gic: interrupt-controller at 1C000000 { + compatible = "arm,cortex-a15-gic";
We should have a more specific compatible string early in the list here too.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +9
-0+ #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1C001000 0 0x1000>, /* GIC Dist */ + <0x0 0x1C002000 0 0x1000>, /* GIC CPU */ + <0x0 0x1C004000 0 0x2000>, /* GIC VCPU Control */ + <0x0 0x1C006000 0 0x2000>; /* GIC VCPU */ + interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ + }; +
arch/arm64/boot/dts/samsung-gh7.dtsi line 77
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +10
-0+ timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, /* Secure Phys IRQ */ + <1 14 0xff01>, /* Non-secure Phys IRQ */ + <1 11 0xff01>, /* Virt IRQ */ + <1 10 0xff01>; /* Hyp IRQ */ + }; + + pmu { + compatible = "arm,armv8-pmuv3";
This is missing a specific compatible string.
arch/arm64/boot/dts/samsung-gh7.dtsi line 86
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +9
-0+ interrupts = <0 294 0>, + <0 295 0>, + <0 296 0>, + <0 297 0>, + <0 298 0>, + <0 299 0>, + <0 300 0>, + <0 301 0>; + };
There are four CPUs described, yet eight interrupts here. There should be one per CPU.
Quoted 8 lines
arch/arm64/boot/dts/samsung-gh7.dtsi new file +8
-0+ + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial at 12c00000 {
arch/arm64/boot/dts/samsung-gh7.dtsi line 104
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +10
-0+ compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c00000 0 0x10000>; + interrupts = <0 418 0>; + }; + + serial at 12c20000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c20000 0 0x10000>; + interrupts = <0 420 0>; + };
These are both missing required clocks.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ }; +};arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +6
-0@@ -0,0 +1,26 @@ +/* + * SAMSUNG SSDK-GH7 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + *
arch/arm64/boot/dts/samsung-ssdk-gh7.dts line 16
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +10
-0+ * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "samsung-gh7.dtsi" + +/ { + model = "SAMSUNG SSDK-GH7 board based on GH7 SoC";
Is the "based on GH7 SoC" part necessary? Does the "SSDK-GH7" not give that away?
Thanks,
Mark.
PATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
Quoted 1 line · Mark Rutland
Hi Mark,
Quoted 26 lines · Kukjin Kim
Quoted 5 lines
Signed-off-by Kukjin Kim <[email protected]>Reviewed-by Thomas Abraham <[email protected]>Cc Catalin Marinas <[email protected]>--- arch/arm64/boot/dts/samsung-gh7.dtsi | 106+++++++++++++++++++++++++++++++
Review
Quoted 6 lines
arch/arm64/boot/dts/samsung-ssdk-gh7.dts | 26 ++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm64/boot/dts/samsung-gh7.dtsi create mode 100644 arch/arm64/boot/dts/samsung-ssdk-gh7.dts(quoted diff) +0
-0
b/arch/arm64/boot/dts/samsung-gh7.dtsiQuoted 12 lines
new file mode 100644
index 0000000..b5e8488arch/arm64/boot/dts/samsung-gh7.dtsi new file +7
-0@@ -0,0 +1,106 @@ +/* + * SAMSUNG GH7 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify
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arch/arm64/boot/dts/samsung-gh7.dtsi line 12
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/memreserve/ 0x80000000 0x0C400000;Please have a comment as to what this memreserve is intended to protect. This is very large, and we don't want pointless memreserves.
Well, you mean I need to comment about each reserved memory area?
We need the reserved memory for EL3 monitor, UEFI services, secure interpreter, hypervisor and Scan-chain for debug...BTW isn't it depending on each hardware platform and usage model?
Just note, I will change the reserve memory area and size. From at 0xf8000000 and size is 128MB(0x8000000).
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What address does the kernel end up getting loaded at on this board?
We load the kernel image from at 0x80080000 after changing the reserve memory area.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +13
-0+ +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = "/amba/uart at 12c00000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>;
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arch/arm64/boot/dts/samsung-gh7.dtsi line 29
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +4
-0+ + cpu at 000 { + device_type = "cpu"; + compatible = "arm,armv8";The "arm,armv8" should be a fallback rather than the only entry. The precise core should be first (see
arch/arm64/boot/dts/apm-storm.dtsifor an example).
Well, do I really need another name if GH7 has just 'ARMv8 core' exactly?
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arch/arm64/boot/dts/samsung-gh7.dtsi line 30
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +1
-0+ reg = <0x0 0x000>;Any reason for padding these to three hexadecimal digits (in both the reg and unit-address)?
Yes, I already commented on Olof's question before, other cores will be added and it should be separated from this.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +23
-0+ enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 003 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>;
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arch/arm64/boot/dts/samsung-gh7.dtsi line 58
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ }; + }; + + gic: interrupt-controller at 1C000000 { + compatible = "arm,cortex-a15-gic";We should have a more specific compatible string early in the list here too.
Well, I think more specific compatible string is not required for gic, there were discussion about using another compatible string for gic-v2. And cortex-a15-gic should be fine at this moment and if another name is required as per previous discussion, we will then.
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arch/arm64/boot/dts/samsung-gh7.dtsi
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1C001000 0 0x1000>, /* GIC Dist */ + <0x0 0x1C002000 0 0x1000>, /* GIC CPU */ + <0x0 0x1C004000 0 0x2000>, /* GIC VCPU Control
*/
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +8
-0+ <0x0 0x1C006000 0 0x2000>; /* GIC VCPU */ + interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, /* Secure Phys IRQ */ + <1 14 0xff01>, /* Non-secure Phys IRQ */
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arch/arm64/boot/dts/samsung-gh7.dtsi line 77
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +6
-0+ <1 11 0xff01>, /* Virt IRQ */ + <1 10 0xff01>; /* Hyp IRQ */ + }; + + pmu { + compatible = "arm,armv8-pmuv3";This is missing a specific compatible string.
I don't know why I need another specific compatible string here because I thought the 'armv8-pmuv3' is enough.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +4
-0+ interrupts = <0 294 0>, + <0 295 0>, + <0 296 0>, + <0 297 0>,
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arch/arm64/boot/dts/samsung-gh7.dtsi line 86
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ <0 298 0>, + <0 299 0>, + <0 300 0>, + <0 301 0>; + };There are four CPUs described, yet eight interrupts here. There should be one per CPU.
Yes right. I added them here by mistake, the other four interrupts will be used for other 4 cores will be added later though.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +12
-0+ + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial at 12c00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c00000 0 0x10000>; + interrupts = <0 418 0>; + };
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arch/arm64/boot/dts/samsung-gh7.dtsi line 104
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +6
-0+ + serial at 12c20000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c20000 0 0x10000>; + interrupts = <0 420 0>; + };These are both missing required clocks.
Yes right.
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Review
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ }; +};(quoted diff) +0
-0
b/arch/arm64/boot/dts/samsung-ssdk-gh7.dtsQuoted 16 lines
new file mode 100644
index 0000000..47afbc4arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +11
-0@@ -0,0 +1,26 @@ +/* + * SAMSUNG SSDK-GH7 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts line 16
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +5
-0+/dts-v1/; +#include "samsung-gh7.dtsi" + +/ { + model = "SAMSUNG SSDK-GH7 board based on GH7 SoC";Is the "based on GH7 SoC" part necessary? Does the "SSDK-GH7" not give that away?
In this case, yes, SSDK-GH7 is enough but I though, in case of different board adding what SoC is used on the board in that is useful. Anyway, OK.
Thanks,
Kukjin
Mark Rutland
reviewerPATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
Quoted 39 lines · Kukjin Kim
Quoted 1 line · Mark Rutland
Hi Mark,
Quoted 26 lines · Kukjin Kim
Quoted 5 lines
Signed-off-by Kukjin Kim <[email protected]>Reviewed-by Thomas Abraham <[email protected]>Cc Catalin Marinas <[email protected]>--- arch/arm64/boot/dts/samsung-gh7.dtsi | 106+++++++++++++++++++++++++++++++
Review
Quoted 6 lines
arch/arm64/boot/dts/samsung-ssdk-gh7.dts | 26 ++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm64/boot/dts/samsung-gh7.dtsi create mode 100644 arch/arm64/boot/dts/samsung-ssdk-gh7.dts(quoted diff) +0
-0
b/arch/arm64/boot/dts/samsung-gh7.dtsiQuoted 12 lines
new file mode 100644
index 0000000..b5e8488arch/arm64/boot/dts/samsung-gh7.dtsi new file +7
-0@@ -0,0 +1,106 @@ +/* + * SAMSUNG GH7 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modifyQuoted 9 lines
arch/arm64/boot/dts/samsung-gh7.dtsi line 12
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/memreserve/ 0x80000000 0x0C400000;Please have a comment as to what this memreserve is intended to protect. This is very large, and we don't want pointless memreserves.
Quoted 1 line
Well, you mean I need to comment about each reserved memory area?
Please have a comment about what each /memreserve/ is intended to protect.
Quoted 3 lines
We need the reserved memory for EL3 monitor, UEFI services, secure interpreter, hypervisor and Scan-chain for debug...BTW isn't it depending on each hardware platform and usage model?
If it depends on each particular model then it doesn't belong in the shared dtsi, and each dts should have the /memreserve/ for that platform.
Why would the hypervisor or secure OS memory ever be accessible to the kernel such that it would require a memreserve? That sounds fundamentally broken.
I was under the impression that if using UEFI we can identify and reserve the UEFI services by walking to UEFI memory map. If we don't use them, they don't need to be protected. As such, I don't see why they need a memreserve for them.
Quoted 2 lines
Just note, I will change the reserve memory area and size. From at
0xf8000000and size is 128MB(0x8000000).
Ok.
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What address does the kernel end up getting loaded at on this board?
We load the kernel image from at
0x80080000after changing the reserve memory area.
Ok.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +12
-0+/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = "/amba/uart at 12c00000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>;Quoted 9 lines
arch/arm64/boot/dts/samsung-gh7.dtsi line 29
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +4
-0+ + cpu at 000 { + device_type = "cpu"; + compatible = "arm,armv8";The "arm,armv8" should be a fallback rather than the only entry. The precise core should be first (see
arch/arm64/boot/dts/apm-storm.dtsifor an example).
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Well, do I really need another name if GH7 has just 'ARMv8 core' exactly?
Yes please. You presumably don't have "just 'ARMv8 core'", but rather a specific ARMv8 implementation.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 30
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +1
-0+ reg = <0x0 0x000>;Any reason for padding these to three hexadecimal digits (in both the reg and unit-address)?
Yes, I already commented on Olof's question before, other cores will be added and it should be separated from this.
Ok.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +23
-0+ enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu at 003 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>;Quoted 9 lines
arch/arm64/boot/dts/samsung-gh7.dtsi line 58
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ }; + }; + + gic: interrupt-controller at 1C000000 { + compatible = "arm,cortex-a15-gic";We should have a more specific compatible string early in the list here too.
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Well, I think more specific compatible string is not required for gic, there were discussion about using another compatible string for gic-v2. And cortex-a15-gic should be fine at this moment and if another name is required as per previous discussion, we will then.
While it's probably ok to have "arm,cortex-a15-gic" in the compatible list, it would be good to also have a more specific string, so we can identify the GIC implementation precisely in future (in case we need to perform any workarounds, or there's some kind of optimisation we could perform for some implementations).
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arch/arm64/boot/dts/samsung-gh7.dtsi
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1C001000 0 0x1000>, /* GIC Dist */ + <0x0 0x1C002000 0 0x1000>, /* GIC CPU */ + <0x0 0x1C004000 0 0x2000>, /* GIC VCPU Control*/
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +8
-0+ <0x0 0x1C006000 0 0x2000>; /* GIC VCPU */ + interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, /* Secure Phys IRQ */ + <1 14 0xff01>, /* Non-secure Phys IRQ */Quoted 9 lines
arch/arm64/boot/dts/samsung-gh7.dtsi line 77
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +6
-0+ <1 11 0xff01>, /* Virt IRQ */ + <1 10 0xff01>; /* Hyp IRQ */ + }; + + pmu { + compatible = "arm,armv8-pmuv3";This is missing a specific compatible string.
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I don't know why I need another specific compatible string here because I thought the 'armv8-pmuv3' is enough.
Each CPU microarchitecture has different PMU events and quirks. While the CPU PMU might be compatible with ARMv8's PMUv3, it will also have implementation-specific events, and may have quirks we need to work around in future.
As with 32-bit, we'd expect these to be of the form "${implementor},${cpu}-pmu".
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +4
-0+ interrupts = <0 294 0>, + <0 295 0>, + <0 296 0>, + <0 297 0>,Quoted 9 lines
arch/arm64/boot/dts/samsung-gh7.dtsi line 86
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ <0 298 0>, + <0 299 0>, + <0 300 0>, + <0 301 0>; + };There are four CPUs described, yet eight interrupts here. There should be one per CPU.
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Yes right. I added them here by mistake, the other four interrupts will be used for other 4 cores will be added later though.
Ok.
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +11
-0+ amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial at 12c00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c00000 0 0x10000>; + interrupts = <0 418 0>; + };Quoted 9 lines
arch/arm64/boot/dts/samsung-gh7.dtsi line 104
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +6
-0+ + serial at 12c20000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c20000 0 0x10000>; + interrupts = <0 420 0>; + };These are both missing required clocks.
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Yes right.
So you'll add these?
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Review
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b/arch/arm64/boot/dts/samsung-ssdk-gh7.dtsQuoted 16 lines
new file mode 100644
index 0000000..47afbc4arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +11
-0@@ -0,0 +1,26 @@ +/* + * SAMSUNG SSDK-GH7 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +Quoted 9 lines
arch/arm64/boot/dts/samsung-ssdk-gh7.dts line 16
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +5
-0+/dts-v1/; +#include "samsung-gh7.dtsi" + +/ { + model = "SAMSUNG SSDK-GH7 board based on GH7 SoC";Is the "based on GH7 SoC" part necessary? Does the "SSDK-GH7" not give that away?
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In this case, yes, SSDK-GH7 is enough but I though, in case of different board adding what SoC is used on the board in that is useful. Anyway, OK.
Looking at ePAPR, the recommended format is "manufacturer,model", and the string is intended to identify a particular implementation. It is not intended to give details about the implementation that can be derived from the name.
We seem to have ignored the format (and to some degree purpose) of the model property so far, but I don't see any reason to fill it with unnecessary information.
Thanks,
Mark.
PATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
Quoted 1 line · Mark Rutland
[...]
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+/memreserve/
0x800000000x0C400000;Please have a comment as to what this memreserve is intended to protect. This is very large, and we don't want pointless memreserves.
Well, you mean I need to comment about each reserved memory area?
Please have a comment about what each /memreserve/ is intended to protect.
OK and I will try to reduce the size of reserved memory.
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We need the reserved memory for EL3 monitor, UEFI services, secure interpreter, hypervisor and Scan-chain for debug...BTW isn't it depending on each hardware platform and usage model?
If it depends on each particular model then it doesn't belong in the shared dtsi, and each dts should have the /memreserve/ for that platform.
I mean it depends on each SoC not board :-)
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Why would the hypervisor or secure OS memory ever be accessible to the kernel such that it would require a memreserve? That sounds fundamentally broken.
I was under the impression that if using UEFI we can identify and reserve the UEFI services by walking to UEFI memory map. If we don't use them, they don't need to be protected. As such, I don't see why they need a memreserve for them.
I need to talk to regarding engineer internally. Then I will update it.
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Just note, I will change the reserve memory area and size. From at
0xf8000000and size is 128MB(0x8000000).Ok.
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What address does the kernel end up getting loaded at on this board?
We load the kernel image from at
0x80080000after changing the reserve memory area.Ok.
[...]
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arch/arm64/boot/dts/samsung-gh7.dtsi line 29
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +3
-0+ cpu at 000 { + device_type = "cpu"; + compatible = "arm,armv8";The "arm,armv8" should be a fallback rather than the only entry. The precise core should be first (see
arch/arm64/boot/dts/apm-storm.dtsifor an example).
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Well, do I really need another name if GH7 has just 'ARMv8 core' exactly?
Yes please. You presumably don't have "just 'ARMv8 core'", but rather a specific ARMv8 implementation.
OK, so in my understanding if it is really _just_ 'ARMv8 core' from S/W point of view, "arm,armv8" should be fine. I will make sure.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 30
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +1
-0+ reg = <0x0 0x000>;Any reason for padding these to three hexadecimal digits (in both the reg and unit-address)?
Yes, I already commented on Olof's question before, other cores will be added and it should be separated from this.
Ok.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 58
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ gic: interrupt-controller at 1C000000 { + compatible = "arm,cortex-a15-gic";We should have a more specific compatible string early in the list here too.
Well, I think more specific compatible string is not required for gic, there were discussion about using another compatible string for gic-v2. And cortex-a15-gic should be fine at this moment and if another name is required as per previous discussion, we will then.
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While it's probably ok to have "arm,cortex-a15-gic" in the compatible list, it would be good to also have a more specific string, so we can identify the GIC implementation precisely in future (in case we need to perform any workarounds, or there's some kind of optimisation we could perform for some implementations).
Hmm... let's use just it for now then add another specific string later ;-)
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arch/arm64/boot/dts/samsung-gh7.dtsi line 77
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ pmu { + compatible = "arm,armv8-pmuv3";This is missing a specific compatible string.
I don't know why I need another specific compatible string here because I thought the 'armv8-pmuv3' is enough.
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Each CPU microarchitecture has different PMU events and quirks. While the CPU PMU might be compatible with ARMv8's PMUv3, it will also have implementation-specific events, and may have quirks we need to work around in future.
As with 32-bit, we'd expect these to be of the form "${implementor},${cpu}-pmu".
OK.
+ compatible = "samsung,gh7-pmu", "armv8-pmuv3";
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +4
-0+ interrupts = <0 294 0>, + <0 295 0>, + <0 296 0>, + <0 297 0>,Quoted 9 lines
arch/arm64/boot/dts/samsung-gh7.dtsi line 86
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ <0 298 0>, + <0 299 0>, + <0 300 0>, + <0 301 0>; + };There are four CPUs described, yet eight interrupts here. There should be one per CPU.
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Yes right. I added them here by mistake, the other four interrupts will be used for other 4 cores will be added later though.
Ok.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 104
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ serial at 12c20000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c20000 0 0x10000>; + interrupts = <0 420 0>; + };These are both missing required clocks.
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Yes right.
So you'll add these?
To be honest, still I'm not sure how it should be handled because regarding clocks do not need to handle in the kernel for GH7. And for it, I needed to use some HACKs to change clock handling in the kernel. I will provide proper solution soon.
[...]
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts line 16
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +1
-0+ model = "SAMSUNG SSDK-GH7 board based on GH7 SoC";Is the "based on GH7 SoC" part necessary? Does the "SSDK-GH7" not give that away?
In this case, yes, SSDK-GH7 is enough but I though, in case of different board adding what SoC is used on the board in that is useful. Anyway, OK.
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Looking at ePAPR, the recommended format is "manufacturer,model", and the string is intended to identify a particular implementation. It is not intended to give details about the implementation that can be derived from the name.
We seem to have ignored the format (and to some degree purpose) of the model property so far, but I don't see any reason to fill it with unnecessary information.
OK, agreed. So it should be:
+ model = "samsung,SSDK-GH7";
Thank,
Kukjin
Mark Rutland
reviewerPATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
Quoted 8 lines · Kukjin Kim
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arch/arm64/boot/dts/samsung-gh7.dtsi line 29
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +3
-0+ cpu at 000 { + device_type = "cpu"; + compatible = "arm,armv8";The "arm,armv8" should be a fallback rather than the only entry. The precise core should be first (see
arch/arm64/boot/dts/apm-storm.dtsifor an example).
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Well, do I really need another name if GH7 has just 'ARMv8 core' exactly?
Yes please. You presumably don't have "just 'ARMv8 core'", but rather a specific ARMv8 implementation.
OK, so in my understanding if it is really _just_ 'ARMv8 core' from S/W point of view, "arm,armv8" should be fine. I will make sure.
It will work, sure. But the compatible list should also list the specific CPU. From the S/W point of view there are likely implementation-defined registers which mean that no real CPU will be "just" an ARMv8 core.
We have enough trouble with DTBs for 32-bit SoCs not listing things they should. I see no reason to be lax here.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 58
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ gic: interrupt-controller at 1C000000 { + compatible = "arm,cortex-a15-gic";We should have a more specific compatible string early in the list here too.
Well, I think more specific compatible string is not required for gic, there were discussion about using another compatible string for gic-v2. And cortex-a15-gic should be fine at this moment and if another name is required as per previous discussion, we will then.
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While it's probably ok to have "arm,cortex-a15-gic" in the compatible list, it would be good to also have a more specific string, so we can identify the GIC implementation precisely in future (in case we need to perform any workarounds, or there's some kind of optimisation we could perform for some implementations).
Hmm... let's use just it for now then add another specific string later ;-)
Why not do this from the start? Then we can actually rely on the DTB rather than it being useless.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 77
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ pmu { + compatible = "arm,armv8-pmuv3";This is missing a specific compatible string.
I don't know why I need another specific compatible string here because I thought the 'armv8-pmuv3' is enough.
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Each CPU microarchitecture has different PMU events and quirks. While the CPU PMU might be compatible with ARMv8's PMUv3, it will also have implementation-specific events, and may have quirks we need to work around in future.
As with 32-bit, we'd expect these to be of the form "${implementor},${cpu}-pmu".
OK.
Review
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-0+ compatible = "samsung,gh7-pmu", "armv8-pmuv3";
Is GH7 an SoC or a CPU?
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arch/arm64/boot/dts/samsung-gh7.dtsi line 104
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ serial at 12c20000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c20000 0 0x10000>; + interrupts = <0 420 0>; + };These are both missing required clocks.
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Yes right.
So you'll add these?
To be honest, still I'm not sure how it should be handled because regarding clocks do not need to handle in the kernel for GH7. And for it, I needed to use some HACKs to change clock handling in the kernel. I will provide proper solution soon.
Are the clocks always-on, fixed-rate clocks, or does some firmware manage them dynamically? We have bindings for the former.
There's not much point having a DTS upstream that relies on hacks which are not.
Cheers,
Mark.
PATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
Quoted 15 lines · Mark Rutland
Quoted 13 lines · Kukjin Kim
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arch/arm64/boot/dts/samsung-gh7.dtsi line 29
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +3
-0+ cpu at 000 { + device_type = "cpu"; + compatible = "arm,armv8";The "arm,armv8" should be a fallback rather than the only entry. The precise core should be first (see
arch/arm64/boot/dts/apm-storm.dtsifor an example).Well, do I really need another name if GH7 has just 'ARMv8 core' exactly?
Yes please. You presumably don't have "just 'ARMv8 core'", but rather a specific ARMv8 implementation.
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OK, so in my understanding if it is really _just_ 'ARMv8 core' from S/W point of view, "arm,armv8" should be fine. I will make sure.
It will work, sure. But the compatible list should also list the specific CPU. From the S/W point of view there are likely implementation-defined registers which mean that no real CPU will be "just" an ARMv8 core.
Well, IMHO, SoC is just SoC and we don't think each CPU(core) from SoC and I'm still wondering why the specific compatible string for CPU is needed in kernel. And I don't see any custom handling for GH7 SoC. Note sorry, I don't get about implementation-defined registers.
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We have enough trouble with DTBs for 32-bit SoCs not listing things they should. I see no reason to be lax here.
Could you please let me know what was the problem? If it could be on exynos, would be helpful to me.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 58
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ gic: interrupt-controller at 1C000000 { + compatible = "arm,cortex-a15-gic";We should have a more specific compatible string early in the list here too.
Well, I think more specific compatible string is not required for gic, there were discussion about using another compatible string for gic-v2. And cortex-a15-gic should be fine at this moment and if another name is required as per previous discussion, we will then.
While it's probably ok to have "arm,cortex-a15-gic" in the compatible list, it would be good to also have a more specific string, so we can identify the GIC implementation precisely in future (in case we need to perform any workarounds, or there's some kind of optimisation we could perform for some implementations).
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Hmm... let's use just it for now then add another specific string later ;-)
Why not do this from the start? Then we can actually rely on the DTB rather than it being useless.
I mean, we need to use current GIC implementation for GH7 SoC at this moment.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 77
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +2
-0+ pmu { + compatible = "arm,armv8-pmuv3";This is missing a specific compatible string.
I don't know why I need another specific compatible string here because I thought the 'armv8-pmuv3' is enough.
Each CPU microarchitecture has different PMU events and quirks. While the CPU PMU might be compatible with ARMv8's PMUv3, it will also have implementation-specific events, and may have quirks we need to work around in future.
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Review
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As with 32-bit, we'd expect these to be of the form "${implementor},${cpu}-pmu".
OK.
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-0+ compatible = "samsung,gh7-pmu", "armv8-pmuv3";Is GH7 an SoC or a CPU?
SoC. Similar as above. AFAIK, ARM SoC vendors usually didn't name for each CPU not SoC if there is no change in core hardware implementation, at least Samsung didn't name.
OK, if you still have strong objection on this, I will remove PMU support here until agreement about that.
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arch/arm64/boot/dts/samsung-gh7.dtsi line 104
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arch/arm64/boot/dts/samsung-gh7.dtsi new file +5
-0+ serial at 12c20000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x12c20000 0 0x10000>; + interrupts = <0 420 0>; + };These are both missing required clocks.
Yes right.
So you'll add these?
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To be honest, still I'm not sure how it should be handled because regarding clocks do not need to handle in the kernel for GH7. And for it, I needed to use some HACKs to change clock handling in the kernel. I will provide proper solution soon.
Are the clocks always-on, fixed-rate clocks, or does some firmware manage them dynamically? We have bindings for the former.
Actually, some firmware handles them and basically and kernel doesn't need.
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There's not much point having a DTS upstream that relies on hacks which are not.
At the end, we are going to use just upstream kernel for GH7 without any HACKs but as a preliminary, this is a good start point even there is HACK for a while.
Thanks,
Kukjin
PATCH v2 1/3 arm64: dts: add initial dts for Samsung GH7 SoC and SSDK-GH7 board
In reply to Mark RutlandQuoted 11 lines · Mark Rutland
Quoted 8 lines · Kukjin Kim
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts line 16
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arch/arm64/boot/dts/samsung-ssdk-gh7.dts new file +2
-0+/ { + model = "SAMSUNG SSDK-GH7 board based on GH7 SoC";Is the "based on GH7 SoC" part necessary? Does the "SSDK-GH7" not give that away?
In this case, yes, SSDK-GH7 is enough but I though, in case of different board adding what SoC is used on the board in that is useful. Anyway, OK.
Quoted 8 lines
Looking at ePAPR, the recommended format is "manufacturer,model", and the string is intended to identify a particular implementation. It is not intended to give details about the implementation that can be derived from the name.
We seem to have ignored the format (and to some degree purpose) of the model property so far, but I don't see any reason to fill it with unnecessary information.
Might it be worth defining a property explicitly intended to be used as
a display name for human consumption? Half the problem with model is
that we don't have a way to use it for quirking so nobody ever really
looks at it (though I guess we will want that at some point now we're
going for fixed ABI stuff), but not having a place to put a pretty name
does encourage this sort of thing.
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PATCH v2 2/3 arm64: defconfig: Enable ARCH_GH7 by default
In reply to Kukjin KimThis patch adds support for Samsung GH7 SoC in arm64/Kconfig and enable Samsung GH7 based SSDK_GH7 in single defconfig for arm64.
--- arch/arm64/Kconfig | 3 +++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/configs/defconfig | 1 + 3 files changed, 5 insertions(+)
arch/arm64/Kconfig +3 -0
@@ -111,6 +111,9 @@ source "kernel/Kconfig.freezer" menu "Platform selection" +config ARCH_GH7 + bool + config ARCH_VEXPRESS bool "ARMv8 software model (Versatile Express)" select ARCH_REQUIRE_GPIOLIB
arch/arm64/boot/dts/Makefile +1 -0
@@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_GH7) += samsung-ssdk-gh7.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
arch/arm64/configs/defconfig +1 -0
@@ -23,6 +23,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_GH7=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_XGENE=y CONFIG_SMP=y
Signature · 1 line
1.8.2.1.339.g52a3e01
Catalin Marinas
maintainerPATCH v2 2/3 arm64: defconfig: Enable ARCH_GH7 by default
Quoted 16 lines · Kukjin Kim
This patch adds support for Samsung GH7 SoC in arm64/Kconfig and enable Samsung GH7 based
SSDK_GH7in single defconfig for arm64.Signed-off-by Kukjin Kim <[email protected]>Cc Catalin Marinas <[email protected]>--- arch/arm64/Kconfig | 3 +++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/configs/defconfig | 1 + 3 files changed, 5 insertions(+)arch/arm64/Kconfig +0
-0
arch/arm64/Kconfig source "kernel/Kconfig.freezer" · line 115
Quoted 5 lines
arch/arm64/Kconfig +2
-0@@ -111,6 +111,9 @@ source "kernel/Kconfig.freezer" menu "Platform selection" +config ARCH_GH7 + bool
You should add some text here so that people can disable it. The aim is single Image by default but I think we should let people disable certain platforms for more targeted deployments.
Signature · 1 line
Catalin
PATCH v2 2/3 arm64: defconfig: Enable ARCH_GH7 by default
Quoted 18 lines · Catalin Marinas
Quoted 17 lines · Kukjin Kim
This patch adds support for Samsung GH7 SoC in arm64/Kconfig and enable Samsung GH7 based
SSDK_GH7in single defconfig for arm64.Signed-off-by Kukjin Kim<[email protected]>Cc Catalin Marinas<[email protected]>--- arch/arm64/Kconfig | 3 +++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/configs/defconfig | 1 + 3 files changed, 5 insertions(+)arch/arm64/Kconfig +0
-0@@ -111,6 +111,9 @@ source "kernel/Kconfig.freezer"
Quoted 9 lines
arch/arm64/Kconfig source "kernel/Kconfig.freezer" · line 115
Quoted 4 lines
arch/arm64/Kconfig +2
-0menu "Platform selection" +config ARCH_GH7 + boolYou should add some text here so that people can disable it. The aim is single Image by default but I think we should let people disable certain platforms for more targeted deployments.
OK, I'll add and re-submit with Cc'ing dt mailing list.
Thanks,
Kukjin
PATCH v2 3/3 Documentation: DT: add new entry for Samsung GH7 SoC and SSDK board
In reply to Kukjin Kim--- Documentation/devicetree/bindings/arm/samsung-boards.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/arm/samsung-boards.txt +9 -0
@@ -16,3 +16,12 @@ Optional: compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; }; + +* Samsung's GH7 based SSDK-GH7 evaluation board + +SSDK-GH7 evaluation board is based on Samsung's GH7 SoC which has ARMv8 cores. + +Required root node properties: + - compatible = should be one or more of the following. + (a) "samsung,ssdk-gh7" - for Samsung's SSDK-GH7 eval board. + (b) "samsung,gh7" - for boards based on GH7 SoC.
Signature · 1 line
1.8.2.1.339.g52a3e01
Catalin Marinas
maintainerPATCH v2 3/3 Documentation: DT: add new entry for Samsung GH7 SoC and SSDK board
Quoted 3 lines · Kukjin Kim
Signed-off-by Kukjin Kim <[email protected]>Reviewed-by Thomas Abraham <[email protected]>Cc Catalin Marinas <[email protected]>
Same here, please cc the devicetree list.
Signature · 1 line
Catalin