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ARM: at91: add PWM clock and device node

PATCH New Bo Shen 2 participants 5 messages Dec 19, 2013 – Mar 12, 2014

Subsystems (4)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm/Microchip (AT91) SoC support
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Bo Shen

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#0 lore raw

cover ARM: at91: add PWM clock and device node

This patch series add PWM clock and device node
- The sama5d3 has transfer to CCF, so only it uses CCF, all others still use old clock method.
Switch gpio control leds to PWM control leds on at91sam9m10g45ek board.

This patch series depends on Atmel PWM driver which has in PWM subsystem.

Bo Shen (3):
ARM: at91: add PWM clock
ARM: at91: add PWM device node
arm: at91: at91sam9m10g45ek: switch to PWM leds

 arch/arm/boot/dts/at91sam9263.dtsi     |    9 +++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi     |    9 +++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts |   25 +++++++++++++++++++++++--
 arch/arm/boot/dts/at91sam9n12.dtsi     |    9 +++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi      |    9 +++++++++
 arch/arm/boot/dts/sama5d3.dtsi         |   10 ++++++++++
 arch/arm/mach-at91/at91sam9263.c       |    1 +
 arch/arm/mach-at91/at91sam9g45.c       |    1 +
 arch/arm/mach-at91/at91sam9n12.c       |    1 +
 arch/arm/mach-at91/at91sam9rl.c        |    1 +
 arch/arm/mach-at91/at91sam9x5.c        |    1 +
 11 files changed, 74 insertions(+), 2 deletions(-)
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH 1/3 ARM: at91: add PWM clock

Add PWM clock for AT91 series SoC which include PWM controller.

Signed-off-by Bo Shen <[email protected]>
---
 arch/arm/mach-at91/at91sam9263.c |    1 +
 arch/arm/mach-at91/at91sam9g45.c |    1 +
 arch/arm/mach-at91/at91sam9n12.c |    1 +
 arch/arm/mach-at91/at91sam9rl.c  |    1 +
 arch/arm/mach-at91/at91sam9x5.c  |    1 +
 5 files changed, 5 insertions(+)
arch/arm/mach-at91/at91sam9263.c +1 -0
index 37b90f4..fbd771d 100644
@@ -223,6 +223,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9g45.c +1 -0
index 2f455ce..e9ba934 100644
@@ -284,6 +284,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_ID("pioE", &pioDE_clk),
 	/* Fake adc clock */
 	CLKDEV_CON_ID("adc_clk", &tsc_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9n12.c +1 -0
index 4ef088c..f2ea7b0 100644
@@ -182,6 +182,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	/* additional fake clock for macb_hclk */
 	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
 	CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 };
 
 /*
arch/arm/mach-at91/at91sam9rl.c +1 -0
index 3651517..e577d37 100644
@@ -196,6 +196,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_ID("pioB", &pioB_clk),
 	CLKDEV_CON_ID("pioC", &pioC_clk),
 	CLKDEV_CON_ID("pioD", &pioD_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9x5.c +1 -0
index 3e8ec26..9ad781d 100644
@@ -253,6 +253,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
 	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 };
 
 /*
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH 1/3 ARM: at91: add PWM clock

On 19/12/2013 04:59, Bo Shen :

Quoted 3 lines

Add PWM clock for AT91 series SoC which include PWM controller.

Signed-off-by Bo Shen <[email protected]>

This one was forgotten in previous update.

Stacked on at91-3.15-cleanup because of dependency on 9rl modifications.

Thanks.

Quoted 69 lines
---
 arch/arm/mach-at91/at91sam9263.c |    1 +
 arch/arm/mach-at91/at91sam9g45.c |    1 +
 arch/arm/mach-at91/at91sam9n12.c |    1 +
 arch/arm/mach-at91/at91sam9rl.c  |    1 +
 arch/arm/mach-at91/at91sam9x5.c  |    1 +
 5 files changed, 5 insertions(+)
arch/arm/mach-at91/at91sam9263.c +1 -0
index 37b90f4..fbd771d 100644
@@ -223,6 +223,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9g45.c +1 -0
index 2f455ce..e9ba934 100644
@@ -284,6 +284,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_ID("pioE", &pioDE_clk),
 	/* Fake adc clock */
 	CLKDEV_CON_ID("adc_clk", &tsc_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9n12.c +1 -0
index 4ef088c..f2ea7b0 100644
@@ -182,6 +182,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	/* additional fake clock for macb_hclk */
 	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
 	CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 };
 
 /*
arch/arm/mach-at91/at91sam9rl.c +1 -0
index 3651517..e577d37 100644
@@ -196,6 +196,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_ID("pioB", &pioB_clk),
 	CLKDEV_CON_ID("pioC", &pioC_clk),
 	CLKDEV_CON_ID("pioD", &pioD_clk),
+	CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
 };
 
 static struct clk_lookup usart_clocks_lookups[] = {
arch/arm/mach-at91/at91sam9x5.c +1 -0
index 3e8ec26..9ad781d 100644
@@ -253,6 +253,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
 	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
+	CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 };
 
 /*
Signature · 1 line
Nicolas Ferre
author
#3 lore raw

PATCH 2/3 ARM: at91: add PWM device node

In reply to Bo Shen

Add PWM device node for AT91 series SoC.

Signed-off-by Bo Shen <[email protected]>
---
 arch/arm/boot/dts/at91sam9263.dtsi |    9 +++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi |    9 +++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi |    9 +++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  |    9 +++++++++
 arch/arm/boot/dts/sama5d3.dtsi     |   10 ++++++++++
 5 files changed, 46 insertions(+)
arch/arm/boot/dts/at91sam9263.dtsi +9 -0
index d5bd65f..94de2f8 100644
@@ -30,6 +30,7 @@
 		i2c0 = &i2c0;
 		ssc0 = &ssc0;
 		ssc1 = &ssc1;
+		pwm0 = &pwm0;
 	};
 	cpus {
 		#address-cells = <0>;

@@ -547,6 +548,14 @@
 				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
+
+			pwm0: pwm at fffb8000 {
+				compatible = "atmel,at91sam9rl-pwm";
+				reg = <0xfffb8000 0x300>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
arch/arm/boot/dts/at91sam9g45.dtsi +9 -0
index c3e5148..d2b29be 100644
@@ -37,6 +37,7 @@
 		i2c1 = &i2c1;
 		ssc0 = &ssc0;
 		ssc1 = &ssc1;
+		pwm0 = &pwm0;
 	};
 	cpus {
 		#address-cells = <0>;

@@ -725,6 +726,14 @@
 					atmel,can-isoc;
 				};
 			};
+
+			pwm0: pwm at fffb8000 {
+				compatible = "atmel,at91sam9rl-pwm";
+				reg = <0xfffb8000 0x300>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
arch/arm/boot/dts/at91sam9n12.dtsi +9 -0
index 6224f9f..7248270 100644
@@ -33,6 +33,7 @@
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		ssc0 = &ssc0;
+		pwm0 = &pwm0;
 	};
 	cpus {
 		#address-cells = <0>;

@@ -542,6 +543,14 @@
 				reg = <0xfffffe40 0x10>;
 				status = "disabled";
 			};
+
+			pwm0: pwm at f8034000 {
+				compatible = "atmel,at91sam9rl-pwm";
+				reg = <0xf8034000 0x300>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
arch/arm/boot/dts/at91sam9x5.dtsi +9 -0
index 40267a1..6e5e9cf 100644
@@ -35,6 +35,7 @@
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		ssc0 = &ssc0;
+		pwm0 = &pwm0;
 	};
 	cpus {
 		#address-cells = <0>;

@@ -762,6 +763,14 @@
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				status = "disabled";
 			};
+
+			pwm0: pwm at f8034000 {
+				compatible = "atmel,at91sam9rl-pwm";
+				reg = <0xf8034000 0x300>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
arch/arm/boot/dts/sama5d3.dtsi +10 -0
index de9fece..02cca2e 100644
@@ -37,6 +37,7 @@
 		i2c2 = &i2c2;
 		ssc0 = &ssc0;
 		ssc1 = &ssc1;
+		pwm0 = &pwm0;
 	};
 	cpus {
 		#address-cells = <1>;

@@ -179,6 +180,15 @@
 				status = "disabled";
 			};
 
+			pwm0: pwm at f002c000 {
+				compatible = "atmel,sama5d3-pwm";
+				reg = <0xf002c000 0x300>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
+				#pwm-cells = <3>;
+				clocks = <&pwm_clk>;
+				status = "disabled";
+			};
+
 			isi: isi at f0034000 {
 				compatible = "atmel,at91sam9g45-isi";
 				reg = <0xf0034000 0x4000>;
Signature · 1 line
1.7.9.5
author
#4 lore raw

PATCH 3/3 arm: at91: at91sam9m10g45ek: switch to PWM leds

In reply to Bo Shen

The d6 and d7 is connected to PWM, we can use PWM to control it, so switch to PWM leds.

Signed-off-by Bo Shen <[email protected]>
---
 arch/arm/boot/dts/at91sam9m10g45ek.dts |   25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)
arch/arm/boot/dts/at91sam9m10g45ek.dts +23 -2
index a4b00e5..96059e6 100644
@@ -105,6 +105,14 @@
 							 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PD29 gpio WP pin pull up */
 					};
 				};
+
+				pwm0 {
+					pinctrl_pwm_leds: pwm-led {
+						atmel,pins =
+							<AT91_PIOD 0  AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PD0 periph B */
+							 AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PD31 periph B */
+					};
+				};
 			};
 
 			spi0: spi at fffa4000{

@@ -121,6 +129,13 @@
 				atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
 				status = "okay";
 			};
+
+			pwm0: pwm at fffb8000 {
+				status = "okay";
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_pwm_leds>;
+			};
 		};
 
 		nand0: nand at 40000000 {

@@ -165,16 +180,22 @@
 			gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
 
 		d6 {
 			label = "d6";
-			gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
+			pwms = <&pwm0 3 5000 0>;
+			max-brightness = <255>;
 			linux,default-trigger = "nand-disk";
 		};
 
 		d7 {
 			label = "d7";
-			gpios = <&pioD 31 GPIO_ACTIVE_LOW>;
+			pwms = <&pwm0 1 5000 0>;
+			max-brightness = <255>;
 			linux,default-trigger = "mmc0";
 		};
 	};
Signature · 1 line
1.7.9.5