clk: exynos-5420: Fix VPLL lock offset
Subsystems (3)
PATCH 1/1 clk: exynos-5420: Fix VPLL lock offset
Set it as per the user manual.
--- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5420.c +1 -1
@@ -33,7 +33,7 @@#define RPLL_LOCK 0x10050#define IPLL_LOCK 0x10060#define SPLL_LOCK 0x10070 -#define VPLL_LOCK 0x10070 +#define VPLL_LOCK 0x10080#define MPLL_LOCK 0x10090#define CPLL_CON0 0x10120#define DPLL_CON0 0x10128
Signature · 1 line
1.7.9.5
PATCH 1/1 clk: exynos-5420: Fix VPLL lock offset
Hi Sachin,
Quoted 13 lines · Sachin Kamat
Set it as per the user manual.
Signed-off-by Sachin Kamat <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/samsung/clk-exynos5420.c +0
-0
drivers/clk/samsung/clk-exynos5420.c line 39
Quoted 8 lines
drivers/clk/samsung/clk-exynos5420.c +1
-1@@ -33,7 +33,7 @@#define RPLL_LOCK 0x10050#define IPLL_LOCK 0x10060#define SPLL_LOCK 0x10070 -#define VPLL_LOCK 0x10070 +#define VPLL_LOCK 0x10080#define MPLL_LOCK 0x10090#define CPLL_CON0 0x10120#define DPLL_CON0 0x10128
Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate setting on Exynos 5420 (no rate tables registered).
Best regards,
Tomasz
PATCH 1/1 clk: exynos-5420: Fix VPLL lock offset
Quoted 5 lines · Tomasz Figa
Hi Sachin,
Quoted 1 line · Sachin Kamat
Quoted 8 lines
Quoted 4 lines
Set it as per the user manual.
Signed-off-by Sachin Kamat <[email protected]>---
Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate setting on Exynos 5420 (no rate tables registered).
Yes, that is correct. Thanks Tomasz.
Signature · 2 lines
With warm regards, Sachin
PATCH 1/1 clk: exynos-5420: Fix VPLL lock offset
Hi Tomasz,
Quoted 8 lines · Sachin Kamat
Quoted 7 lines · Tomasz Figa
Hi Sachin,
Quoted 3 lines · Sachin Kamat
Set it as per the user manual.
Quoted 8 lines
Quoted 6 lines
Quoted 2 lines
Signed-off-by Sachin Kamat <[email protected]>---
Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate setting on Exynos 5420 (no rate tables registered).
Yes, that is correct. Thanks Tomasz.
Looks like this patch hasn't made it to mainline yet.
Signature · 2 lines
With warm regards, Sachin
PATCH 1/1 clk: exynos-5420: Fix VPLL lock offset
Hi Sachin,
Quoted 15 lines · Sachin Kamat
Hi Tomasz,
Quoted 12 lines · Sachin Kamat
Quoted 11 lines · Tomasz Figa
Hi Sachin,
Quoted 5 lines · Sachin Kamat
Set it as per the user manual.
Signed-off-by Sachin Kamat <[email protected]>---
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate setting on Exynos 5420 (no rate tables registered).
Yes, that is correct. Thanks Tomasz.
Looks like this patch hasn't made it to mainline yet.
Unfortunately that's right. Due to problems with cross tree dependencies there was some fall out and I needed to requeue some patches for 3.16. Sorry for this.
Best regards,
Tomasz