clk: exynos: add support for exynos5260 SoC

Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer.

This layer is modified accordingly to enable the support for multiple clock providers.

Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c2412 and S3c2443 are also modified as per changed helper functions.

Signed-off-by Rahul Sharma <[email protected]>

---
  drivers/clk/samsung/clk-exynos4.c    |   47 +++++++-------
  drivers/clk/samsung/clk-exynos5250.c |   25 +++++---
  drivers/clk/samsung/clk-exynos5420.c |   24 ++++---
  drivers/clk/samsung/clk-exynos5440.c |   18 +++---
  drivers/clk/samsung/clk-pll.c        |   14 +++--
  drivers/clk/samsung/clk-s3c2412.c    |   29 +++++----
  drivers/clk/samsung/clk-s3c2443.c    |   46 +++++++-------
  drivers/clk/samsung/clk-s3c64xx.c    |   44 +++++++------
  drivers/clk/samsung/clk.c            |  114 ++++++++++++++++++----------------
  drivers/clk/samsung/clk.h            |   72 ++++++++++++++-------
  10 files changed, 251 insertions(+), 182 deletions(-)

From: Pankaj Dubey <[email protected]>

exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here.

Signed-off-by Pankaj Dubey <[email protected]>

Signed-off-by Rahul Sharma <[email protected]>

Signed-off-by Arun Kumar K <[email protected]>

---
  drivers/clk/samsung/clk-pll.c |  108 +++++++++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-pll.h |    1 +
  2 files changed, 109 insertions(+)

Add support for pll2650xx in samsung pll file. This PLL variant is close to pll36xx but uses CON2 registers instead of CON1.

Aud_pll in Exynos5260 is pll2650xx and uses this code.

Signed-off-by Rahul Sharma <[email protected]>

---
  drivers/clk/samsung/clk-pll.c |  101 +++++++++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-pll.h |    1 +
  2 files changed, 102 insertions(+)

drivers/clk/samsung/clk-pll.c +101 -0

index 18e42ef..b07fad2 100644
@@ -1049,6 +1049,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
  	.recalc_rate = samsung_pll2550xx_recalc_rate,
  };
 
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR 3000
+
+#define PLL2650XX_MDIV_SHIFT		9
+#define PLL2650XX_PDIV_SHIFT		3
+#define PLL2650XX_SDIV_SHIFT		0
+#define PLL2650XX_KDIV_SHIFT		0
+#define PLL2650XX_MDIV_MASK		0x1ff
+#define PLL2650XX_PDIV_MASK		0x3f
+#define PLL2650XX_SDIV_MASK		0x7
+#define PLL2650XX_KDIV_MASK		0xffff
+#define PLL2650XX_PLL_ENABLE_SHIFT	23
+#define PLL2650XX_PLL_LOCKTIME_SHIFT	21
+#define PLL2650XX_PLL_FOUTMASK_SHIFT	31
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+				unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+	s16 kdiv;
+	u64 fvco = parent_rate;
+
+	pll_con0 = __raw_readl(pll->con_reg);
+	pll_con2 = __raw_readl(pll->con_reg + 8);
+	mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+	kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+	fvco *= (mdiv << 16) + kdiv;
+	do_div(fvco, (pdiv << sdiv));
+	fvco >>= 16;
+
+	return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+					unsigned long parent_rate)
+{
+	struct samsung_clk_pll *pll = to_clk_pll(hw);
+	u32 tmp, pll_con0, pll_con2;
+	const struct samsung_pll_rate_table *rate;
+
+	rate = samsung_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+			drate, __clk_get_name(hw->clk));
+		return -EINVAL;
+	}
+
+	pll_con0 = __raw_readl(pll->con_reg);
+	pll_con2 = __raw_readl(pll->con_reg + 8);
+
+	 /* Change PLL PMS values */
+	pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+			PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+			PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+	pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+	pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+	pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+	pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+	pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+	pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+	pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+			<< PLL2650XX_KDIV_SHIFT;
+
+	/* Set PLL lock time. */
+	__raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+	__raw_writel(pll_con0, pll->con_reg);
+	__raw_writel(pll_con2, pll->con_reg + 8);
+
+	do {
+		tmp = __raw_readl(pll->con_reg);
+	} while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+	return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+	.recalc_rate = samsung_pll2650xx_recalc_rate,
+	.set_rate = samsung_pll2650xx_set_rate,
+	.round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+	.recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
  static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
  				struct samsung_pll_clock *pll_clk,
  				void __iomem *base)

@@ -1157,6 +1252,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
  		else
  			init.ops = &samsung_pll2550xx_clk_ops;
  		break;
+	case pll_2650xx:
+		if (!pll->rate_table)
+			init.ops = &samsung_pll2650xx_clk_min_ops;
+		else
+			init.ops = &samsung_pll2650xx_clk_ops;
+		break;
  	default:
  		pr_warn("%s: Unknown pll type for pll clk %s\n",
  			__func__, pll_clk->name);

drivers/clk/samsung/clk-pll.h +0 -0

index ec4bc1d..c0ed4d4 100644

Hi Rahul,

Quoted 141 lines · Rahul Sharma

Add support for pll2650xx in samsung pll file. This PLL variant is close to pll36xx but uses CON2 registers instead of CON1.

Aud_pll in Exynos5260 is pll2650xx and uses this code.

Signed-off-by Rahul Sharma <[email protected]>

---
  drivers/clk/samsung/clk-pll.c |  101
+++++++++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-pll.h |    1 +
  2 files changed, 102 insertions(+)

drivers/clk/samsung/clk-pll.c +94 -0

index 18e42ef..b07fad2 100644
@@ -1049,6 +1049,101 @@ static const struct clk_ops
 samsung_pll2550xx_clk_min_ops = {
        .recalc_rate = samsung_pll2550xx_recalc_rate,
  };
  +/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR 3000
+
+#define PLL2650XX_MDIV_SHIFT           9
+#define PLL2650XX_PDIV_SHIFT           3
+#define PLL2650XX_SDIV_SHIFT           0
+#define PLL2650XX_KDIV_SHIFT           0
+#define PLL2650XX_MDIV_MASK            0x1ff
+#define PLL2650XX_PDIV_MASK            0x3f
+#define PLL2650XX_SDIV_MASK            0x7
+#define PLL2650XX_KDIV_MASK            0xffff
+#define PLL2650XX_PLL_ENABLE_SHIFT     23
+#define PLL2650XX_PLL_LOCKTIME_SHIFT   21
+#define PLL2650XX_PLL_FOUTMASK_SHIFT   31
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+                               unsigned long parent_rate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+       s16 kdiv;
+       u64 fvco = parent_rate;
+
+       pll_con0 = __raw_readl(pll->con_reg);
+       pll_con2 = __raw_readl(pll->con_reg + 8);
+       mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+       pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+       sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+       kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+       fvco *= (mdiv << 16) + kdiv;
+       do_div(fvco, (pdiv << sdiv));
+       fvco >>= 16;
+
+       return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long
 drate,
+                                       unsigned long parent_rate)
+{
+       struct samsung_clk_pll *pll = to_clk_pll(hw);
+       u32 tmp, pll_con0, pll_con2;
+       const struct samsung_pll_rate_table *rate;
+
+       rate = samsung_get_pll_settings(pll, drate);
+       if (!rate) {
+               pr_err("%s: Invalid rate : %lu for pll clk %s\n",
 __func__,
+                       drate, __clk_get_name(hw->clk));
+               return -EINVAL;
+       }
+
+       pll_con0 = __raw_readl(pll->con_reg);
+       pll_con2 = __raw_readl(pll->con_reg + 8);
+
+        /* Change PLL PMS values */
+       pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+                       PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+                       PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+       pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+       pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+       pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+       pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+       pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+       pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+       pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+                       << PLL2650XX_KDIV_SHIFT;
+
+       /* Set PLL lock time. */
+       __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+       __raw_writel(pll_con0, pll->con_reg);
+       __raw_writel(pll_con2, pll->con_reg + 8);
+
+       do {
+               tmp = __raw_readl(pll->con_reg);
+       } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+       return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+       .recalc_rate = samsung_pll2650xx_recalc_rate,
+       .set_rate = samsung_pll2650xx_set_rate,
+       .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+       .recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
  static void __init _samsung_clk_register_pll(struct samsung_clk_provider

*ctx,
struct samsung_pll_clock *pll_clk, void __iomem *base)

drivers/clk/samsung/clk-pll.c +6 -0

@@ -1157,6 +1252,12 @@ static void __init _samsung_clk_register_pll(struct
 samsung_clk_provider *ctx,
                else
                        init.ops = &samsung_pll2550xx_clk_ops;
                break;
+       case pll_2650xx:
+               if (!pll->rate_table)
+                       init.ops = &samsung_pll2650xx_clk_min_ops;
+               else
+                       init.ops = &samsung_pll2650xx_clk_ops;
+               break;
        default:
                pr_warn("%s: Unknown pll type for pll clk %s\n",

                        __func__, pll_clk->name);

drivers/clk/samsung/clk-pll.h +0 -0

index ec4bc1d..c0ed4d4 100644

drivers/clk/samsung/clk-pll.h enum samsung_pll_type { · line 37

Quoted 6 lines

drivers/clk/samsung/clk-pll.h +1 -0

@@ -32,6 +32,7 @@ enum samsung_pll_type {
        pll_s3c2410_upll,
        pll_s3c2440_mpll,
        pll_2550xx,
+       pll_2650xx,
  };
    #define PLL_35XX_RATE(_rate, _m, _p, _s)                    \

Reviewed-by Pankaj Dubey <[email protected]>

--
Best Regards,
Pankaj Dubey

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Add support for pll2650xx in samsung pll file. This PLL variant is close to pll36xx but uses CON2 registers instead of CON1.

Aud_pll in Exynos5260 is pll2650xx and uses this code.

Signed-off-by Rahul Sharma <[email protected]>

---
  drivers/clk/samsung/clk-pll.c |  101 +++++++++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-pll.h |    1 +
  2 files changed, 102 insertions(+)

Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.

Signed-off-by Rahul Sharma <[email protected]>

---
  .../devicetree/bindings/clock/exynos5260-clock.txt |   55 +++++
  include/dt-bindings/clock/exynos5260-clk.h         |  233 ++++++++++++++++++++
  2 files changed, 288 insertions(+)

create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 include/dt-bindings/clock/exynos5260-clk.h

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +22 -0

new file mode 100644
index 0000000..4128892
@@ -0,0 +1,55 @@
+* Samsung Exynos5260 Clock Controller
+
+The Exynos5260 clock controller encapsulate all CMUs which are
+instantiaited independently from the device-tree. As a whole, these
+CMUs generates and supplies clocks to various controllers within
+the Exynos5260 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+	"exynos5260-clock-top"
+	"exynos5260-clock-peri"
+	"exynos5260-clock-egl"
+	"exynos5260-clock-kfc"
+	"exynos5260-clock-g2d"
+	"exynos5260-clock-mif"
+	"exynos5260-clock-mfc"
+	"exynos5260-clock-g3d"
+	"exynos5260-clock-fsys"
+	"exynos5260-clock-aud"
+	"exynos5260-clock-isp"
+	"exynos5260-clock-gscl"

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +12 -0

+specify the clock, which they want to consume.
+
+Example 1: An example of a clock controller node is listed below.
+
+	cmu_disp: clock-controller@0x14550000 {
+		compatible = "exynos5260-clock-disp";
+		reg = <0x14550000 0x10000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the
+		peri clock controller. Refer to the standard clock bindings for

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +1 -0

+

include/dt-bindings/clock/exynos5260-clk.h new file +11 -0

new file mode 100644
index 0000000..d6f4391
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H

include/dt-bindings/clock/exynos5260-clk.h new file +202 -0

+#define TOP_NR_CLK		12
+
+/* List Of Clocks For CMU_EGL */
+#define EGL_FOUT_EGL_PLL	1
+#define EGL_FOUT_EGL_DPLL	2
+#define EGL_NR_CLK		3
+
+/* List Of Clocks For CMU_KFC */
+#define KFC_FOUT_KFC_PLL	1
+#define KFC_NR_CLK		2
+
+/* List Of Clocks For CMU_MIF */
+#define MIF_FOUT_MEM_PLL	1
+#define MIF_FOUT_BUS_PLL	2
+#define MIF_FOUT_MEDIA_PLL	3
+#define MIF_NR_CLK		4
+
+/* List Of Clocks For CMU_G3D */
+#define G3D_FOUT_G3D_PLL	1
+#define G3D_CLK_G3D_HPM		2
+#define G3D_CLK_G3D		3
+#define G3D_NR_CLK		4
+
+/* List Of Clocks For CMU_AUD */
+#define AUD_CLK_AUD_UART	1
+#define AUD_CLK_PCM		2
+#define AUD_CLK_I2S		3
+#define AUD_CLK_DMAC		4
+#define AUD_SCLK_AUD_UART	5
+#define AUD_SCLK_PCM		6
+#define AUD_SCLK_I2S		7
+#define AUD_NR_CLK		8
+
+/* List Of Clocks For CMU_MFC */
+#define MFC_CLK_MFC		1
+#define MFC_CLK_SMMU2_MFCM1	2
+#define MFC_CLK_SMMU2_MFCM0	3
+#define MFC_NR_CLK		4
+
+/* List Of Clocks For CMU_GSCL */
+#define GSCL_CLK_PIXEL_GSCL1	1
+#define GSCL_CLK_PIXEL_GSCL0	2
+#define GSCL_CLK_MSCL1		3
+#define GSCL_CLK_MSCL0		4
+#define GSCL_CLK_GSCL1		5
+#define GSCL_CLK_GSCL0		6
+#define GSCL_CLK_FIMC_LITE_D	7
+#define GSCL_CLK_FIMC_LITE_B	8
+#define GSCL_CLK_FIMC_LITE_A	9
+#define GSCL_CLK_CSIS1		10
+#define GSCL_CLK_CSIS0		11
+#define GSCL_CLK_SMMU3_LITE_D	12
+#define GSCL_CLK_SMMU3_LITE_B	13
+#define GSCL_CLK_SMMU3_LITE_A	14
+#define GSCL_CLK_SMMU3_GSCL0	15
+#define GSCL_CLK_SMMU3_GSCL1	16
+#define GSCL_CLK_SMMU3_MSCL0	17
+#define GSCL_CLK_SMMU3_MSCL1	18
+#define GSCL_SCLK_CSIS1_WRAP	19
+#define GSCL_SCLK_CSIS0_WRAP	20
+#define GSCL_NR_CLK		21
+
+/* List Of Clocks For CMU_FSYS */
+#define FSYS_CLK_TSI		1
+#define FSYS_CLK_USBLINK	2
+#define FSYS_CLK_USBHOST20	3
+#define FSYS_CLK_USBDRD30	4
+#define FSYS_CLK_SROMC		5
+#define FSYS_CLK_PDMA		6
+#define FSYS_CLK_MMC2		7
+#define FSYS_CLK_MMC1		8
+#define FSYS_CLK_MMC0		9
+#define FSYS_CLK_RTIC		10
+#define FSYS_CLK_SMMU_RTIC	11
+#define FSYS_PHYCLK_USBDRD30	12
+#define FSYS_PHYCLK_USBHOST20	13
+#define FSYS_NR_CLK		14
+
+/* List Of Clocks For CMU_PERI */
+#define PERI_CLK_WDT_KFC	1
+#define PERI_CLK_WDT_EGL	2
+#define PERI_CLK_HSIC3		3
+#define PERI_CLK_HSIC2		4
+#define PERI_CLK_HSIC1		5
+#define PERI_CLK_HSIC0		6
+#define PERI_CLK_PCM		7
+#define PERI_CLK_MCT		8
+#define PERI_CLK_I2S		9
+#define PERI_CLK_I2CHDMI	10
+#define PERI_CLK_I2C7		11
+#define PERI_CLK_I2C6		12
+#define PERI_CLK_I2C5		13
+#define PERI_CLK_I2C4		14
+#define PERI_CLK_I2C9		15
+#define PERI_CLK_I2C8		16
+#define PERI_CLK_I2C11		17
+#define PERI_CLK_I2C10		18
+#define PERI_CLK_HDMICEC	19
+#define PERI_CLK_EFUSE_WRITER	20
+#define PERI_CLK_ABB		21
+#define PERI_CLK_UART2		22
+#define PERI_CLK_UART1		23
+#define PERI_CLK_UART0		24
+#define PERI_CLK_ADC		25
+#define PERI_CLK_TMU4		26
+#define PERI_CLK_TMU3		27
+#define PERI_CLK_TMU2		28
+#define PERI_CLK_TMU1		29
+#define PERI_CLK_TMU0		30
+#define PERI_CLK_SPI2		31
+#define PERI_CLK_SPI1		32
+#define PERI_CLK_SPI0		33
+#define PERI_CLK_SPDIF		34
+#define PERI_CLK_PWM		35
+#define PERI_CLK_UART4		36
+#define PERI_CLK_CHIPID		37
+#define PERI_CLK_PROVKEY0	38
+#define PERI_CLK_PROVKEY1	39
+#define PERI_CLK_SECKEY		40
+#define PERI_CLK_TOP_RTC	41
+#define PERI_CLK_TZPC10		42
+#define PERI_CLK_TZPC9		43
+#define PERI_CLK_TZPC8		44
+#define PERI_CLK_TZPC7		45
+#define PERI_CLK_TZPC6		46
+#define PERI_CLK_TZPC5		47
+#define PERI_CLK_TZPC4		48
+#define PERI_CLK_TZPC3		49
+#define PERI_CLK_TZPC2		50
+#define PERI_CLK_TZPC1		51
+#define PERI_CLK_TZPC0		52
+#define PERI_SCLK_SPI2		53
+#define PERI_SCLK_SPI1		54
+#define PERI_SCLK_SPI0		55
+#define PERI_SCLK_SPDIF		56
+#define PERI_SCLK_I2S		57
+#define PERI_SCLK_PCM1		58
+#define PERI_SCLK_UART2		59
+#define PERI_SCLK_UART1		60
+#define PERI_SCLK_UART0		61
+#define PERI_NR_CLK		62
+
+/* List Of Clocks For CMU_DISP */
+#define DISP_CLK_SMMU_TV	1
+#define DISP_CLK_SMMU_FIMD1M1	2
+#define DISP_CLK_SMMU_FIMD1M0	3
+#define DISP_CLK_MIXER		4
+#define DISP_CLK_MIPIPHY	5
+#define DISP_CLK_HDMIPHY	6
+#define DISP_CLK_HDMI		7
+#define DISP_CLK_FIMD1		8
+#define DISP_CLK_DSIM1		9
+#define DISP_CLK_DPPHY		10
+#define DISP_CLK_DP		11
+#define DISP_SCLK_PIXEL		12
+#define DISP_MOUT_HDMI_PHY_PIXEL_USER		13
+#define DISP_MOUT_HDMI_PHY_PIXEL	14
+#define DISP_NR_CLK		15
+
+/* List Of Clocks For CMU_G2D */
+#define G2D_CLK_SMMU3_JPEG	1
+#define G2D_CLK_MDMA		2
+#define G2D_CLK_JPEG		3
+#define G2D_CLK_G2D		4
+#define G2D_CLK_SSS		5
+#define G2D_CLK_SLIM_SSS	6
+#define G2D_CLK_SMMU_SLIM_SSS	7
+#define G2D_CLK_SMMU_SSS	8
+#define G2D_CLK_SMMU_MDMA	9
+#define G2D_CLK_SMMU3_G2D	10
+#define G2D_NR_CLK		11
+
+/* List Of Clocks For CMU_ISP */
+#define ISP_CLK_GIC		1
+#define ISP_CLK_WDT		2
+#define ISP_CLK_UART		3
+#define ISP_CLK_SPI1		4
+#define ISP_CLK_SPI0		5
+#define ISP_CLK_SMMU_SCALERP	6
+#define ISP_CLK_SMMU_SCALERC	7
+#define ISP_CLK_SMMU_ISPCX	8
+#define ISP_CLK_SMMU_ISP	9
+#define ISP_CLK_SMMU_FD		10
+#define ISP_CLK_SMMU_DRC	11
+#define ISP_CLK_PWM		12
+#define ISP_CLK_MTCADC		13
+#define ISP_CLK_MPWM		14
+#define ISP_CLK_MCUCTL		15
+#define ISP_CLK_I2C1		16
+#define ISP_CLK_I2C0		17
+#define ISP_CLK_FIMC_SCALERP	18
+#define ISP_CLK_FIMC_SCALERC	19
+#define ISP_CLK_FIMC		20
+#define ISP_CLK_FIMC_FD		21
+#define ISP_CLK_FIMC_DRC	22
+#define ISP_CLK_CA5		23
+#define ISP_SCLK_SPI0_EXT	24
+#define ISP_SCLK_SPI1_EXT	25
+#define ISP_SCLK_UART_EXT	26
+#define ISP_NR_CLK		27
+
+#endif

Hi Rahul,

Quoted 49 lines · Rahul Sharma

Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.

Signed-off-by Rahul Sharma <[email protected]>

---
  .../devicetree/bindings/clock/exynos5260-clock.txt |   55 +++++
  include/dt-bindings/clock/exynos5260-clk.h         |  233
++++++++++++++++++++
  2 files changed, 288 insertions(+)

create mode 100644
Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 include/dt-bindings/clock/exynos5260-clk.h

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +25 -0

new file mode 100644
index 0000000..4128892
@@ -0,0 +1,55 @@
+* Samsung Exynos5260 Clock Controller
+
+The Exynos5260 clock controller encapsulate all CMUs which are
+instantiaited independently from the device-tree. As a whole, these
+CMUs generates and supplies clocks to various controllers within
+the Exynos5260 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+       "exynos5260-clock-top"
+       "exynos5260-clock-peri"
+       "exynos5260-clock-egl"
+       "exynos5260-clock-kfc"
+       "exynos5260-clock-g2d"
+       "exynos5260-clock-mif"
+       "exynos5260-clock-mfc"
+       "exynos5260-clock-g3d"
+       "exynos5260-clock-fsys"
+       "exynos5260-clock-aud"
+       "exynos5260-clock-isp"
+       "exynos5260-clock-gscl"
+       "exynos5260-clock-disp"
+
+- reg: physical base address of the controller and length of memory

mapped

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +2 -0

+  region.
+

Documentation/devicetree/bindings/clock/exynos5260-clock.txt line 32

Quoted 5 lines

+- #clock-cells: should be 1.

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +4 -0

+
+The following is the list of clocks generated by each controller. Each
+clock is assigned with a MACRO constant. These constants are defined in
+"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to

nit: s/clk/clock

Quoted 21 lines

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +12 -0

+specify the clock, which they want to consume.
+
+Example 1: An example of a clock controller node is listed below.
+
+       cmu_disp: clock-controller at 0x14550000 {
+               compatible = "exynos5260-clock-disp";
+               reg = <0x14550000 0x10000>;
+               #clock-cells = <1>;
+       };
+
+Example 2: UART controller node that consumes the clock generated by the
+               peri clock controller. Refer to the standard clock

bindings for

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +7 -0

+               information about 'clocks' and 'clock-names' property.
+
+       serial at 12C00000 {
+               compatible = "samsung,exynos4210-uart";
+               reg = <0x12C00000 0x100>;
+               interrupts = <0 146 0>;
+               clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri

Documentation/devicetree/bindings/clock/exynos5260-clock.txt line 54

Quoted 4 lines

PERI_SCLK_UART0>;

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +3 -0

+               clock-names = "uart", "clk_uart_baud0";
+               status = "disabled";
+       };

Isn't it better that we should add binding information about fixed-clocks (phyclocks and ioclks) here?

Quoted 20 lines

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +1 -0

+

include/dt-bindings/clock/exynos5260-clk.h new file +11 -0

new file mode 100644
index 0000000..d6f4391
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H

include/dt-bindings/clock/exynos5260-clk.h line 21

Quoted 10 lines

include/dt-bindings/clock/exynos5260-clk.h new file +10 -0

+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/*
+ * Clock names:        XXXXX_YYYYYY_ZZZZ
+ *             |---| |----| |--|
+ *              cmu   type   IP
+ */
+
+/* List Of Clocks For CMU_TOP */
+#define FIN_PLL                        1

This should be removed now.

include/dt-bindings/clock/exynos5260-clk.h line 31

Quoted 10 lines

include/dt-bindings/clock/exynos5260-clk.h new file +10 -0

+#define TOP_FOUT_DISP_PLL      2
+#define TOP_FOUT_AUD_PLL       3
+#define TOP_SCLK_MMC0          4
+#define TOP_SCLK_MMC1          5
+#define TOP_SCLK_MMC2          6
+#define TOP_SCLK_HDMIPHY       7
+#define TOP_SCLK_FIMD1         8
+#define TOP_MOUT_FIMD1         9
+#define TOP_MOUT_DISP_PLL      10
+#define TOP_HDMI_PHY_PIXEL_CLKO        11

Quoted 196 lines

include/dt-bindings/clock/exynos5260-clk.h new file +194 -0

+#define TOP_NR_CLK             12
+
+/* List Of Clocks For CMU_EGL */
+#define EGL_FOUT_EGL_PLL       1
+#define EGL_FOUT_EGL_DPLL      2
+#define EGL_NR_CLK             3
+
+/* List Of Clocks For CMU_KFC */
+#define KFC_FOUT_KFC_PLL       1
+#define KFC_NR_CLK             2
+
+/* List Of Clocks For CMU_MIF */
+#define MIF_FOUT_MEM_PLL       1
+#define MIF_FOUT_BUS_PLL       2
+#define MIF_FOUT_MEDIA_PLL     3
+#define MIF_NR_CLK             4
+
+/* List Of Clocks For CMU_G3D */
+#define G3D_FOUT_G3D_PLL       1
+#define G3D_CLK_G3D_HPM                2
+#define G3D_CLK_G3D            3
+#define G3D_NR_CLK             4
+
+/* List Of Clocks For CMU_AUD */
+#define AUD_CLK_AUD_UART       1
+#define AUD_CLK_PCM            2
+#define AUD_CLK_I2S            3
+#define AUD_CLK_DMAC           4
+#define AUD_SCLK_AUD_UART      5
+#define AUD_SCLK_PCM           6
+#define AUD_SCLK_I2S           7
+#define AUD_NR_CLK             8
+
+/* List Of Clocks For CMU_MFC */
+#define MFC_CLK_MFC            1
+#define MFC_CLK_SMMU2_MFCM1    2
+#define MFC_CLK_SMMU2_MFCM0    3
+#define MFC_NR_CLK             4
+
+/* List Of Clocks For CMU_GSCL */
+#define GSCL_CLK_PIXEL_GSCL1   1
+#define GSCL_CLK_PIXEL_GSCL0   2
+#define GSCL_CLK_MSCL1         3
+#define GSCL_CLK_MSCL0         4
+#define GSCL_CLK_GSCL1         5
+#define GSCL_CLK_GSCL0         6
+#define GSCL_CLK_FIMC_LITE_D   7
+#define GSCL_CLK_FIMC_LITE_B   8
+#define GSCL_CLK_FIMC_LITE_A   9
+#define GSCL_CLK_CSIS1         10
+#define GSCL_CLK_CSIS0         11
+#define GSCL_CLK_SMMU3_LITE_D  12
+#define GSCL_CLK_SMMU3_LITE_B  13
+#define GSCL_CLK_SMMU3_LITE_A  14
+#define GSCL_CLK_SMMU3_GSCL0   15
+#define GSCL_CLK_SMMU3_GSCL1   16
+#define GSCL_CLK_SMMU3_MSCL0   17
+#define GSCL_CLK_SMMU3_MSCL1   18
+#define GSCL_SCLK_CSIS1_WRAP   19
+#define GSCL_SCLK_CSIS0_WRAP   20
+#define GSCL_NR_CLK            21
+
+/* List Of Clocks For CMU_FSYS */
+#define FSYS_CLK_TSI           1
+#define FSYS_CLK_USBLINK       2
+#define FSYS_CLK_USBHOST20     3
+#define FSYS_CLK_USBDRD30      4
+#define FSYS_CLK_SROMC         5
+#define FSYS_CLK_PDMA          6
+#define FSYS_CLK_MMC2          7
+#define FSYS_CLK_MMC1          8
+#define FSYS_CLK_MMC0          9
+#define FSYS_CLK_RTIC          10
+#define FSYS_CLK_SMMU_RTIC     11
+#define FSYS_PHYCLK_USBDRD30   12
+#define FSYS_PHYCLK_USBHOST20  13
+#define FSYS_NR_CLK            14
+
+/* List Of Clocks For CMU_PERI */
+#define PERI_CLK_WDT_KFC       1
+#define PERI_CLK_WDT_EGL       2
+#define PERI_CLK_HSIC3         3
+#define PERI_CLK_HSIC2         4
+#define PERI_CLK_HSIC1         5
+#define PERI_CLK_HSIC0         6
+#define PERI_CLK_PCM           7
+#define PERI_CLK_MCT           8
+#define PERI_CLK_I2S           9
+#define PERI_CLK_I2CHDMI       10
+#define PERI_CLK_I2C7          11
+#define PERI_CLK_I2C6          12
+#define PERI_CLK_I2C5          13
+#define PERI_CLK_I2C4          14
+#define PERI_CLK_I2C9          15
+#define PERI_CLK_I2C8          16
+#define PERI_CLK_I2C11         17
+#define PERI_CLK_I2C10         18
+#define PERI_CLK_HDMICEC       19
+#define PERI_CLK_EFUSE_WRITER  20
+#define PERI_CLK_ABB           21
+#define PERI_CLK_UART2         22
+#define PERI_CLK_UART1         23
+#define PERI_CLK_UART0         24
+#define PERI_CLK_ADC           25
+#define PERI_CLK_TMU4          26
+#define PERI_CLK_TMU3          27
+#define PERI_CLK_TMU2          28
+#define PERI_CLK_TMU1          29
+#define PERI_CLK_TMU0          30
+#define PERI_CLK_SPI2          31
+#define PERI_CLK_SPI1          32
+#define PERI_CLK_SPI0          33
+#define PERI_CLK_SPDIF         34
+#define PERI_CLK_PWM           35
+#define PERI_CLK_UART4         36
+#define PERI_CLK_CHIPID                37
+#define PERI_CLK_PROVKEY0      38
+#define PERI_CLK_PROVKEY1      39
+#define PERI_CLK_SECKEY                40
+#define PERI_CLK_TOP_RTC       41
+#define PERI_CLK_TZPC10                42
+#define PERI_CLK_TZPC9         43
+#define PERI_CLK_TZPC8         44
+#define PERI_CLK_TZPC7         45
+#define PERI_CLK_TZPC6         46
+#define PERI_CLK_TZPC5         47
+#define PERI_CLK_TZPC4         48
+#define PERI_CLK_TZPC3         49
+#define PERI_CLK_TZPC2         50
+#define PERI_CLK_TZPC1         51
+#define PERI_CLK_TZPC0         52
+#define PERI_SCLK_SPI2         53
+#define PERI_SCLK_SPI1         54
+#define PERI_SCLK_SPI0         55
+#define PERI_SCLK_SPDIF                56
+#define PERI_SCLK_I2S          57
+#define PERI_SCLK_PCM1         58
+#define PERI_SCLK_UART2                59
+#define PERI_SCLK_UART1                60
+#define PERI_SCLK_UART0                61
+#define PERI_NR_CLK            62
+
+/* List Of Clocks For CMU_DISP */
+#define DISP_CLK_SMMU_TV       1
+#define DISP_CLK_SMMU_FIMD1M1  2
+#define DISP_CLK_SMMU_FIMD1M0  3
+#define DISP_CLK_MIXER         4
+#define DISP_CLK_MIPIPHY       5
+#define DISP_CLK_HDMIPHY       6
+#define DISP_CLK_HDMI          7
+#define DISP_CLK_FIMD1         8
+#define DISP_CLK_DSIM1         9
+#define DISP_CLK_DPPHY         10
+#define DISP_CLK_DP            11
+#define DISP_SCLK_PIXEL                12
+#define DISP_MOUT_HDMI_PHY_PIXEL_USER          13
+#define DISP_MOUT_HDMI_PHY_PIXEL       14
+#define DISP_NR_CLK            15
+
+/* List Of Clocks For CMU_G2D */
+#define G2D_CLK_SMMU3_JPEG     1
+#define G2D_CLK_MDMA           2
+#define G2D_CLK_JPEG           3
+#define G2D_CLK_G2D            4
+#define G2D_CLK_SSS            5
+#define G2D_CLK_SLIM_SSS       6
+#define G2D_CLK_SMMU_SLIM_SSS  7
+#define G2D_CLK_SMMU_SSS       8
+#define G2D_CLK_SMMU_MDMA      9
+#define G2D_CLK_SMMU3_G2D      10
+#define G2D_NR_CLK             11
+
+/* List Of Clocks For CMU_ISP */
+#define ISP_CLK_GIC            1
+#define ISP_CLK_WDT            2
+#define ISP_CLK_UART           3
+#define ISP_CLK_SPI1           4
+#define ISP_CLK_SPI0           5
+#define ISP_CLK_SMMU_SCALERP   6
+#define ISP_CLK_SMMU_SCALERC   7
+#define ISP_CLK_SMMU_ISPCX     8
+#define ISP_CLK_SMMU_ISP       9
+#define ISP_CLK_SMMU_FD                10
+#define ISP_CLK_SMMU_DRC       11
+#define ISP_CLK_PWM            12
+#define ISP_CLK_MTCADC         13
+#define ISP_CLK_MPWM           14
+#define ISP_CLK_MCUCTL         15
+#define ISP_CLK_I2C1           16
+#define ISP_CLK_I2C0           17
+#define ISP_CLK_FIMC_SCALERP   18
+#define ISP_CLK_FIMC_SCALERC   19
+#define ISP_CLK_FIMC           20
+#define ISP_CLK_FIMC_FD                21

include/dt-bindings/clock/exynos5260-clk.h line 233

Quoted 8 lines

include/dt-bindings/clock/exynos5260-clk.h new file +8 -0

+#define ISP_CLK_FIMC_DRC       22
+#define ISP_CLK_CA5            23
+#define ISP_SCLK_SPI0_EXT      24
+#define ISP_SCLK_SPI1_EXT      25
+#define ISP_SCLK_UART_EXT      26
+#define ISP_NR_CLK             27
+
+#endif

--
Best Regards,
Pankaj Dubey

Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.

Signed-off-by Rahul Sharma <[email protected]>

---
  .../devicetree/bindings/clock/exynos5260-clock.txt |   55 +++++
  include/dt-bindings/clock/exynos5260-clk.h         |  233 ++++++++++++++++++++
  2 files changed, 288 insertions(+)

create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 include/dt-bindings/clock/exynos5260-clk.h

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +0 -0

new file mode 100644
index 0000000..4128892

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +8 -0

+the Exynos5260 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+	"exynos5260-clock-top"
+	"exynos5260-clock-peri"
+	"exynos5260-clock-egl"

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +17 -0

+		reg = <0x14550000 0x10000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the
+		peri clock controller. Refer to the standard clock bindings for
+		information about 'clocks' and 'clock-names' property.
+
+	serial at 12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 146 0>;
+		clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+

include/dt-bindings/clock/exynos5260-clk.h new file +24 -0

new file mode 100644
index 0000000..d6f4391
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/*
+ * Clock names:	XXXXX_YYYYYY_ZZZZ
+ *		|---| |----| |--|
+ *		 cmu   type   IP
+ */
+
+/* List Of Clocks For CMU_TOP */
+#define FIN_PLL			1
+#define TOP_FOUT_DISP_PLL	2
+#define TOP_FOUT_AUD_PLL	3
+#define TOP_SCLK_MMC0		4

Add support for exynos5260 clocks in clock driver.

Signed-off-by Rahul Sharma <[email protected]>

Signed-off-by Pankaj Dubey <[email protected]>

---
  drivers/clk/samsung/Makefile         |    1 +
  drivers/clk/samsung/clk-exynos5260.c | 1805 ++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-exynos5260.h |  448 +++++++++
  3 files changed, 2254 insertions(+)

create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h

drivers/clk/samsung/clk-exynos5260.c new file +0 -0

new file mode 100644
index 0000000..f72ad6a

drivers/clk/samsung/clk-exynos5260.c new file +5 -0

+struct samsung_gate_clock aud_gate_clks[] __initdata = {
+	GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
+			EN_IP_AUD, 4, 0, 0),
+	GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
+	GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),

drivers/clk/samsung/clk-exynos5260.c new file +25 -0

+struct samsung_gate_clock disp_gate_clks[] __initdata = {
+	GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 25, 0, 0),
+	GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
+			"mout_aclk_disp_222_user",
+			EN_IP_DISP, 23, 0, 0),
+	GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
+			"mout_aclk_disp_222_user",
+			EN_IP_DISP, 22, 0, 0),
+	GATE(0, "clk_pixel_mixer", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(0, "clk_pixel_disp", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 11, 0, 0),
+	GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 10, 0, 0),
+	GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 9, 0, 0),
+	GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 8, 0, 0),
+	GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 7, 0, 0),
+	GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
+			EN_IP_DISP, 6, 0, 0),

drivers/clk/samsung/clk-exynos5260.c new file +19 -0

+struct samsung_gate_clock fsys_gate_clks[] __initdata = {
+	GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 20, 0, 0),
+	GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 18, 0, 0),
+	GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 15, 0, 0),
+	GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 14, 0, 0),
+	GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 13, 0, 0),
+	GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 9, 0, 0),
+	GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 8, 0, 0),
+	GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 7, 0, 0),
+	GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
+			EN_IP_FSYS, 6, 0, 0),

drivers/clk/samsung/clk-exynos5260.c new file +40 -0

+struct samsung_gate_clock gscl_gate_clks[] __initdata = {
+	GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 9, 0, 0),
+	GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 8, 0, 0),
+	GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 5, 0, 0),
+	GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 4, 0, 0),
+	GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 3, 0, 0),
+	GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333",
+			EN_IP_GSCL, 2, 0, 0),
+	GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 12, 0, 0),
+	GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 11, 0, 0),
+	GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 10, 0, 0),
+	GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 9, 0, 0),
+	GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 8, 0, 0),
+	GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 7, 0, 0),
+	GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 6, 0, 0),
+	GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
+			"mout_aclk_gscl_fimc_user",
+			EN_IP_GSCL_FIMC, 5, 0, 0),
+	GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
+			"mout_aclk_gscl_333",
+			EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
+	GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333",
+			EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),

drivers/clk/samsung/clk-exynos5260.c new file +47 -0

+struct samsung_gate_clock isp_gate_clks[] __initdata = {
+	GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
+			EN_IP_ISP0, 15, 0, 0),
+	GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 31, 0, 0),
+	GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 30, 0, 0),
+	GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 28, 0, 0),
+	GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 27, 0, 0),
+	GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 26, 0, 0),
+	GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 25, 0, 0),
+	GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 24, 0, 0),
+	GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 23, 0, 0),
+	GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 22, 0, 0),
+	GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 21, 0, 0),
+	GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 14, 0, 0),
+	GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 11, 0, 0),
+	GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 10, 0, 0),
+	GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 9, 0, 0),
+	GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 8, 0, 0),
+	GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 7, 0, 0),
+	GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 6, 0, 0),
+	GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
+			"mout_aclk_isp1_266",
+			EN_IP_ISP1, 5, 0, 0),
+	GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 4, 0, 0),
+	GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
+			EN_IP_ISP1, 3, 0, 0),

drivers/clk/samsung/clk-exynos5260.c new file +16 -0

+struct samsung_gate_clock mif_gate_clks[] __initdata = {
+	GATE(0, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
+			EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
+			EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(0, "clk_monocnt", "dout_aclk_bus_100",
+			EN_IP_MIF_SECURE_MONOCNT, 22,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(0, "clk_mif_rtc", "dout_aclk_bus_100",
+			EN_IP_MIF_SECURE_RTC_APBIF, 23,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(0, "clk_drex1", "dout_aclk_mif_466",
+			EN_IP_MIF_SECURE_DREX1_TZ, 9,
+			CLK_IGNORE_UNUSED, 0),
+	GATE(0, "clk_drex0", "dout_aclk_mif_466",
+			EN_IP_MIF_SECURE_DREX0_TZ, 9,

+struct samsung_gate_clock peri_gate_clks[] __initdata = {

drivers/clk/samsung/clk-exynos5260.c new file +15 -0

+		EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
+	GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
+	GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
+	GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
+		EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
+	GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
+			EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
+	GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
+			EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
+	GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
+			EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
+	GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
+			EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),

drivers/clk/samsung/clk-exynos5260.c new file +42 -0

+struct samsung_mux_clock top_mux_clks[] __initdata = {
+	MUX(0, "mout_audtop_pll_user", mout_audtop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 24, 1),
+	MUX(0, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP_PLL0, 16, 1),
+	MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+			MUX_SEL_TOP_PLL0, 12, 1),
+	MUX(0, "mout_bustop_pll_user", mout_bustop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 8, 1),
+	MUX(0, "mout_memtop_pll_user", mout_memtop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 4, 1),
+	MUX(0, "mout_mediatop_pll_user", mout_mediatop_pll_user_p,
+			MUX_SEL_TOP_PLL0, 0, 1),
+	MUX(0, "mout_disp_disp_333", mout_disp_disp_333_p,
+			MUX_SEL_TOP_DISP0, 0, 1),
+	MUX(0, "mout_aclk_disp_333", mout_aclk_disp_333_p,
+			MUX_SEL_TOP_DISP0, 8, 1),
+	MUX(0, "mout_disp_disp_222", mout_disp_disp_222_p,
+			MUX_SEL_TOP_DISP0, 12, 1),
+	MUX(0, "mout_aclk_disp_222", mout_aclk_disp_222_p,
+			MUX_SEL_TOP_DISP0, 20, 1),
+	MUX(0, "mout_disp_media_pixel", mout_disp_media_pixel_p,
+			MUX_SEL_TOP_DISP1, 8, 1),
+	MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
+			MUX_SEL_TOP_DISP1, 0, 1),
+	MUX(0, "mout_sclk_peri_spi0_clk", mout_sclk_peri_spi_clk_p,
+			MUX_SEL_TOP_PERI1, 8, 1),
+	MUX(0, "mout_sclk_peri_spi1_clk", mout_sclk_peri_spi_clk_p,
+			MUX_SEL_TOP_PERI1, 4, 1),
+	MUX(0, "mout_sclk_peri_spi2_clk", mout_sclk_peri_spi_clk_p,
+			MUX_SEL_TOP_PERI1, 0, 1),
+	MUX(0, "mout_sclk_peri_uart0_uclk", mout_sclk_peri_uart_uclk_p,
+			MUX_SEL_TOP_PERI1, 20, 1),
+	MUX(0, "mout_sclk_peri_uart2_uclk", mout_sclk_peri_uart_uclk_p,
+			MUX_SEL_TOP_PERI1, 16, 1),
+	MUX(0, "mout_sclk_peri_uart1_uclk", mout_sclk_peri_uart_uclk_p,
+			MUX_SEL_TOP_PERI1, 12, 1),
+	MUX(0, "mout_bus4_bustop_100", mout_bus_bustop_100_p,
+			MUX_SEL_TOP_BUS, 28, 1),
+	MUX(0, "mout_bus4_bustop_400", mout_bus_bustop_400_p,
+			MUX_SEL_TOP_BUS, 24, 1),
+	MUX(0, "mout_bus3_bustop_100", mout_bus_bustop_100_p,
+			MUX_SEL_TOP_BUS, 20, 1),

drivers/clk/samsung/clk-exynos5260.c new file +30 -0

+	MUX(0, "mout_sclk_fsys_usb", mout_sclk_fsys_usb_p,
+			MUX_SEL_TOP_FSYS, 0, 1),
+	MUX(0, "mout_sclk_fsys_mmc0_sdclkin_a",
+			mout_sclk_fsys_mmc_sdclkin_a_p,
+			MUX_SEL_TOP_FSYS, 20, 1),
+	MUX(0, "mout_sclk_fsys_mmc1_sdclkin_a",
+			mout_sclk_fsys_mmc_sdclkin_a_p,
+			MUX_SEL_TOP_FSYS, 12, 1),
+	MUX(0, "mout_sclk_fsys_mmc2_sdclkin_a",
+			mout_sclk_fsys_mmc_sdclkin_a_p,
+			MUX_SEL_TOP_FSYS, 4, 1),
+	MUX(0, "mout_sclk_fsys_mmc0_sdclkin_b",
+			mout_sclk_fsys_mmc0_sdclkin_b_p,
+			MUX_SEL_TOP_FSYS, 24, 1),
+	MUX(0, "mout_sclk_fsys_mmc1_sdclkin_b",
+			mout_sclk_fsys_mmc1_sdclkin_b_p,
+			MUX_SEL_TOP_FSYS, 16, 1),
+	MUX(0, "mout_sclk_fsys_mmc2_sdclkin_b",
+			mout_sclk_fsys_mmc2_sdclkin_b_p,
+			MUX_SEL_TOP_FSYS, 8, 1),
+	MUX(0, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
+			MUX_SEL_TOP_ISP10, 20, 1),
+	MUX(0, "mout_isp1_media_266", mout_isp1_media_266_p,
+			MUX_SEL_TOP_ISP10, 16, 1),
+	MUX(0, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
+			MUX_SEL_TOP_ISP10, 8 , 1),
+	MUX(0, "mout_isp1_media_400", mout_isp1_media_400_p,
+			MUX_SEL_TOP_ISP10, 4, 1),
+	MUX(0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
+			MUX_SEL_TOP_ISP11, 4, 1),

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+	MUX(0, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
+			MUX_SEL_TOP_MFC, 8, 1),
+	MUX(0, "mout_mfc_bustop_333", mout_mfc_bustop_333_p,
+			MUX_SEL_TOP_MFC, 4, 1),
+	MUX(0, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
+			MUX_SEL_TOP_G2D, 8, 1),
+	MUX(0, "mout_g2d_bustop_333", mout_g2d_bustop_333_p,
+			MUX_SEL_TOP_G2D, 4, 1),
+	MUX(0, "mout_aclk_gscl_fimc", mout_aclk_gscl_fimc_p,
+			MUX_SEL_TOP_GSCL, 20, 1),

drivers/clk/samsung/clk-exynos5260.c new file +30 -0

+	DIV(0, "dout_sclk_isp1_sensor2_a", "mout_aclk_gscl_fimc",
+			DIV_TOP_GSCL_ISP0, 24, 4),
+	DIV(0, "dout_sclk_isp1_sensor1_a", "mout_aclk_gscl_400",
+			DIV_TOP_GSCL_ISP0, 20, 4),
+	DIV(0, "dout_sclk_isp1_sensor0_a", "mout_aclk_gscl_fimc",
+			DIV_TOP_GSCL_ISP0, 16, 4),
+	DIV(0, "dout_aclk_gscl_fimc", "mout_aclk_gscl_fimc",
+			DIV_TOP_GSCL_ISP0, 8, 3),
+	DIV(0, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
+			DIV_TOP_GSCL_ISP0, 4, 3),
+	DIV(0, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
+			DIV_TOP_GSCL_ISP0, 0, 3),
+	DIV(0, "dout_sclk_isp1_spi0_b", "dout_sclk_isp1_spi0_a",
+			DIV_TOP_ISP10, 16, 8),
+	DIV(0, "dout_sclk_isp1_spi0_a", "mout_sclk_isp1_spi0",
+			DIV_TOP_ISP10, 12, 4),
+	DIV(0, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
+			DIV_TOP_ISP10, 4, 3),
+	DIV(0, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
+			DIV_TOP_ISP10, 0, 3),
+	DIV(0, "dout_sclk_isp1_uart", "mout_sclk_isp1_uart",
+			DIV_TOP_ISP11, 12, 4),
+	DIV(0, "dout_sclk_isp1_spi1_b", "dout_sclk_isp1_spi1_a",
+			DIV_TOP_ISP11, 4, 8),
+	DIV(0, "dout_sclk_isp1_spi1_a", "mout_sclk_isp1_spi1",
+			DIV_TOP_ISP11, 0, 4),
+	DIV(0, "dout_sclk_isp1_sensor2_b", "dout_sclk_isp1_sensor2_a",
+			DIV_TOP_ISP11, 24, 4),
+	DIV(0, "dout_sclk_isp1_sensor1_b", "dout_sclk_isp1_sensor1_a",
+			DIV_TOP_ISP11, 20, 4),

drivers/clk/samsung/clk-exynos5260.c new file +58 -0

+	DIV(0, "dout_aclk_bus4_100", "mout_bus4_bustop_100",
+			DIV_TOP_BUS, 28, 4),
+	DIV(0, "dout_aclk_bus4_400", "mout_bus4_bustop_400",
+			DIV_TOP_BUS, 24, 3),
+	DIV(0, "dout_aclk_bus3_100", "mout_bus3_bustop_100",
+			DIV_TOP_BUS, 20, 4),
+	DIV(0, "dout_aclk_bus3_400", "mout_bus3_bustop_400",
+			DIV_TOP_BUS, 16, 3),
+	DIV(0, "dout_aclk_bus2_100", "mout_bus2_bustop_100",
+			DIV_TOP_BUS, 12, 4),
+	DIV(0, "dout_aclk_bus2_400", "mout_bus2_bustop_400",
+			DIV_TOP_BUS, 8, 3),
+	DIV(0, "dout_aclk_bus1_100", "mout_bus1_bustop_100",
+			DIV_TOP_BUS, 4, 4),
+	DIV(0, "dout_aclk_bus1_400", "mout_bus1_bustop_400",
+			DIV_TOP_BUS, 0, 3),
+	DIV(0, "dout_sclk_peri_spi1_b", "dout_sclk_peri_spi1_a",
+			DIV_TOP_PERI0, 20, 8),
+	DIV(0, "dout_sclk_peri_spi1_a", "mout_sclk_peri_spi1_clk",
+			DIV_TOP_PERI0, 16, 4),
+	DIV(0, "dout_sclk_peri_spi0_b", "dout_sclk_peri_spi0_a",
+			DIV_TOP_PERI0, 8, 8),
+	DIV(0, "dout_sclk_peri_spi0_a", "mout_sclk_peri_spi0_clk",
+			DIV_TOP_PERI0, 4, 4),
+	DIV(0, "dout_sclk_peri_uart0", "mout_sclk_peri_uart0_uclk",
+			DIV_TOP_PERI1, 24, 4),
+	DIV(0, "dout_sclk_peri_uart2", "mout_sclk_peri_uart2_uclk",
+			DIV_TOP_PERI1, 20, 4),
+	DIV(0, "dout_sclk_peri_uart1", "mout_sclk_peri_uart1_uclk",
+			DIV_TOP_PERI1, 16, 4),
+	DIV(0, "dout_sclk_peri_spi2_b", "dout_sclk_peri_spi2_a",
+			DIV_TOP_PERI1, 4, 8),
+	DIV(0, "dout_sclk_peri_spi2_a", "mout_sclk_peri_spi2_clk",
+			DIV_TOP_PERI1, 0, 4),
+	DIV(0, "dout_aclk_peri_aud", "mout_audtop_pll_user",
+			DIV_TOP_PERI2, 24, 3),
+	DIV(0, "dout_aclk_peri_66", "mout_bustop_pll_user",
+			DIV_TOP_PERI2, 20, 4),
+	DIV(0, "dout_sclk_fsys_mmc0_sdclkin_b",
+			"dout_sclk_fsys_mmc0_sdclkin_a",
+			DIV_TOP_FSYS0, 16, 8),
+	DIV(0, "dout_sclk_fsys_mmc0_sdclkin_a",
+			"mout_sclk_fsys_mmc0_sdclkin_b",
+			DIV_TOP_FSYS0, 12, 4),
+	DIV(0, "dout_sclk_fsys_usbdrd30_suspend_clk",
+			"mout_sclk_fsys_usb",
+			DIV_TOP_FSYS0, 4, 4),
+	DIV(0, "dout_aclk_fsys_200", "mout_bustop_pll_user",
+			DIV_TOP_FSYS0, 0, 3),
+
+	DIV(0, "dout_sclk_fsys_mmc2_sdclkin_b",
+			"dout_sclk_fsys_mmc2_sdclkin_a",
+			DIV_TOP_FSYS1, 16, 8),
+	DIV(0, "dout_sclk_fsys_mmc2_sdclkin_a",
+			"mout_sclk_fsys_mmc2_sdclkin_b",
+			DIV_TOP_FSYS1, 12, 4),
+	DIV(0, "dout_sclk_fsys_mmc1_sdclkin_b",
+			"dout_sclk_fsys_mmc1_sdclkin_a",

drivers/clk/samsung/clk-exynos5260.c new file +11 -0

+	GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
+			"dout_sclk_fsys_mmc2_sdclkin_b",
+			EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
+	GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
+			"dout_sclk_fsys_mmc1_sdclkin_b",
+			EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT,
+			0),
+	GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
+			"dout_sclk_fsys_mmc0_sdclkin_b",
+			EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
+};

drivers/clk/samsung/clk-exynos5260.h new file +0 -0

new file mode 100644
index 0000000..7c3717a

Quoted 13 lines · Rahul Sharma

Add support for exynos5260 clocks in clock driver.

Signed-off-by Rahul Sharma <[email protected]>

Signed-off-by Pankaj Dubey <[email protected]>

---
  drivers/clk/samsung/Makefile         |    1 +
  drivers/clk/samsung/clk-exynos5260.c | 1805
++++++++++++++++++++++++++++++++++
  drivers/clk/samsung/clk-exynos5260.h |  448 +++++++++
  3 files changed, 2254 insertions(+)

create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h

[snip]

Quoted 6 lines

drivers/clk/samsung/clk-exynos5260.c new file +0 -0

new file mode 100644
index 0000000..f72ad6a

[snip]

Quoted 7 lines

drivers/clk/samsung/clk-exynos5260.c new file +4 -0

+struct samsung_gate_clock aud_gate_clks[] __initdata = {
+       GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
+                       EN_IP_AUD, 4, 0, 0),
+       GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0,

0),
+ GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0,
0),

drivers/clk/samsung/clk-exynos5260.c line 255

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
+                       EN_IP_AUD, 1, 0, 0),
+       GATE(0, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD, 0, 0, 0),
+
+       GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
+                       EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
+                       EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
+                       EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),

Please keep the clocks sorted by the register offsets ascending as well, to match the order in UM.

[snip]

drivers/clk/samsung/clk-exynos5260.c line 344

Quoted 8 lines

drivers/clk/samsung/clk-exynos5260.c new file +8 -0

+
+struct samsung_mux_clock disp_mux_clks[] __initdata = {
+       MUX(0, "mout_sclk_hdmi_spdif", mout_sclk_hdmi_spdif_p,
+                       MUX_SEL_DISP4, 4, 2),
+
+       MUX(0, "mout_sclk_dsim1_tx_clk_esc_clk_user",
+                       mout_sclk_dsim1_tx_clk_esc_clk_user_p,
+                       MUX_SEL_DISP2, 28, 1),

Ditto.

[snip]

Quoted 25 lines

drivers/clk/samsung/clk-exynos5260.c new file +25 -0

+struct samsung_gate_clock disp_gate_clks[] __initdata = {
+       GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 25, 0, 0),
+       GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
+                       "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 23, 0, 0),
+       GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
+                       "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 22, 0, 0),
+       GATE(0, "clk_pixel_mixer", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
+       GATE(0, "clk_pixel_disp", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
+       GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 11, 0, 0),
+       GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 10, 0, 0),
+       GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 9, 0, 0),
+       GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 8, 0, 0),
+       GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 7, 0, 0),
+       GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 6, 0, 0),

drivers/clk/samsung/clk-exynos5260.c line 446

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 5, 0, 0),
+       GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
+                       EN_IP_DISP, 4, 0, 0),
+       GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
+                       "dout_sclk_hdmi_phy_pixel_clki",
+                       EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
+       GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
+                       "mout_phyclk_hdmi_phy_pixel_clko_user",
+                       EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),

Ditto.

[snip]

Quoted 19 lines

drivers/clk/samsung/clk-exynos5260.c new file +19 -0

+struct samsung_gate_clock fsys_gate_clks[] __initdata = {
+       GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 20, 0, 0),
+       GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 18, 0, 0),
+       GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 15, 0, 0),
+       GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 14, 0, 0),
+       GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 13, 0, 0),
+       GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 9, 0, 0),
+       GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 8, 0, 0),
+       GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 7, 0, 0),
+       GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
+                       EN_IP_FSYS, 6, 0, 0),

drivers/clk/samsung/clk-exynos5260.c line 602

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       GATE(FSYS_CLK_RTIC, "clk_rtic", "mout_bustop_pll_user",
+                       EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
+       GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "mout_bustop_pll_user",
+                       EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
+       GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
+                       "mout_phyclk_usbdrd30_phyclock_user",
+                       EN_SCLK_FSYS, 7, 0, 0),
+       GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
+                       "mout_phyclk_usbdrd30_phyclock_user",
+                       EN_SCLK_FSYS, 1, 0, 0),

Ditto.

[snip]

Quoted 53 lines

drivers/clk/samsung/clk-exynos5260.c new file +2 -0

+struct samsung_gate_clock gscl_gate_clks[] __initdata = {
+       GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",

"mout_aclk_gscl_333",

drivers/clk/samsung/clk-exynos5260.c new file +2 -0

+                       EN_IP_GSCL, 9, 0, 0),
+       GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",

"mout_aclk_gscl_333",

drivers/clk/samsung/clk-exynos5260.c new file +35 -0

+                       EN_IP_GSCL, 8, 0, 0),
+       GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333",
+                       EN_IP_GSCL, 5, 0, 0),
+       GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333",
+                       EN_IP_GSCL, 4, 0, 0),
+       GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333",
+                       EN_IP_GSCL, 3, 0, 0),
+       GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333",
+                       EN_IP_GSCL, 2, 0, 0),
+       GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
+                       "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 12, 0, 0),
+       GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
+                       "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 11, 0, 0),
+       GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
+                       "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 10, 0, 0),
+       GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 9, 0, 0),
+       GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 8, 0, 0),
+       GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
+                       "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 7, 0, 0),
+       GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
+                       "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 6, 0, 0),
+       GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
+                       "mout_aclk_gscl_fimc_user",
+                       EN_IP_GSCL_FIMC, 5, 0, 0),
+       GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
+                       "mout_aclk_gscl_333",
+                       EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
+       GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1",

"mout_aclk_gscl_333",

drivers/clk/samsung/clk-exynos5260.c new file +8 -0

+                       EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
+       GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
+                       "mout_aclk_m2m_400_user",
+                       EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
+       GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
+                       "mout_aclk_m2m_400_user",
+                       EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
+       GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap",

"dout_aclk_csis_200",

drivers/clk/samsung/clk-exynos5260.c new file +2 -0

+                       EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
+       GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap",

Quoted 2 lines

"dout_aclk_csis_200",
+ EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),

Ditto.

[snip]

Quoted 47 lines

drivers/clk/samsung/clk-exynos5260.c new file +47 -0

+struct samsung_gate_clock isp_gate_clks[] __initdata = {
+       GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
+                       EN_IP_ISP0, 15, 0, 0),
+       GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 31, 0, 0),
+       GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 30, 0, 0),
+       GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 28, 0, 0),
+       GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 27, 0, 0),
+       GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
+                       "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 26, 0, 0),
+       GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
+                       "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 25, 0, 0),
+       GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 24, 0, 0),
+       GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 23, 0, 0),
+       GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 22, 0, 0),
+       GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 21, 0, 0),
+       GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 14, 0, 0),
+       GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 11, 0, 0),
+       GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 10, 0, 0),
+       GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 9, 0, 0),
+       GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 8, 0, 0),
+       GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 7, 0, 0),
+       GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
+                       "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 6, 0, 0),
+       GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
+                       "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 5, 0, 0),
+       GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 4, 0, 0),
+       GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 3, 0, 0),

drivers/clk/samsung/clk-exynos5260.c line 981

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 2, 0, 0),
+       GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
+                       EN_IP_ISP1, 1, 0, 0),
+       GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
+                       EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
+       GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
+                       EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
+       GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
+                       EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),

Ditto.

[snip]

Quoted 16 lines

drivers/clk/samsung/clk-exynos5260.c new file +16 -0

+struct samsung_gate_clock mif_gate_clks[] __initdata = {
+       GATE(0, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
+                       EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
+       GATE(0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
+                       EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
+       GATE(0, "clk_monocnt", "dout_aclk_bus_100",
+                       EN_IP_MIF_SECURE_MONOCNT, 22,
+                       CLK_IGNORE_UNUSED, 0),
+       GATE(0, "clk_mif_rtc", "dout_aclk_bus_100",
+                       EN_IP_MIF_SECURE_RTC_APBIF, 23,
+                       CLK_IGNORE_UNUSED, 0),
+       GATE(0, "clk_drex1", "dout_aclk_mif_466",
+                       EN_IP_MIF_SECURE_DREX1_TZ, 9,
+                       CLK_IGNORE_UNUSED, 0),
+       GATE(0, "clk_drex0", "dout_aclk_mif_466",
+                       EN_IP_MIF_SECURE_DREX0_TZ, 9,

drivers/clk/samsung/clk-exynos5260.c line 1212

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+                       CLK_IGNORE_UNUSED, 0),
+       GATE(0, "clk_intmem", "dout_aclk_bus_200",
+                       EN_IP_MIF_SECURE_INTEMEM, 11,
+                       CLK_IGNORE_UNUSED, 0),
+       GATE(0, "sclk_lpddr3phy_wrap_u1", "dout_clkm_phy",
+                       EN_SCLK_MIF, 0, CLK_IGNORE_UNUSED |
+                               CLK_SET_RATE_PARENT, 0),
+       GATE(0, "sclk_lpddr3phy_wrap_u0", "dout_clkm_phy",
+                       EN_SCLK_MIF, 0, CLK_IGNORE_UNUSED |
+                               CLK_SET_RATE_PARENT, 0),

Ditto.

[snip]

Quoted 1 line

+struct samsung_gate_clock peri_gate_clks[] __initdata = {

[snip]

Quoted 15 lines

drivers/clk/samsung/clk-exynos5260.c new file +15 -0

+               EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
+       GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
+               EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
+       GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
+               EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
+       GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
+               EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
+       GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
+                       EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
+       GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
+                       EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
+       GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
+                       EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
+       GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
+                       EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),

drivers/clk/samsung/clk-exynos5260.c line 1424

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
+                       EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
+       GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
+                       EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
+       GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
+                       EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
+       GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
+                       CLK_SET_RATE_PARENT, 0),
+       GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
+                       CLK_SET_RATE_PARENT, 0),

Ditto.

[snip]

Quoted 43 lines

drivers/clk/samsung/clk-exynos5260.c new file +23 -0

+struct samsung_mux_clock top_mux_clks[] __initdata = {
+       MUX(0, "mout_audtop_pll_user", mout_audtop_pll_user_p,
+                       MUX_SEL_TOP_PLL0, 24, 1),
+       MUX(0, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP_PLL0, 16, 1),
+       MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
+                       MUX_SEL_TOP_PLL0, 12, 1),
+       MUX(0, "mout_bustop_pll_user", mout_bustop_pll_user_p,
+                       MUX_SEL_TOP_PLL0, 8, 1),
+       MUX(0, "mout_memtop_pll_user", mout_memtop_pll_user_p,
+                       MUX_SEL_TOP_PLL0, 4, 1),
+       MUX(0, "mout_mediatop_pll_user", mout_mediatop_pll_user_p,
+                       MUX_SEL_TOP_PLL0, 0, 1),
+       MUX(0, "mout_disp_disp_333", mout_disp_disp_333_p,
+                       MUX_SEL_TOP_DISP0, 0, 1),
+       MUX(0, "mout_aclk_disp_333", mout_aclk_disp_333_p,
+                       MUX_SEL_TOP_DISP0, 8, 1),
+       MUX(0, "mout_disp_disp_222", mout_disp_disp_222_p,
+                       MUX_SEL_TOP_DISP0, 12, 1),
+       MUX(0, "mout_aclk_disp_222", mout_aclk_disp_222_p,
+                       MUX_SEL_TOP_DISP0, 20, 1),
+       MUX(0, "mout_disp_media_pixel", mout_disp_media_pixel_p,
+                       MUX_SEL_TOP_DISP1, 8, 1),
+       MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel",

mout_sclk_disp_pixel_p,

drivers/clk/samsung/clk-exynos5260.c new file +19 -0

+                       MUX_SEL_TOP_DISP1, 0, 1),
+       MUX(0, "mout_sclk_peri_spi0_clk", mout_sclk_peri_spi_clk_p,
+                       MUX_SEL_TOP_PERI1, 8, 1),
+       MUX(0, "mout_sclk_peri_spi1_clk", mout_sclk_peri_spi_clk_p,
+                       MUX_SEL_TOP_PERI1, 4, 1),
+       MUX(0, "mout_sclk_peri_spi2_clk", mout_sclk_peri_spi_clk_p,
+                       MUX_SEL_TOP_PERI1, 0, 1),
+       MUX(0, "mout_sclk_peri_uart0_uclk", mout_sclk_peri_uart_uclk_p,
+                       MUX_SEL_TOP_PERI1, 20, 1),
+       MUX(0, "mout_sclk_peri_uart2_uclk", mout_sclk_peri_uart_uclk_p,
+                       MUX_SEL_TOP_PERI1, 16, 1),
+       MUX(0, "mout_sclk_peri_uart1_uclk", mout_sclk_peri_uart_uclk_p,
+                       MUX_SEL_TOP_PERI1, 12, 1),
+       MUX(0, "mout_bus4_bustop_100", mout_bus_bustop_100_p,
+                       MUX_SEL_TOP_BUS, 28, 1),
+       MUX(0, "mout_bus4_bustop_400", mout_bus_bustop_400_p,
+                       MUX_SEL_TOP_BUS, 24, 1),
+       MUX(0, "mout_bus3_bustop_100", mout_bus_bustop_100_p,
+                       MUX_SEL_TOP_BUS, 20, 1),

drivers/clk/samsung/clk-exynos5260.c line 1588

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       MUX(0, "mout_bus3_bustop_400", mout_bus_bustop_400_p,
+                       MUX_SEL_TOP_BUS, 16, 1),
+       MUX(0, "mout_bus2_bustop_400", mout_bus_bustop_400_p,
+                       MUX_SEL_TOP_BUS, 12, 1),
+       MUX(0, "mout_bus2_bustop_100", mout_bus_bustop_100_p,
+                       MUX_SEL_TOP_BUS, 8, 1),
+       MUX(0, "mout_bus1_bustop_100", mout_bus_bustop_100_p,
+                       MUX_SEL_TOP_BUS, 4, 1),
+       MUX(0, "mout_bus1_bustop_400", mout_bus_bustop_400_p,
+                       MUX_SEL_TOP_BUS, 0, 1),

Ditto.

Quoted 30 lines

drivers/clk/samsung/clk-exynos5260.c new file +30 -0

+       MUX(0, "mout_sclk_fsys_usb", mout_sclk_fsys_usb_p,
+                       MUX_SEL_TOP_FSYS, 0, 1),
+       MUX(0, "mout_sclk_fsys_mmc0_sdclkin_a",
+                       mout_sclk_fsys_mmc_sdclkin_a_p,
+                       MUX_SEL_TOP_FSYS, 20, 1),
+       MUX(0, "mout_sclk_fsys_mmc1_sdclkin_a",
+                       mout_sclk_fsys_mmc_sdclkin_a_p,
+                       MUX_SEL_TOP_FSYS, 12, 1),
+       MUX(0, "mout_sclk_fsys_mmc2_sdclkin_a",
+                       mout_sclk_fsys_mmc_sdclkin_a_p,
+                       MUX_SEL_TOP_FSYS, 4, 1),
+       MUX(0, "mout_sclk_fsys_mmc0_sdclkin_b",
+                       mout_sclk_fsys_mmc0_sdclkin_b_p,
+                       MUX_SEL_TOP_FSYS, 24, 1),
+       MUX(0, "mout_sclk_fsys_mmc1_sdclkin_b",
+                       mout_sclk_fsys_mmc1_sdclkin_b_p,
+                       MUX_SEL_TOP_FSYS, 16, 1),
+       MUX(0, "mout_sclk_fsys_mmc2_sdclkin_b",
+                       mout_sclk_fsys_mmc2_sdclkin_b_p,
+                       MUX_SEL_TOP_FSYS, 8, 1),
+       MUX(0, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
+                       MUX_SEL_TOP_ISP10, 20, 1),
+       MUX(0, "mout_isp1_media_266", mout_isp1_media_266_p,
+                       MUX_SEL_TOP_ISP10, 16, 1),
+       MUX(0, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
+                       MUX_SEL_TOP_ISP10, 8 , 1),
+       MUX(0, "mout_isp1_media_400", mout_isp1_media_400_p,
+                       MUX_SEL_TOP_ISP10, 4, 1),
+       MUX(0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
+                       MUX_SEL_TOP_ISP11, 4, 1),

drivers/clk/samsung/clk-exynos5260.c line 1628

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       MUX(0, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
+                       MUX_SEL_TOP_ISP11, 8, 1),
+       MUX(0, "mout_sclk_isp1_uart", mout_sclk_isp_uart_p,
+                       MUX_SEL_TOP_ISP11, 12, 1),
+       MUX(0, "mout_sclk_isp1_sensor2", mout_sclk_isp_sensor_p,
+                       MUX_SEL_TOP_ISP11, 24, 1),
+       MUX(0, "mout_sclk_isp1_sensor1", mout_sclk_isp_sensor_p,
+                       MUX_SEL_TOP_ISP11, 20, 1),
+       MUX(0, "mout_sclk_isp1_sensor0", mout_sclk_isp_sensor_p,
+                       MUX_SEL_TOP_ISP11, 16, 1),

Ditto.

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       MUX(0, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
+                       MUX_SEL_TOP_MFC, 8, 1),
+       MUX(0, "mout_mfc_bustop_333", mout_mfc_bustop_333_p,
+                       MUX_SEL_TOP_MFC, 4, 1),
+       MUX(0, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
+                       MUX_SEL_TOP_G2D, 8, 1),
+       MUX(0, "mout_g2d_bustop_333", mout_g2d_bustop_333_p,
+                       MUX_SEL_TOP_G2D, 4, 1),
+       MUX(0, "mout_aclk_gscl_fimc", mout_aclk_gscl_fimc_p,
+                       MUX_SEL_TOP_GSCL, 20, 1),

drivers/clk/samsung/clk-exynos5260.c line 1648

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       MUX(0, "mout_gscl_bustop_fimc", mout_gscl_bustop_fimc_p,
+                       MUX_SEL_TOP_GSCL, 16, 1),
+       MUX(0, "mout_aclk_gscl_333", mout_aclk_gscl_333_p,
+                       MUX_SEL_TOP_GSCL, 12, 1),
+       MUX(0, "mout_gscl_bustop_333", mout_gscl_bustop_333_p,
+                       MUX_SEL_TOP_GSCL, 8, 1),
+       MUX(0, "mout_aclk_gscl_400", mout_aclk_gscl_400_p,
+                       MUX_SEL_TOP_GSCL, 4, 1),
+       MUX(0, "mout_m2m_mediatop_400", mout_m2m_mediatop_400_p,
+                       MUX_SEL_TOP_GSCL, 0, 1),

Ditto.

drivers/clk/samsung/clk-exynos5260.c line 1655

Quoted 7 lines

drivers/clk/samsung/clk-exynos5260.c new file +7 -0

+};
+
+struct samsung_div_clock top_div_clks[] __initdata = {
+       DIV(0, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
+                       DIV_TOP_G2D_MFC, 4, 3),
+       DIV(0, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
+                       DIV_TOP_GSCL_ISP0, 0, 3),

This looks wrong. The register and bit field are the same as "dout_aclk_gscl_333" below.

Quoted 30 lines

drivers/clk/samsung/clk-exynos5260.c new file +30 -0

+       DIV(0, "dout_sclk_isp1_sensor2_a", "mout_aclk_gscl_fimc",
+                       DIV_TOP_GSCL_ISP0, 24, 4),
+       DIV(0, "dout_sclk_isp1_sensor1_a", "mout_aclk_gscl_400",
+                       DIV_TOP_GSCL_ISP0, 20, 4),
+       DIV(0, "dout_sclk_isp1_sensor0_a", "mout_aclk_gscl_fimc",
+                       DIV_TOP_GSCL_ISP0, 16, 4),
+       DIV(0, "dout_aclk_gscl_fimc", "mout_aclk_gscl_fimc",
+                       DIV_TOP_GSCL_ISP0, 8, 3),
+       DIV(0, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
+                       DIV_TOP_GSCL_ISP0, 4, 3),
+       DIV(0, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
+                       DIV_TOP_GSCL_ISP0, 0, 3),
+       DIV(0, "dout_sclk_isp1_spi0_b", "dout_sclk_isp1_spi0_a",
+                       DIV_TOP_ISP10, 16, 8),
+       DIV(0, "dout_sclk_isp1_spi0_a", "mout_sclk_isp1_spi0",
+                       DIV_TOP_ISP10, 12, 4),
+       DIV(0, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
+                       DIV_TOP_ISP10, 4, 3),
+       DIV(0, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
+                       DIV_TOP_ISP10, 0, 3),
+       DIV(0, "dout_sclk_isp1_uart", "mout_sclk_isp1_uart",
+                       DIV_TOP_ISP11, 12, 4),
+       DIV(0, "dout_sclk_isp1_spi1_b", "dout_sclk_isp1_spi1_a",
+                       DIV_TOP_ISP11, 4, 8),
+       DIV(0, "dout_sclk_isp1_spi1_a", "mout_sclk_isp1_spi1",
+                       DIV_TOP_ISP11, 0, 4),
+       DIV(0, "dout_sclk_isp1_sensor2_b", "dout_sclk_isp1_sensor2_a",
+                       DIV_TOP_ISP11, 24, 4),
+       DIV(0, "dout_sclk_isp1_sensor1_b", "dout_sclk_isp1_sensor1_a",
+                       DIV_TOP_ISP11, 20, 4),

drivers/clk/samsung/clk-exynos5260.c line 1695

Quoted 10 lines

drivers/clk/samsung/clk-exynos5260.c new file +10 -0

+       DIV(0, "dout_sclk_isp1_sensor0_b", "dout_sclk_isp1_sensor0_a",
+                       DIV_TOP_ISP11, 16, 4),
+       DIV(0, "dout_sclk_hpm_targetclk", "mout_bustop_pll_user",
+                       DIV_TOP_HPM, 0, 3),
+       DIV(0, "dout_sclk_disp_pixel", "mout_sclk_disp_pixel",
+                       DIV_TOP_DISP, 8, 3),
+       DIV(0, "dout_aclk_disp_222", "mout_aclk_disp_222",
+                       DIV_TOP_DISP, 4, 3),
+       DIV(0, "dout_aclk_disp_333", "mout_aclk_disp_333",
+                       DIV_TOP_DISP, 0, 3),

Sorting order.

Quoted 64 lines

drivers/clk/samsung/clk-exynos5260.c new file +64 -0

+       DIV(0, "dout_aclk_bus4_100", "mout_bus4_bustop_100",
+                       DIV_TOP_BUS, 28, 4),
+       DIV(0, "dout_aclk_bus4_400", "mout_bus4_bustop_400",
+                       DIV_TOP_BUS, 24, 3),
+       DIV(0, "dout_aclk_bus3_100", "mout_bus3_bustop_100",
+                       DIV_TOP_BUS, 20, 4),
+       DIV(0, "dout_aclk_bus3_400", "mout_bus3_bustop_400",
+                       DIV_TOP_BUS, 16, 3),
+       DIV(0, "dout_aclk_bus2_100", "mout_bus2_bustop_100",
+                       DIV_TOP_BUS, 12, 4),
+       DIV(0, "dout_aclk_bus2_400", "mout_bus2_bustop_400",
+                       DIV_TOP_BUS, 8, 3),
+       DIV(0, "dout_aclk_bus1_100", "mout_bus1_bustop_100",
+                       DIV_TOP_BUS, 4, 4),
+       DIV(0, "dout_aclk_bus1_400", "mout_bus1_bustop_400",
+                       DIV_TOP_BUS, 0, 3),
+       DIV(0, "dout_sclk_peri_spi1_b", "dout_sclk_peri_spi1_a",
+                       DIV_TOP_PERI0, 20, 8),
+       DIV(0, "dout_sclk_peri_spi1_a", "mout_sclk_peri_spi1_clk",
+                       DIV_TOP_PERI0, 16, 4),
+       DIV(0, "dout_sclk_peri_spi0_b", "dout_sclk_peri_spi0_a",
+                       DIV_TOP_PERI0, 8, 8),
+       DIV(0, "dout_sclk_peri_spi0_a", "mout_sclk_peri_spi0_clk",
+                       DIV_TOP_PERI0, 4, 4),
+       DIV(0, "dout_sclk_peri_uart0", "mout_sclk_peri_uart0_uclk",
+                       DIV_TOP_PERI1, 24, 4),
+       DIV(0, "dout_sclk_peri_uart2", "mout_sclk_peri_uart2_uclk",
+                       DIV_TOP_PERI1, 20, 4),
+       DIV(0, "dout_sclk_peri_uart1", "mout_sclk_peri_uart1_uclk",
+                       DIV_TOP_PERI1, 16, 4),
+       DIV(0, "dout_sclk_peri_spi2_b", "dout_sclk_peri_spi2_a",
+                       DIV_TOP_PERI1, 4, 8),
+       DIV(0, "dout_sclk_peri_spi2_a", "mout_sclk_peri_spi2_clk",
+                       DIV_TOP_PERI1, 0, 4),
+       DIV(0, "dout_aclk_peri_aud", "mout_audtop_pll_user",
+                       DIV_TOP_PERI2, 24, 3),
+       DIV(0, "dout_aclk_peri_66", "mout_bustop_pll_user",
+                       DIV_TOP_PERI2, 20, 4),
+       DIV(0, "dout_sclk_fsys_mmc0_sdclkin_b",
+                       "dout_sclk_fsys_mmc0_sdclkin_a",
+                       DIV_TOP_FSYS0, 16, 8),
+       DIV(0, "dout_sclk_fsys_mmc0_sdclkin_a",
+                       "mout_sclk_fsys_mmc0_sdclkin_b",
+                       DIV_TOP_FSYS0, 12, 4),
+       DIV(0, "dout_sclk_fsys_usbdrd30_suspend_clk",
+                       "mout_sclk_fsys_usb",
+                       DIV_TOP_FSYS0, 4, 4),
+       DIV(0, "dout_aclk_fsys_200", "mout_bustop_pll_user",
+                       DIV_TOP_FSYS0, 0, 3),
+
+       DIV(0, "dout_sclk_fsys_mmc2_sdclkin_b",
+                       "dout_sclk_fsys_mmc2_sdclkin_a",
+                       DIV_TOP_FSYS1, 16, 8),
+       DIV(0, "dout_sclk_fsys_mmc2_sdclkin_a",
+                       "mout_sclk_fsys_mmc2_sdclkin_b",
+                       DIV_TOP_FSYS1, 12, 4),
+       DIV(0, "dout_sclk_fsys_mmc1_sdclkin_b",
+                       "dout_sclk_fsys_mmc1_sdclkin_a",
+                       DIV_TOP_FSYS1, 4, 8),
+       DIV(0, "dout_sclk_fsys_mmc1_sdclkin_a",
+                       "mout_sclk_fsys_mmc1_sdclkin_b",
+                       DIV_TOP_FSYS1, 0, 4),
+};
+