QOM CPUState patch queue 2014-03-13
[Qemu-devel] [PULL for-2.0-rc0 40/58] translate-all: Change cpu_restore_state() argument to CPUState
In reply to Andreas FärberThis lets us drop some local variables in tlb_fill() functions.
Signed-off-by Andreas Färber <[email protected]>
--- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 2 +- target-alpha/mem_helper.c | 7 ++----- target-arm/op_helper.c | 2 +- target-cris/op_helper.c | 2 +- target-i386/helper.c | 2 +- target-i386/mem_helper.c | 2 +- target-lm32/op_helper.c | 5 +---- target-m68k/op_helper.c | 5 +---- target-microblaze/op_helper.c | 5 +---- target-mips/op_helper.c | 2 +- target-moxie/helper.c | 6 ++---- target-openrisc/mmu_helper.c | 5 +---- target-ppc/mmu_helper.c | 2 +- target-s390x/mem_helper.c | 5 +---- target-s390x/misc_helper.c | 2 +- target-sh4/op_helper.c | 7 ++----- target-sparc/helper.c | 20 ++++++++++++++------ target-sparc/ldst_helper.c | 8 +++----- target-unicore32/op_helper.c | 5 +---- target-xtensa/op_helper.c | 6 ++++-- translate-all.c | 3 ++- user-exec.c | 2 +- 24 files changed, 46 insertions(+), 63 deletions(-)
hw/i386/kvmvapic.c +1 -1
@@ -406,7 +406,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip) }if (!kvm_enabled ()) { -cpu_restore_state (env, cs->mem_io_pc); +cpu_restore_state (cs, cs->mem_io_pc);cpu_get_tb_cpu_state (env, ¤t_pc, ¤t_cs_base, ¤t_flags); }
include/exec/exec-all.h +1 -1
@@ -80,7 +80,7 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,void cpu_gen_init (void );int cpu_gen_code (CPUArchState *env,struct TranslationBlock *tb,int *gen_code_size_ptr); -bool cpu_restore_state (CPUArchState *env,uintptr_t searched_pc); +bool cpu_restore_state (CPUState *cpu,uintptr_t searched_pc);void page_size_init (void ); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
target-alpha/helper.c +1 -1
@@ -526,7 +526,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, cs->exception_index = excp; env->error_code = error;if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-alpha/mem_helper.c +2 -5
@@ -105,7 +105,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,uint32_t insn;if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); } pc = env->pc;
@@ -159,11 +159,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret =alpha_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (unlikely (ret !=0 )) { -AlphaCPU *cpu =ALPHA_CPU (cs); -CPUAlphaState *env = &cpu->env; -if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }/* Exception index and error code are already set */ cpu_loop_exit (cs);
target-arm/op_helper.c +1 -1
@@ -87,7 +87,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,if (retaddr) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }raise_exception (env, cs->exception_index); }
target-cris/op_helper.c +1 -1
@@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,if (unlikely (ret)) {if (retaddr) {/* now we have a real cpu fault */ -if (cpu_restore_state (env, retaddr)) { +if (cpu_restore_state (cs, retaddr)) {/* Evaluate flags after retranslation. */ helper_top_evaluate_flags (env); }
target-i386/helper.c +1 -1
@@ -1263,7 +1263,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)cpu_interrupt (cs,CPU_INTERRUPT_TPR ); }else { -cpu_restore_state (env, cs->mem_io_pc); +cpu_restore_state (cs, cs->mem_io_pc);apic_handle_tpr_access_report (cpu->apic_state, env->eip, access); }
target-i386/mem_helper.c +1 -1
@@ -145,7 +145,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,if (retaddr) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }raise_exception_err (env, cs->exception_index, env->error_code); }
target-lm32/op_helper.c +1 -4
@@ -160,12 +160,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =lm32_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (unlikely (ret)) { -LM32CPU *cpu =LM32_CPU (cs); -CPULM32State *env = &cpu->env; -if (retaddr) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-m68k/op_helper.c +1 -4
@@ -60,12 +60,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =m68k_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (unlikely (ret)) { -M68kCPU *cpu =M68K_CPU (cs); -CPUM68KState *env = &cpu->env; -if (retaddr) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-microblaze/op_helper.c +1 -4
@@ -49,12 +49,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =mb_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (unlikely (ret)) { -MicroBlazeCPU *cpu =MICROBLAZE_CPU (cs); -CPUMBState *env = &cpu->env; -if (retaddr) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-mips/op_helper.c +1 -1
@@ -48,7 +48,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,if (pc) {/* now we have a real cpu fault */ -cpu_restore_state (env, pc); +cpu_restore_state (cs, pc); }cpu_loop_exit (cs);
target-moxie/helper.c +2 -4
@@ -49,14 +49,12 @@void tlb_fill (CPUState *cs,target_ulong addr,int is_write,int mmu_idx,uintptr_t retaddr) { -MoxieCPU *cpu =MOXIE_CPU (cs); -CPUMoxieState *env = &cpu->env;int ret; ret =moxie_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (unlikely (ret)) {if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); } }cpu_loop_exit (cs);
@@ -70,7 +68,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex)/* Stash the exception type. */ env->sregs[2 ] = ex;/* Stash the address where the exception occurred. */ -cpu_restore_state (env,GETPC ()); +cpu_restore_state (cs,GETPC ()); env->sregs[5 ] = env->pc;/* Jump the the exception handline routine. */ env->pc = env->sregs[1 ];
target-openrisc/mmu_helper.c +1 -4
@@ -44,12 +44,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret =openrisc_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (ret) { -OpenRISCCPU *cpu =OPENRISC_CPU (cs); -CPUOpenRISCState *env = &cpu->env; -if (retaddr) {/* now we have a real cpu fault. */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }/* Raise Exception. */ cpu_loop_exit (cs);
target-ppc/mmu_helper.c +1 -1
@@ -2909,7 +2909,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,if (unlikely (ret !=0 )) {if (likely (retaddr)) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }helper_raise_exception_err (env, cs->exception_index, env->error_code); }
target-s390x/mem_helper.c +1 -4
@@ -51,12 +51,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =s390_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (unlikely (ret !=0 )) { -S390CPU *cpu =S390_CPU (cs); -CPUS390XState *env = &cpu->env; -if (likely (retaddr)) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-s390x/misc_helper.c +1 -1
@@ -54,7 +54,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, env->int_pgm_code = excp;/* Use the (ultimate) callers address to find the insn that trapped. */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr);/* Advance past the insn. */ t =cpu_ldub_code (env, env->psw.addr);
target-sh4/op_helper.c +2 -5
@@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =superh_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (ret) {/* now we have a real cpu fault */ -SuperHCPU *cpu =SUPERH_CPU (cs); -CPUSH4State *env = &cpu->env; -if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
@@ -75,7 +72,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, cs->exception_index = index;if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-sparc/helper.c +14 -6
@@ -71,6 +71,7 @@ void helper_tick_set_limit(void *opaque, uint64_t limit)static target_ulong helper_udiv_common (CPUSPARCState *env,target_ulong a,target_ulong b,int cc) { +SPARCCPU *cpu =sparc_env_get_cpu (env);int overflow =0 ;uint64_t x0;uint32_t x1;
@@ -79,7 +80,7 @@ static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a, x1 = (b &0xffffffff );if (x1 ==0 ) { -cpu_restore_state (env,GETPC ()); +cpu_restore_state (CPU (cpu),GETPC ());helper_raise_exception (env,TT_DIV_ZERO ); }
@@ -110,6 +111,7 @@ target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b)static target_ulong helper_sdiv_common (CPUSPARCState *env,target_ulong a,target_ulong b,int cc) { +SPARCCPU *cpu =sparc_env_get_cpu (env);int overflow =0 ;int64_t x0;int32_t x1;
@@ -118,7 +120,7 @@ static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a, x1 = (b &0xffffffff );if (x1 ==0 ) { -cpu_restore_state (env,GETPC ()); +cpu_restore_state (CPU (cpu),GETPC ());helper_raise_exception (env,TT_DIV_ZERO ); }
@@ -151,7 +153,9 @@ int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b) {if (b ==0 ) {/* Raise divide by zero trap. */ -cpu_restore_state (env,GETPC ()); +SPARCCPU *cpu =sparc_env_get_cpu (env); + +cpu_restore_state (CPU (cpu),GETPC ());helper_raise_exception (env,TT_DIV_ZERO ); }else if (b ==-1 ) {/* Avoid overflow trap with i386 divide insn. */
@@ -165,7 +169,9 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b) {if (b ==0 ) {/* Raise divide by zero trap. */ -cpu_restore_state (env,GETPC ()); +SPARCCPU *cpu =sparc_env_get_cpu (env); + +cpu_restore_state (CPU (cpu),GETPC ());helper_raise_exception (env,TT_DIV_ZERO ); }return a / b;
@@ -175,6 +181,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b)target_ulong helper_taddcctv (CPUSPARCState *env,target_ulong src1,target_ulong src2) { +SPARCCPU *cpu =sparc_env_get_cpu (env);target_ulong dst;/* Tag overflow occurs if either input has bits 0 or 1 set. */
@@ -197,13 +204,14 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,return dst; tag_overflow: -cpu_restore_state (env,GETPC ()); +cpu_restore_state (CPU (cpu),GETPC ());helper_raise_exception (env,TT_TOVF ); }target_ulong helper_tsubcctv (CPUSPARCState *env,target_ulong src1,target_ulong src2) { +SPARCCPU *cpu =sparc_env_get_cpu (env);target_ulong dst;/* Tag overflow occurs if either input has bits 0 or 1 set. */
@@ -226,7 +234,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,return dst; tag_overflow: -cpu_restore_state (env,GETPC ()); +cpu_restore_state (CPU (cpu),GETPC ());helper_raise_exception (env,TT_TOVF ); }
target-sparc/ldst_helper.c +3 -5
@@ -2424,12 +2424,13 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + SPARCCPU *cpu = sparc_env_get_cpu(env);#ifdef DEBUG_UNALIGNED printf ("Unaligned access to 0x" TARGET_FMT_lx" from 0x" TARGET_FMT_lx"\n" , addr, env->pc);#endif if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (CPU (cpu), retaddr); }helper_raise_exception (env,TT_UNALIGNED ); }
@@ -2445,11 +2446,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, ret =sparc_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (ret) { -SPARCCPU *cpu =SPARC_CPU (cs); -CPUSPARCState *env = &cpu->env; -if (retaddr) { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-unicore32/op_helper.c +1 -4
@@ -264,12 +264,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, ret =uc32_cpu_handle_mmu_fault (cs, addr, is_write, mmu_idx);if (unlikely (ret)) { -UniCore32CPU *cpu =UNICORE32_CPU (cs); -CPUUniCore32State *env = &cpu->env; -if (retaddr) {/* now we have a real cpu fault */ -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr); }cpu_loop_exit (cs); }
target-xtensa/op_helper.c +4 -2
@@ -52,9 +52,11 @@ static void do_unaligned_access(CPUXtensaState *env,static void do_unaligned_access (CPUXtensaState *env,target_ulong addr,int is_write,int is_user,uintptr_t retaddr) { +XtensaCPU *cpu =xtensa_env_get_cpu (env); +if (xtensa_option_enabled (env->config,XTENSA_OPTION_UNALIGNED_EXCEPTION ) && !xtensa_option_enabled (env->config,XTENSA_OPTION_HW_ALIGNMENT )) { -cpu_restore_state (env, retaddr); +cpu_restore_state (CPU (cpu), retaddr);HELPER (exception_cause_vaddr)(env, env->pc,LOAD_STORE_ALIGNMENT_CAUSE , addr); }
@@ -80,7 +82,7 @@ void tlb_fill(CPUState *cs, paddr &TARGET_PAGE_MASK , access, mmu_idx, page_size); }else { -cpu_restore_state (env, retaddr); +cpu_restore_state (cs, retaddr);HELPER (exception_cause_vaddr)(env, env->pc, ret, vaddr); } }
translate-all.c +2 -1
@@ -253,8 +253,9 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,return 0 ; } -bool cpu_restore_state (CPUArchState *env,uintptr_t retaddr) +bool cpu_restore_state (CPUState *cpu,uintptr_t retaddr) { +CPUArchState *env = cpu->env_ptr;TranslationBlock *tb; tb =tb_find_pc (retaddr);
user-exec.c +1 -1
@@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,return 1 ;/* the MMU fault was handled without causing real CPU fault */ }/* now we have a real cpu fault */ -cpu_restore_state (env, pc); +cpu_restore_state (cpu, pc);/* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 44/58] translate-all: Change tb_gen_code() argument to CPUState
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- cpu-exec.c | 4 ++-- exec.c | 2 +- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- translate-all.c | 9 +++++---- 5 files changed, 10 insertions(+), 9 deletions(-)
cpu-exec.c +2 -2
@@ -103,7 +103,7 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles,if (max_cycles >CF_COUNT_MASK ) max_cycles =CF_COUNT_MASK ; - tb =tb_gen_code (env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, + tb =tb_gen_code (cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, max_cycles); cpu->current_tb = tb;/* execute the generated code */
@@ -156,7 +156,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, } not_found:/* if no translated code available, then translate it now */ - tb =tb_gen_code (env, pc, cs_base, flags,0 ); + tb =tb_gen_code (cpu, pc, cs_base, flags,0 ); found:/* Move the last found TB to the head of the list */
exec.c +1 -1
@@ -1611,7 +1611,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)cpu_loop_exit (cpu); }else {cpu_get_tb_cpu_state (env, &pc, &cs_base, &cpu_flags); -tb_gen_code (env, pc, cs_base, cpu_flags,1 ); +tb_gen_code (cpu, pc, cs_base, cpu_flags,1 );cpu_resume_from_signal (env,NULL ); } }
hw/i386/kvmvapic.c +1 -1
@@ -448,7 +448,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)if (!kvm_enabled ()) { cs->current_tb =NULL ; -tb_gen_code (env, current_pc, current_cs_base, current_flags,1 ); +tb_gen_code (cs, current_pc, current_cs_base, current_flags,1 );cpu_resume_from_signal (env,NULL ); } }
include/exec/exec-all.h +1 -1
@@ -85,7 +85,7 @@ void page_size_init(void); void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); -TranslationBlock *tb_gen_code (CPUArchState *env, +TranslationBlock *tb_gen_code (CPUState *cpu,target_ulong pc,target_ulong cs_base,int flags,int cflags);void cpu_exec_init (CPUArchState *env);
translate-all.c +5 -4
@@ -938,10 +938,11 @@ static void build_page_bitmap(PageDesc *p) } } -TranslationBlock *tb_gen_code (CPUArchState *env, +TranslationBlock *tb_gen_code (CPUState *cpu,target_ulong pc,target_ulong cs_base,int flags,int cflags) { +CPUArchState *env = cpu->env_ptr;TranslationBlock *tb;uint8_t *tc_ptr;tb_page_addr_t phys_pc, phys_page2;
@@ -1111,7 +1112,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb =NULL ; -tb_gen_code (env, current_pc, current_cs_base, current_flags,1 ); +tb_gen_code (cpu, current_pc, current_cs_base, current_flags,1 ); cpu_resume_from_signal(env, NULL); }#endif
@@ -1208,7 +1209,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,modifying the memory. It will ensure that it cannot modify itself */ cpu->current_tb =NULL ; -tb_gen_code (env, current_pc, current_cs_base, current_flags,1 ); +tb_gen_code (cpu, current_pc, current_cs_base, current_flags,1 );if (locked) {mmap_unlock (); }
@@ -1469,7 +1470,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)tb_phys_invalidate (tb,-1 );/* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ -tb_gen_code (env, pc, cs_base, flags, cflags); +tb_gen_code (cpu, pc, cs_base, flags, cflags);/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not the first in the TB) then we end up generating a whole new TB and repeating the fault, which is horribly inefficient.
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 45/58] translate-all: Change tb_flush_jmp_cache() argument to CPUState
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- cputlb.c | 2 +- include/exec/cputlb.h | 2 +- translate-all.c | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-)
cputlb.c +1 -1
@@ -106,7 +106,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr)tlb_flush_entry (&env->tlb_table[mmu_idx][i], addr); } -tb_flush_jmp_cache (env, addr); +tb_flush_jmp_cache (cpu, addr); }/* update the TLBs so that writes to code in the virtual page 'addr'
include/exec/cputlb.h +1 -1
@@ -31,7 +31,7 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);extern int tlb_flush_count;/* exec.c */ -void tb_flush_jmp_cache (CPUArchState *env,target_ulong addr); +void tb_flush_jmp_cache (CPUState *cpu,target_ulong addr);MemoryRegionSection * address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
translate-all.c +1 -2
@@ -1479,9 +1479,8 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)cpu_resume_from_signal (env,NULL ); } -void tb_flush_jmp_cache (CPUArchState *env,target_ulong addr) +void tb_flush_jmp_cache (CPUState *cpu,target_ulong addr) { -CPUState *cpu =ENV_GET_CPU (env);unsigned int i;/* Discard jump cache entries for any tb which might potentially
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 46/58] target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hook
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- target-ppc/cpu-qom.h | 8 +++++--- target-ppc/mmu-hash32.c | 5 +++-- target-ppc/mmu-hash32.h | 2 +- target-ppc/mmu-hash64.c | 5 +++-- target-ppc/mmu-hash64.h | 2 +- target-ppc/mmu_helper.c | 2 +- 6 files changed, 14 insertions(+), 10 deletions(-)
target-ppc/cpu-qom.h +5 -3
@@ -38,6 +38,8 @@#define POWERPC_CPU_GET_CLASS (obj) \ OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) +typedef struct PowerPCCPU PowerPCCPU ; +/** * PowerPCCPUClass: * @parent_realize: The parent class' realize handler.
@@ -71,7 +73,7 @@ typedef struct PowerPCCPUClass {void (*init_proc)(CPUPPCState *env);int (*check_pow)(CPUPPCState *env);#if defined(CONFIG_SOFTMMU ) -int (*handle_mmu_fault)(CPUPPCState *env,target_ulong eaddr,int rwx, +int (*handle_mmu_fault)(PowerPCCPU *cpu,target_ulong eaddr,int rwx,int mmu_idx);#endif } PowerPCCPUClass;
@@ -83,14 +85,14 @@ typedef struct PowerPCCPUClass {* * A PowerPC CPU. */ -typedef struct PowerPCCPU { +struct PowerPCCPU {/*< private >*/ CPUState parent_obj;/*< public >*/ CPUPPCState env;int cpu_dt_id; -}PowerPCCPU ; +};static inline PowerPCCPU *ppc_env_get_cpu (CPUPPCState *env) {
target-ppc/mmu-hash32.c +3 -2
@@ -381,10 +381,11 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash32_handle_mmu_fault (CPUPPCState *env,target_ulong eaddr,int rwx, +int ppc_hash32_handle_mmu_fault (PowerPCCPU *cpu,target_ulong eaddr,int rwx,int mmu_idx) { -CPUState *cs =CPU (ppc_env_get_cpu (env)); +CPUState *cs =CPU (cpu); +CPUPPCState *env = &cpu->env;target_ulong sr;hwaddr pte_offset;ppc_hash_pte32_t pte;
target-ppc/mmu-hash32.h +1 -1
@@ -5,7 +5,7 @@hwaddr get_pteg_offset32 (CPUPPCState *env,hwaddr hash);hwaddr ppc_hash32_get_phys_page_debug (CPUPPCState *env,target_ulong addr); -int ppc_hash32_handle_mmu_fault (CPUPPCState *env,target_ulong address,int rw, +int ppc_hash32_handle_mmu_fault (PowerPCCPU *cpu,target_ulong address,int rw,int mmu_idx);/*
target-ppc/mmu-hash64.c +3 -2
@@ -454,10 +454,11 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,return (rpn & ~mask) | (eaddr & mask); } -int ppc_hash64_handle_mmu_fault (CPUPPCState *env,target_ulong eaddr, +int ppc_hash64_handle_mmu_fault (PowerPCCPU *cpu,target_ulong eaddr,int rwx,int mmu_idx) { -CPUState *cs =CPU (ppc_env_get_cpu (env)); +CPUState *cs =CPU (cpu); +CPUPPCState *env = &cpu->env;ppc_slb_t *slb;hwaddr pte_offset;ppc_hash_pte64_t pte;
target-ppc/mmu-hash64.h +1 -1
@@ -7,7 +7,7 @@void dump_slb (FILE *f,fprintf_function cpu_fprintf,CPUPPCState *env);int ppc_store_slb (CPUPPCState *env,target_ulong rb,target_ulong rs);hwaddr ppc_hash64_get_phys_page_debug (CPUPPCState *env,target_ulong addr); -int ppc_hash64_handle_mmu_fault (CPUPPCState *env,target_ulong address,int rw, +int ppc_hash64_handle_mmu_fault (PowerPCCPU *cpu,target_ulong address,int rw,int mmu_idx);void ppc_hash64_store_hpte (CPUPPCState *env,target_ulong index,target_ulong pte0,target_ulong pte1);
target-ppc/mmu_helper.c +1 -1
@@ -2902,7 +2902,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,int ret;if (pcc->handle_mmu_fault) { - ret = pcc->handle_mmu_fault (env, addr, is_write, mmu_idx); + ret = pcc->handle_mmu_fault (cpu, addr, is_write, mmu_idx); }else { ret =cpu_ppc_handle_mmu_fault (env, addr, is_write, mmu_idx); }
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 48/58] exec: Change cpu_breakpoint_{insert, remove{, _by_ref, _all}} argument
In reply to Andreas FärberUse CPUState. Allows to clean up CPUArchState in gdbstub.
Signed-off-by Andreas Färber <[email protected]>
--- exec.c | 20 ++++++++------------ gdbstub.c | 20 ++++++++------------ include/exec/cpu-all.h | 15 --------------- include/qom/cpu.h | 15 +++++++++++++++ linux-user/main.c | 2 +- target-i386/cpu.c | 2 +- target-i386/helper.c | 4 ++-- target-i386/machine.c | 2 +- target-lm32/helper.c | 9 +++++++-- 9 files changed, 43 insertions(+), 46 deletions(-)
exec.c +8 -12
@@ -617,11 +617,10 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)#endif /* Add a breakpoint. */ -int cpu_breakpoint_insert (CPUArchState *env,target_ulong pc,int flags, +int cpu_breakpoint_insert (CPUState *cpu,vaddr pc,int flags,CPUBreakpoint **breakpoint) {#if defined(TARGET_HAS_ICE ) -CPUState *cpu =ENV_GET_CPU (env);CPUBreakpoint *bp; bp =g_malloc (sizeof (*bp));
@@ -648,15 +647,14 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, }/* Remove a specific breakpoint. */ -int cpu_breakpoint_remove (CPUArchState *env,target_ulong pc,int flags) +int cpu_breakpoint_remove (CPUState *cpu,vaddr pc,int flags) {#if defined(TARGET_HAS_ICE ) -CPUState *cpu =ENV_GET_CPU (env);CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {if (bp->pc == pc && bp->flags == flags) { -cpu_breakpoint_remove_by_ref (env, bp); +cpu_breakpoint_remove_by_ref (cpu, bp);return 0 ; } }
@@ -667,11 +665,9 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) }/* Remove a specific breakpoint by reference. */ -void cpu_breakpoint_remove_by_ref (CPUArchState *env,CPUBreakpoint *breakpoint) +void cpu_breakpoint_remove_by_ref (CPUState *cpu,CPUBreakpoint *breakpoint) {#if defined(TARGET_HAS_ICE ) -CPUState *cpu =ENV_GET_CPU (env); -QTAILQ_REMOVE (&cpu->breakpoints, breakpoint, entry);breakpoint_invalidate (cpu, breakpoint->pc);
@@ -681,15 +677,15 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) }/* Remove all matching breakpoints. */ -void cpu_breakpoint_remove_all (CPUArchState *env,int mask) +void cpu_breakpoint_remove_all (CPUState *cpu,int mask) {#if defined(TARGET_HAS_ICE ) -CPUState *cpu =ENV_GET_CPU (env);CPUBreakpoint *bp, *next; QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { -if (bp->flags & mask) -cpu_breakpoint_remove_by_ref (env, bp); +if (bp->flags & mask) { +cpu_breakpoint_remove_by_ref (cpu, bp); + } }#endif }
gdbstub.c +8 -12
@@ -635,7 +635,6 @@ static const int xlat_gdb_type[] = {static int gdb_breakpoint_insert (target_ulong addr,target_ulong len,int type) {CPUState *cpu; -CPUArchState *env;int err =0 ;if (kvm_enabled ()) {
@@ -646,10 +645,10 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)case GDB_BREAKPOINT_SW :case GDB_BREAKPOINT_HW : CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err =cpu_breakpoint_insert (env, addr,BP_GDB ,NULL ); -if (err) + err =cpu_breakpoint_insert (cpu, addr,BP_GDB ,NULL ); +if (err) {break ; + } }return err;#ifndef CONFIG_USER_ONLY
@@ -672,7 +671,6 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)static int gdb_breakpoint_remove (target_ulong addr,target_ulong len,int type) {CPUState *cpu; -CPUArchState *env;int err =0 ;if (kvm_enabled ()) {
@@ -683,10 +681,10 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)case GDB_BREAKPOINT_SW :case GDB_BREAKPOINT_HW : CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err =cpu_breakpoint_remove (env, addr,BP_GDB ); -if (err) + err =cpu_breakpoint_remove (cpu, addr,BP_GDB ); +if (err) {break ; + } }return err;#ifndef CONFIG_USER_ONLY
@@ -708,7 +706,6 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)static void gdb_breakpoint_remove_all (void ) {CPUState *cpu; -CPUArchState *env;if (kvm_enabled ()) {kvm_remove_all_breakpoints (gdbserver_state->c_cpu);
@@ -716,8 +713,7 @@ static void gdb_breakpoint_remove_all(void) }CPU_FOREACH (cpu) { - env = cpu->env_ptr; -cpu_breakpoint_remove_all (env,BP_GDB ); +cpu_breakpoint_remove_all (cpu,BP_GDB );#ifndef CONFIG_USER_ONLY cpu_watchpoint_remove_all (cpu,BP_GDB );#endif
@@ -1599,7 +1595,7 @@ void gdbserver_fork(CPUArchState *env) }close (s->fd); s->fd =-1 ; -cpu_breakpoint_remove_all (env,BP_GDB ); +cpu_breakpoint_remove_all (cpu,BP_GDB );cpu_watchpoint_remove_all (cpu,BP_GDB ); }#else
include/exec/cpu-all.h +0 -15
@@ -413,21 +413,6 @@ void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) | CPU_INTERRUPT_TGT_EXT_3 \ | CPU_INTERRUPT_TGT_EXT_4) -/* Breakpoint/watchpoint flags */ -#define BP_MEM_READ 0x01 -#define BP_MEM_WRITE 0x02 -#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) -#define BP_STOP_BEFORE_ACCESS 0x04 -#define BP_WATCHPOINT_HIT 0x08 -#define BP_GDB 0x10 -#define BP_CPU 0x20 - -int cpu_breakpoint_insert (CPUArchState *env,target_ulong pc,int flags, -CPUBreakpoint **breakpoint); -int cpu_breakpoint_remove (CPUArchState *env,target_ulong pc,int flags); -void cpu_breakpoint_remove_by_ref (CPUArchState *env,CPUBreakpoint *breakpoint); -void cpu_breakpoint_remove_all (CPUArchState *env,int mask); -#if !defined(CONFIG_USER_ONLY )/* memory API */
include/qom/cpu.h +15 -0
@@ -595,6 +595,21 @@ void qemu_init_vcpu(CPUState *cpu);*/ void cpu_single_step (CPUState *cpu,int enabled); +/* Breakpoint/watchpoint flags */ +#define BP_MEM_READ 0x01 +#define BP_MEM_WRITE 0x02 +#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) +#define BP_STOP_BEFORE_ACCESS 0x04 +#define BP_WATCHPOINT_HIT 0x08 +#define BP_GDB 0x10 +#define BP_CPU 0x20 + +int cpu_breakpoint_insert (CPUState *cpu,vaddr pc,int flags, +CPUBreakpoint **breakpoint); +int cpu_breakpoint_remove (CPUState *cpu,vaddr pc,int flags); +void cpu_breakpoint_remove_by_ref (CPUState *cpu,CPUBreakpoint *breakpoint); +void cpu_breakpoint_remove_all (CPUState *cpu,int mask); +int cpu_watchpoint_insert (CPUState *cpu,vaddr addr,vaddr len,int flags,CPUWatchpoint **watchpoint); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
linux-user/main.c +1 -1
@@ -3455,7 +3455,7 @@ CPUArchState *cpu_copy(CPUArchState *env)QTAILQ_INIT (&cpu->watchpoints);#if defined(TARGET_HAS_ICE ) QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { -cpu_breakpoint_insert (new_env, bp->pc, bp->flags,NULL ); +cpu_breakpoint_insert (new_cpu, bp->pc, bp->flags,NULL ); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1,
target-i386/cpu.c +1 -1
@@ -2469,7 +2469,7 @@ static void x86_cpu_reset(CPUState *s)memset (env->dr,0 ,sizeof (env->dr)); env->dr[6 ] =DR6_FIXED_1 ; env->dr[7 ] =DR7_FIXED_1 ; -cpu_breakpoint_remove_all (env,BP_CPU ); +cpu_breakpoint_remove_all (s,BP_CPU );cpu_watchpoint_remove_all (s,BP_CPU ); env->tsc_adjust =0 ;
target-i386/helper.c +2 -2
@@ -999,7 +999,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index)switch (hw_breakpoint_type (env->dr[7 ], index)) {case DR7_TYPE_BP_INST :if (hw_breakpoint_enabled (env->dr[7 ], index)) { - err =cpu_breakpoint_insert (env, env->dr[index],BP_CPU , + err =cpu_breakpoint_insert (cs, env->dr[index],BP_CPU , &env->cpu_breakpoint[index]); }break ;
@@ -1036,7 +1036,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index)switch (hw_breakpoint_type (env->dr[7 ], index)) {case DR7_TYPE_BP_INST :if (hw_breakpoint_enabled (env->dr[7 ], index)) { -cpu_breakpoint_remove_by_ref (env, env->cpu_breakpoint[index]); +cpu_breakpoint_remove_by_ref (cs, env->cpu_breakpoint[index]); }break ;case DR7_TYPE_DATA_WR :
target-i386/machine.c +1 -1
@@ -320,7 +320,7 @@ static int cpu_post_load(void *opaque, int version_id) env->fptags[i] = (env->fptag_vmstate >> i) &1 ; } -cpu_breakpoint_remove_all (env,BP_CPU ); +cpu_breakpoint_remove_all (cs,BP_CPU );cpu_watchpoint_remove_all (cs,BP_CPU );for (i =0 ; i <DR7_MAX_BP ; i++) {hw_breakpoint_insert (env, i);
target-lm32/helper.c +7 -2
@@ -53,16 +53,21 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)void lm32_breakpoint_insert (CPULM32State *env,int idx,target_ulong address) { -cpu_breakpoint_insert (env, address,BP_CPU , &env->cpu_breakpoint[idx]); +LM32CPU *cpu =lm32_env_get_cpu (env); + +cpu_breakpoint_insert (CPU (cpu), address,BP_CPU , + &env->cpu_breakpoint[idx]); }void lm32_breakpoint_remove (CPULM32State *env,int idx) { +LM32CPU *cpu =lm32_env_get_cpu (env); +if (!env->cpu_breakpoint[idx]) {return ; } -cpu_breakpoint_remove_by_ref (env, env->cpu_breakpoint[idx]); +cpu_breakpoint_remove_by_ref (CPU (cpu), env->cpu_breakpoint[idx]); env->cpu_breakpoint[idx] =NULL ; }
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 47/58] exec: Change cpu_watchpoint_{insert, remove{, _by_ref, _all}} argument
In reply to Andreas FärberUse CPUState. This lets us drop a few local env usages.
Signed-off-by Andreas Färber <[email protected]>
--- exec.c | 34 +++++++++++++++++----------------- gdbstub.c | 17 +++++++++-------- include/exec/cpu-all.h | 6 ------ include/qom/cpu.h | 7 +++++++ linux-user/main.c | 5 +++-- target-i386/cpu.c | 2 +- target-i386/helper.c | 11 ++++++++--- target-i386/machine.c | 3 ++- target-lm32/helper.c | 7 +++++-- target-xtensa/op_helper.c | 9 ++++++--- 10 files changed, 58 insertions(+), 43 deletions(-)
exec.c +17 -17
@@ -33,6 +33,7 @@#include "hw/xen/xen.h" #include "qemu/timer.h" #include "qemu/config-file.h" +#include "qemu/error-report.h" #include "exec/memory.h" #include "sysemu/dma.h" #include "exec/address-spaces.h"
@@ -527,30 +528,30 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)#endif /* TARGET_HAS_ICE */ #if defined(CONFIG_USER_ONLY ) -void cpu_watchpoint_remove_all (CPUArchState *env,int mask) +void cpu_watchpoint_remove_all (CPUState *cpu,int mask) { } -int cpu_watchpoint_insert (CPUArchState *env,target_ulong addr,target_ulong len, +int cpu_watchpoint_insert (CPUState *cpu,vaddr addr,vaddr len,int flags,CPUWatchpoint **watchpoint) {return -ENOSYS ; }#else /* Add a watchpoint. */ -int cpu_watchpoint_insert (CPUArchState *env,target_ulong addr,target_ulong len, +int cpu_watchpoint_insert (CPUState *cpu,vaddr addr,vaddr len,int flags,CPUWatchpoint **watchpoint) { -CPUState *cpu =ENV_GET_CPU (env); -target_ulong len_mask = ~(len -1 ); +CPUArchState *env = cpu->env_ptr; +vaddr len_mask = ~(len -1 );CPUWatchpoint *wp;/* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ if ((len & (len -1 )) || (addr & ~len_mask) || len ==0 || len >TARGET_PAGE_SIZE ) { -fprintf (stderr,"qemu: tried to set invalid watchpoint at " - TARGET_FMT_lx", len=" TARGET_FMT_lu"\n" , addr, len); +error_report ("tried to set invalid watchpoint at %" + VADDR_PRIx", len=%" VADDR_PRIu, addr, len);return -EINVAL ; } wp =g_malloc (sizeof (*wp));
@@ -574,17 +575,16 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len }/* Remove a specific watchpoint. */ -int cpu_watchpoint_remove (CPUArchState *env,target_ulong addr,target_ulong len, +int cpu_watchpoint_remove (CPUState *cpu,vaddr addr,vaddr len,int flags) { -CPUState *cpu =ENV_GET_CPU (env); -target_ulong len_mask = ~(len -1 ); +vaddr len_mask = ~(len -1 );CPUWatchpoint *wp; QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {if (addr == wp->vaddr && len_mask == wp->len_mask && flags == (wp->flags & ~BP_WATCHPOINT_HIT )) { -cpu_watchpoint_remove_by_ref (env, wp); +cpu_watchpoint_remove_by_ref (cpu, wp);return 0 ; } }
@@ -592,9 +592,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len }/* Remove a specific watchpoint by reference. */ -void cpu_watchpoint_remove_by_ref (CPUArchState *env,CPUWatchpoint *watchpoint) +void cpu_watchpoint_remove_by_ref (CPUState *cpu,CPUWatchpoint *watchpoint) { -CPUState *cpu =ENV_GET_CPU (env); +CPUArchState *env = cpu->env_ptr;QTAILQ_REMOVE (&cpu->watchpoints, watchpoint, entry);
@@ -604,14 +604,14 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) }/* Remove all matching watchpoints. */ -void cpu_watchpoint_remove_all (CPUArchState *env,int mask) +void cpu_watchpoint_remove_all (CPUState *cpu,int mask) { -CPUState *cpu =ENV_GET_CPU (env);CPUWatchpoint *wp, *next; QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { -if (wp->flags & mask) -cpu_watchpoint_remove_by_ref (env, wp); +if (wp->flags & mask) { +cpu_watchpoint_remove_by_ref (cpu, wp); + } } }#endif
gdbstub.c +9 -8
@@ -657,8 +657,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)case GDB_WATCHPOINT_READ :case GDB_WATCHPOINT_ACCESS : CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err =cpu_watchpoint_insert (env, addr, len, xlat_gdb_type[type], + err =cpu_watchpoint_insert (cpu, addr, len, xlat_gdb_type[type],NULL );if (err)break ;
@@ -695,8 +694,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)case GDB_WATCHPOINT_READ :case GDB_WATCHPOINT_ACCESS : CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err =cpu_watchpoint_remove (env, addr, len, xlat_gdb_type[type]); + err =cpu_watchpoint_remove (cpu, addr, len, xlat_gdb_type[type]);if (err)break ; }
@@ -721,7 +719,7 @@ static void gdb_breakpoint_remove_all(void) env = cpu->env_ptr;cpu_breakpoint_remove_all (env,BP_GDB );#ifndef CONFIG_USER_ONLY -cpu_watchpoint_remove_all (env,BP_GDB ); +cpu_watchpoint_remove_all (cpu,BP_GDB );#endif } }
@@ -1593,13 +1591,16 @@ int gdbserver_start(int port)/* Disable gdb stub for child processes. */ void gdbserver_fork (CPUArchState *env) { +CPUState *cpu =ENV_GET_CPU (env);GDBState *s = gdbserver_state; -if (gdbserver_fd <0 || s->fd <0 ) -return ; + +if (gdbserver_fd <0 || s->fd <0 ) { +return ; + }close (s->fd); s->fd =-1 ;cpu_breakpoint_remove_all (env,BP_GDB ); -cpu_watchpoint_remove_all (env,BP_GDB ); +cpu_watchpoint_remove_all (cpu,BP_GDB ); }#else static int gdb_chr_can_receive (void *opaque)
include/exec/cpu-all.h +0 -6
@@ -427,12 +427,6 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,int cpu_breakpoint_remove (CPUArchState *env,target_ulong pc,int flags);void cpu_breakpoint_remove_by_ref (CPUArchState *env,CPUBreakpoint *breakpoint);void cpu_breakpoint_remove_all (CPUArchState *env,int mask); -int cpu_watchpoint_insert (CPUArchState *env,target_ulong addr,target_ulong len, -int flags,CPUWatchpoint **watchpoint); -int cpu_watchpoint_remove (CPUArchState *env,target_ulong addr, -target_ulong len,int flags); -void cpu_watchpoint_remove_by_ref (CPUArchState *env,CPUWatchpoint *watchpoint); -void cpu_watchpoint_remove_all (CPUArchState *env,int mask);#if !defined(CONFIG_USER_ONLY )
include/qom/cpu.h +7 -0
@@ -595,6 +595,13 @@ void qemu_init_vcpu(CPUState *cpu);*/ void cpu_single_step (CPUState *cpu,int enabled); +int cpu_watchpoint_insert (CPUState *cpu,vaddr addr,vaddr len, +int flags,CPUWatchpoint **watchpoint); +int cpu_watchpoint_remove (CPUState *cpu,vaddr addr, +vaddr len,int flags); +void cpu_watchpoint_remove_by_ref (CPUState *cpu,CPUWatchpoint *watchpoint); +void cpu_watchpoint_remove_all (CPUState *cpu,int mask); +#ifdef CONFIG_SOFTMMU extern const struct VMStateDescription vmstate_cpu_common;#else
linux-user/main.c +3 -2
@@ -3437,13 +3437,14 @@ CPUArchState *cpu_copy(CPUArchState *env) {CPUState *cpu =ENV_GET_CPU (env);CPUArchState *new_env =cpu_init (cpu_model); +CPUState *new_cpu =ENV_GET_CPU (new_env);#if defined(TARGET_HAS_ICE )CPUBreakpoint *bp;CPUWatchpoint *wp;#endif /* Reset non arch specific state */ -cpu_reset (ENV_GET_CPU (new_env)); +cpu_reset (new_cpu);memcpy (new_env, env,sizeof (CPUArchState));
@@ -3457,7 +3458,7 @@ CPUArchState *cpu_copy(CPUArchState *env)cpu_breakpoint_insert (new_env, bp->pc, bp->flags,NULL ); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { -cpu_watchpoint_insert (new_env, wp->vaddr, (~wp->len_mask) +1 , +cpu_watchpoint_insert (new_cpu, wp->vaddr, (~wp->len_mask) +1 , wp->flags, NULL); }#endif
target-i386/cpu.c +1 -1
@@ -2470,7 +2470,7 @@ static void x86_cpu_reset(CPUState *s) env->dr[6 ] =DR6_FIXED_1 ; env->dr[7 ] =DR7_FIXED_1 ;cpu_breakpoint_remove_all (env,BP_CPU ); -cpu_watchpoint_remove_all (env,BP_CPU ); +cpu_watchpoint_remove_all (s,BP_CPU ); env->tsc_adjust =0 ; env->tsc =0 ;
target-i386/helper.c +8 -3
@@ -993,6 +993,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)void hw_breakpoint_insert (CPUX86State *env,int index) { +CPUState *cs =CPU (x86_env_get_cpu (env));int type =0 , err =0 ;switch (hw_breakpoint_type (env->dr[7 ], index)) {
@@ -1014,7 +1015,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index) }if (type !=0 ) { - err =cpu_watchpoint_insert (env, env->dr[index], + err =cpu_watchpoint_insert (cs, env->dr[index],hw_breakpoint_len (env->dr[7 ], index), type, &env->cpu_watchpoint[index]); }
@@ -1026,8 +1027,12 @@ void hw_breakpoint_insert(CPUX86State *env, int index)void hw_breakpoint_remove (CPUX86State *env,int index) { -if (!env->cpu_breakpoint[index]) +CPUState *cs; + +if (!env->cpu_breakpoint[index]) {return ; + } + cs =CPU (x86_env_get_cpu (env));switch (hw_breakpoint_type (env->dr[7 ], index)) {case DR7_TYPE_BP_INST :if (hw_breakpoint_enabled (env->dr[7 ], index)) {
@@ -1036,7 +1041,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index)break ;case DR7_TYPE_DATA_WR :case DR7_TYPE_DATA_RW : -cpu_watchpoint_remove_by_ref (env, env->cpu_watchpoint[index]); +cpu_watchpoint_remove_by_ref (cs, env->cpu_watchpoint[index]);break ;case DR7_TYPE_IO_RW :/* No support for I/O watchpoints yet */
target-i386/machine.c +2 -1
@@ -290,6 +290,7 @@ static void cpu_pre_save(void *opaque)static int cpu_post_load (void *opaque,int version_id) {X86CPU *cpu = opaque; +CPUState *cs =CPU (cpu);CPUX86State *env = &cpu->env;int i;
@@ -320,7 +321,7 @@ static int cpu_post_load(void *opaque, int version_id) }cpu_breakpoint_remove_all (env,BP_CPU ); -cpu_watchpoint_remove_all (env,BP_CPU ); +cpu_watchpoint_remove_all (cs,BP_CPU );for (i =0 ; i <DR7_MAX_BP ; i++) {hw_breakpoint_insert (env, i); }
target-lm32/helper.c +5 -2
@@ -69,6 +69,7 @@ void lm32_breakpoint_remove(CPULM32State *env, int idx)void lm32_watchpoint_insert (CPULM32State *env,int idx,target_ulong address,lm32_wp_t wp_type) { +LM32CPU *cpu =lm32_env_get_cpu (env);int flags =0 ;switch (wp_type) {
@@ -87,18 +88,20 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, }if (flags !=0 ) { -cpu_watchpoint_insert (env, address,1 , flags, +cpu_watchpoint_insert (CPU (cpu), address,1 , flags, &env->cpu_watchpoint[idx]); } }void lm32_watchpoint_remove (CPULM32State *env,int idx) { +LM32CPU *cpu =lm32_env_get_cpu (env); +if (!env->cpu_watchpoint[idx]) {return ; } -cpu_watchpoint_remove_by_ref (env, env->cpu_watchpoint[idx]); +cpu_watchpoint_remove_by_ref (CPU (cpu), env->cpu_watchpoint[idx]); env->cpu_watchpoint[idx] =NULL ; }
target-xtensa/op_helper.c +6 -3
@@ -790,11 +790,12 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)static void set_dbreak (CPUXtensaState *env,unsigned i,uint32_t dbreaka,uint32_t dbreakc) { +CPUState *cs =CPU (xtensa_env_get_cpu (env));int flags =BP_CPU |BP_STOP_BEFORE_ACCESS ;uint32_t mask = dbreakc | ~DBREAKC_MASK ;if (env->cpu_watchpoint[i]) { -cpu_watchpoint_remove_by_ref (env, env->cpu_watchpoint[i]); +cpu_watchpoint_remove_by_ref (cs, env->cpu_watchpoint[i]); }if (dbreakc &DBREAKC_SB ) { flags |=BP_MEM_WRITE ;
@@ -808,7 +809,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,/* cut mask after the first zero bit */ mask =0xffffffff << (32 -clo32 (mask)); } -if (cpu_watchpoint_insert (env, dbreaka & mask, ~mask +1 , +if (cpu_watchpoint_insert (cs, dbreaka & mask, ~mask +1 , flags, &env->cpu_watchpoint[i])) { env->cpu_watchpoint[i] =NULL ; qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
@@ -834,7 +835,9 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)set_dbreak (env, i, env->sregs[DBREAKA + i], v); }else {if (env->cpu_watchpoint[i]) { -cpu_watchpoint_remove_by_ref (env, env->cpu_watchpoint[i]); +CPUState *cs =CPU (xtensa_env_get_cpu (env)); + +cpu_watchpoint_remove_by_ref (cs, env->cpu_watchpoint[i]); env->cpu_watchpoint[i] =NULL ; } }
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 51/58] exec: Change memory_region_section_get_iotlb() argument to CPUState
In reply to Andreas FärberIt no longer needs CPUArchState since moving watchpoints to CPUState.
Signed-off-by Andreas Färber <[email protected]>
--- cputlb.c | 2 +- exec.c | 3 +-- include/exec/cputlb.h | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-)
cputlb.c +1 -1
@@ -261,7 +261,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, } code_address = address; - iotlb =memory_region_section_get_iotlb (env, section, vaddr, paddr, xlat, + iotlb =memory_region_section_get_iotlb (cpu, section, vaddr, paddr, xlat, prot, &address); index = (vaddr >>TARGET_PAGE_BITS ) & (CPU_TLB_SIZE -1 );
exec.c +1 -2
@@ -799,14 +799,13 @@ static void cpu_physical_memory_set_dirty_tracking(bool enable) in_migration = enable; } -hwaddr memory_region_section_get_iotlb (CPUArchState *env, +hwaddr memory_region_section_get_iotlb (CPUState *cpu,MemoryRegionSection *section,target_ulong vaddr,hwaddr paddr,hwaddr xlat,int prot,target_ulong *address) { -CPUState *cpu =ENV_GET_CPU (env);hwaddr iotlb;CPUWatchpoint *wp;
include/exec/cputlb.h +1 -1
@@ -36,7 +36,7 @@ void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);MemoryRegionSection *address_space_translate_for_iotlb (AddressSpace *as,hwaddr addr,hwaddr *xlat,hwaddr *plen); -hwaddr memory_region_section_get_iotlb(CPUArchState *env, +hwaddr memory_region_section_get_iotlb(CPUState *cpu, MemoryRegionSection *section, target_ulong vaddr, hwaddr paddr, hwaddr xlat,
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 50/58] cputlb: Change tlb_unprotect_code_phys() argument to CPUState
In reply to Andreas FärberNote that the argument is unused.
Signed-off-by Andreas Färber <[email protected]>
--- cputlb.c | 2 +- include/exec/cputlb.h | 2 +- translate-all.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-)
cputlb.c +1 -1
@@ -119,7 +119,7 @@ void tlb_protect_code(ram_addr_t ram_addr)/* update the TLB so that writes in physical page 'phys_addr' are no longer tested for self modifying code */ -void tlb_unprotect_code_phys (CPUArchState *env,ram_addr_t ram_addr, +void tlb_unprotect_code_phys (CPUState *cpu,ram_addr_t ram_addr,target_ulong vaddr) {cpu_physical_memory_set_dirty_flag (ram_addr,DIRTY_MEMORY_CODE );
include/exec/cputlb.h +1 -1
@@ -22,7 +22,7 @@#if !defined(CONFIG_USER_ONLY )/* cputlb.c */ void tlb_protect_code (ram_addr_t ram_addr); -void tlb_unprotect_code_phys (CPUArchState *env,ram_addr_t ram_addr, +void tlb_unprotect_code_phys (CPUState *cpu,ram_addr_t ram_addr,target_ulong vaddr);void tlb_reset_dirty_range (CPUTLBEntry *tlb_entry,uintptr_t start,uintptr_t length);
translate-all.c +3 -3
@@ -1007,7 +1007,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, {TranslationBlock *tb, *tb_next, *saved_tb;CPUState *cpu = current_cpu; -#if defined(TARGET_HAS_PRECISE_SMC ) || !defined(CONFIG_USER_ONLY ) +#if defined(TARGET_HAS_PRECISE_SMC )CPUArchState *env =NULL ;#endif tb_page_addr_t tb_start, tb_end;
@@ -1032,7 +1032,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,/* build code bitmap */ build_page_bitmap (p); } -#if defined(TARGET_HAS_PRECISE_SMC ) || !defined(CONFIG_USER_ONLY ) +#if defined(TARGET_HAS_PRECISE_SMC )if (cpu !=NULL ) { env = cpu->env_ptr; }
@@ -1102,7 +1102,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,if (!p->first_tb) {invalidate_page_bitmap (p);if (is_cpu_write_access) { -tlb_unprotect_code_phys (env, start, cpu->mem_io_vaddr); +tlb_unprotect_code_phys (cpu, start, cpu->mem_io_vaddr); } }#endif
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 49/58] cpu-exec: Change cpu_resume_from_signal() argument to CPUState
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- cpu-exec.c | 4 +--- exec.c | 2 +- hw/i386/kvmvapic.c | 2 +- include/exec/exec-all.h | 2 +- target-i386/helper.c | 2 +- target-lm32/helper.c | 2 +- target-xtensa/helper.c | 2 +- translate-all.c | 6 +++--- user-exec.c | 3 +-- 9 files changed, 11 insertions(+), 14 deletions(-)
cpu-exec.c +1 -3
@@ -33,10 +33,8 @@ void cpu_loop_exit(CPUState *cpu)restored in a state compatible with the CPU emulator */ #if defined(CONFIG_SOFTMMU ) -void cpu_resume_from_signal (CPUArchState *env,void *puc) +void cpu_resume_from_signal (CPUState *cpu,void *puc) { -CPUState *cpu =ENV_GET_CPU (env); -/* XXX: restore cpu registers saved in host registers */ cpu->exception_index =-1 ;
exec.c +1 -1
@@ -1608,7 +1608,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) }else {cpu_get_tb_cpu_state (env, &pc, &cs_base, &cpu_flags);tb_gen_code (cpu, pc, cs_base, cpu_flags,1 ); -cpu_resume_from_signal (env,NULL ); +cpu_resume_from_signal (cpu,NULL ); } } }else {
hw/i386/kvmvapic.c +1 -1
@@ -449,7 +449,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)if (!kvm_enabled ()) { cs->current_tb =NULL ;tb_gen_code (cs, current_pc, current_cs_base, current_flags,1 ); -cpu_resume_from_signal (env,NULL ); +cpu_resume_from_signal (cs,NULL ); } }
include/exec/exec-all.h +1 -1
@@ -83,7 +83,7 @@ int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,bool cpu_restore_state (CPUState *cpu,uintptr_t searched_pc);void page_size_init (void ); -void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); +void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc); void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, target_ulong cs_base, int flags,
target-i386/helper.c +1 -1
@@ -1102,7 +1102,7 @@ void breakpoint_handler(CPUX86State *env)if (check_hw_breakpoints (env, false)) {raise_exception (env,EXCP01_DB ); }else { -cpu_resume_from_signal (env,NULL ); +cpu_resume_from_signal (cs,NULL ); } } }else {
target-lm32/helper.c +1 -1
@@ -135,7 +135,7 @@ void lm32_debug_excp_handler(CPULM32State *env)if (check_watchpoints (env)) {raise_exception (env,EXCP_WATCHPOINT ); }else { -cpu_resume_from_signal (env,NULL ); +cpu_resume_from_signal (cs,NULL ); } } }else {
target-xtensa/helper.c +1 -1
@@ -92,7 +92,7 @@ void xtensa_breakpoint_handler(CPUXtensaState *env)if (cause) {debug_exception_env (env, cause); } -cpu_resume_from_signal (env,NULL ); +cpu_resume_from_signal (cs,NULL ); } } }
translate-all.c +3 -3
@@ -1113,7 +1113,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,itself */ cpu->current_tb =NULL ;tb_gen_code (cpu, current_pc, current_cs_base, current_flags,1 ); - cpu_resume_from_signal(env, NULL); + cpu_resume_from_signal(cpu, NULL); }#endif }
@@ -1213,7 +1213,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,if (locked) {mmap_unlock (); } - cpu_resume_from_signal(env, puc); + cpu_resume_from_signal(cpu, puc); }#endif }
@@ -1476,7 +1476,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)repeating the fault, which is horribly inefficient. Better would be to execute just this insn uncached, or generate a second new TB. */ -cpu_resume_from_signal (env,NULL ); +cpu_resume_from_signal (cpu,NULL ); }void tb_flush_jmp_cache (CPUState *cpu,target_ulong addr)
user-exec.c +1 -2
@@ -52,9 +52,8 @@ static void exception_action(CPUArchState *env1)/* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ -void cpu_resume_from_signal (CPUArchState *env1,void *puc) +void cpu_resume_from_signal (CPUState *cpu,void *puc) { -CPUState *cpu =ENV_GET_CPU (env1);#ifdef __linux__struct ucontext *uc = puc;#elif defined(__OpenBSD__)
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 53/58] target-cris: Replace DisasContext::env field with CRISCPU
In reply to Andreas FärberThis cleans up repeated cris_env_get_cpu() for cpu_abort().
Signed-off-by Andreas Färber <[email protected]>
--- target-cris/translate.c | 16 ++++++++-------- target-cris/translate_v10.c | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-)
target-cris/translate.c +8 -8
@@ -74,7 +74,7 @@ static TCGv env_pc;/* This is the state at translation time. */ typedef struct DisasContext { - CPUCRISState *env; + CRISCPU *cpu; target_ulong pc, ppc; /* Decoder. */
@@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int line) {printf ("BUG: pc=%x %s %d\n" , dc->pc, file, line);qemu_log ("BUG: pc=%x %s %d\n" , dc->pc, file, line); -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"%s:%d\n" , file, line); +cpu_abort (CPU (dc->cpu),"%s:%d\n" , file, line); } static const char *regnames[] =
@@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,break ; }default : -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"Invalid fetch size %d\n" , size); +cpu_abort (CPU (dc->cpu),"Invalid fetch size %d\n" , size);break ; }return r;
@@ -1125,7 +1125,7 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)static void gen_load64 (DisasContext *dc,TCGv_i64 dst,TCGv addr) { -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env);/* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */
@@ -1139,7 +1139,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)static void gen_load (DisasContext *dc,TCGv dst,TCGv addr,unsigned int size,int sign) { -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env);/* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */
@@ -1154,7 +1154,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,static void gen_store (DisasContext *dc,TCGv addr,TCGv val,unsigned int size) { -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env);/* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */
@@ -3170,7 +3170,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,* delayslot, like in real hw. */ pc_start = tb->pc & ~1 ; - dc->env = env; + dc->cpu = cpu; dc->tb = tb; gen_opc_end = tcg_ctx.gen_opc_buf +OPC_MAX_SIZE ;
@@ -3391,7 +3391,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,#if !DISAS_CRIS if (qemu_loglevel_mask (CPU_LOG_TB_IN_ASM )) {log_target_disas (env, pc_start, dc->pc - pc_start, - dc->env->pregs[PR_VR ]); + env->pregs[PR_VR ]);qemu_log ("\nisize=%d osize=%td\n" , dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf); }
target-cris/translate_v10.c +8 -8
@@ -96,7 +96,7 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,static void gen_store_v10 (DisasContext *dc,TCGv addr,TCGv val,unsigned int size) { -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env);/* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */
@@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)default :LOG_DIS ("pc=%x mode=%x quickimm %d r%d r%d\n" , dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"Unhandled quickimm\n" ); +cpu_abort (CPU (dc->cpu),"Unhandled quickimm\n" );break ; }return 2 ;
@@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc)case 2 : tmp =1 ;break ;case 1 : tmp =0 ;break ;default : -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"Unhandled BIAP" ); +cpu_abort (CPU (dc->cpu),"Unhandled BIAP" );break ; }
@@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc)default :LOG_DIS ("pc=%x reg %d r%d r%d\n" , dc->pc, dc->opcode, dc->src, dc->dst); -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"Unhandled opcode" ); +cpu_abort (CPU (dc->cpu),"Unhandled opcode" );break ; } }else {
@@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc)default :LOG_DIS ("pc=%x reg %d r%d r%d\n" , dc->pc, dc->opcode, dc->src, dc->dst); -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"Unhandled opcode" ); +cpu_abort (CPU (dc->cpu),"Unhandled opcode" );break ; } }
@@ -1006,7 +1006,7 @@ static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)if (!dc->postinc && (dc->ir & (1 <<11 ))) {int simm = dc->ir &0xff ; -/* cpu_abort(dc->env, "Unhandled opcode"); */ +/* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */ /* sign extended. */ simm = (int8_t )simm;
@@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)default :LOG_DIS ("pc=%x var-ind.%d %d r%d r%d\n" , dc->pc, size, dc->opcode, dc->src, dc->dst); -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"Unhandled opcode" ); +cpu_abort (CPU (dc->cpu),"Unhandled opcode" );break ; }return insn_len;
@@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)break ;default :LOG_DIS ("ERROR pc=%x opcode=%d\n" , dc->pc, dc->opcode); -cpu_abort (CPU (cris_env_get_cpu (dc->env)),"Unhandled opcode" ); +cpu_abort (CPU (dc->cpu),"Unhandled opcode" );break ; }
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 54/58] target-microblaze: Replace DisasContext::env field with MicroBlazeCPU
In reply to Andreas FärberThis cleans up some mb_env_get_cpu() needed for cpu_abort().
Signed-off-by Andreas Färber <[email protected]>
--- target-microblaze/translate.c | 87 +++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 44 deletions(-)
target-microblaze/translate.c +43 -44
@@ -56,7 +56,7 @@ static TCGv env_res_val;/* This is the state at translation time. */ typedef struct DisasContext { - CPUMBState *env; + MicroBlazeCPU *cpu; target_ulong pc; /* Decoder. */
@@ -327,8 +327,8 @@ static void dec_pattern(DisasContext *dc)int l1;if ((dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) - && !((dc->env->pvr.regs[2 ] &PVR2_USE_PCMP_INSTR ))) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) + && !((dc->cpu->env.pvr.regs[2 ] &PVR2_USE_PCMP_INSTR ))) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP ); }
@@ -370,7 +370,7 @@ static void dec_pattern(DisasContext *dc) }break ;default : -cpu_abort (CPU (mb_env_get_cpu (dc->env)), +cpu_abort (CPU (dc->cpu),"unsupported pattern insn opcode=%x\n" , dc->opcode);break ; }
@@ -441,11 +441,10 @@ static inline void msr_write(DisasContext *dc, TCGv v)static void dec_msr (DisasContext *dc) { -MicroBlazeCPU *cpu =mb_env_get_cpu (dc->env); -CPUState *cs =CPU (cpu); +CPUState *cs =CPU (dc->cpu);TCGv t0, t1;unsigned int sr, to, rn; -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env); sr = dc->imm & ((1 <<14 ) -1 ); to = dc->imm & (1 <<14 );
@@ -460,7 +459,7 @@ static void dec_msr(DisasContext *dc)LOG_DIS ("msr%s r%d imm=%x\n" , clr ?"clr" :"set" , dc->rd, dc->imm); -if (!(dc->env->pvr.regs[2 ] &PVR2_USE_MSR_INSTR )) { +if (!(dc->cpu->env.pvr.regs[2 ] &PVR2_USE_MSR_INSTR )) {/* nop??? */ return ; }
@@ -539,7 +538,7 @@ static void dec_msr(DisasContext *dc)tcg_gen_st_tl (cpu_R[dc->ra], cpu_env, offsetof(CPUMBState , shr));break ;default : -cpu_abort (CPU (mb_env_get_cpu (dc->env)),"unknown mts reg %x\n" , sr); +cpu_abort (CPU (dc->cpu),"unknown mts reg %x\n" , sr);break ; } }else {
@@ -645,8 +644,8 @@ static void dec_mul(DisasContext *dc)unsigned int subcode;if ((dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) - && !(dc->env->pvr.regs[0 ] &PVR0_USE_HW_MUL_MASK )) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) + && !(dc->cpu->env.pvr.regs[0 ] &PVR0_USE_HW_MUL_MASK )) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP );return ;
@@ -664,7 +663,7 @@ static void dec_mul(DisasContext *dc)/* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ if (subcode >=1 && subcode <=3 - && !((dc->env->pvr.regs[2 ] &PVR2_USE_MUL64_MASK ))) { + && !((dc->cpu->env.pvr.regs[2 ] &PVR2_USE_MUL64_MASK ))) {/* nop??? */ }
@@ -686,7 +685,7 @@ static void dec_mul(DisasContext *dc)t_gen_mulu (d[0 ], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);break ;default : -cpu_abort (CPU (mb_env_get_cpu (dc->env)),"unknown MUL insn %x\n" , subcode); +cpu_abort (CPU (dc->cpu),"unknown MUL insn %x\n" , subcode);break ; } done:
@@ -702,8 +701,8 @@ static void dec_div(DisasContext *dc) u = dc->imm &2 ;LOG_DIS ("div\n" ); -if ((dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) - && !((dc->env->pvr.regs[0 ] &PVR0_USE_DIV_MASK ))) { +if ((dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) + && !((dc->cpu->env.pvr.regs[0 ] &PVR0_USE_DIV_MASK ))) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP ); }
@@ -724,8 +723,8 @@ static void dec_barrel(DisasContext *dc)unsigned int s, t;if ((dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) - && !(dc->env->pvr.regs[0 ] &PVR0_USE_BARREL_MASK )) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) + && !(dc->cpu->env.pvr.regs[0 ] &PVR0_USE_BARREL_MASK )) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP );return ;
@@ -754,11 +753,10 @@ static void dec_barrel(DisasContext *dc)static void dec_bit (DisasContext *dc) { -MicroBlazeCPU *cpu =mb_env_get_cpu (dc->env); -CPUState *cs =CPU (cpu); +CPUState *cs =CPU (dc->cpu);TCGv t0;unsigned int op; -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env); op = dc->ir & ((1 <<9 ) -1 );switch (op) {
@@ -823,12 +821,12 @@ static void dec_bit(DisasContext *dc)break ;case 0xe0 :if ((dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) - && !((dc->env->pvr.regs[2 ] &PVR2_USE_PCMP_INSTR ))) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) + && !((dc->cpu->env.pvr.regs[2 ] &PVR2_USE_PCMP_INSTR ))) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP ); } -if (dc->env->pvr.regs[2 ] &PVR2_USE_PCMP_INSTR ) { +if (dc->cpu->env.pvr.regs[2 ] &PVR2_USE_PCMP_INSTR ) {gen_helper_clz (cpu_R[dc->rd], cpu_R[dc->ra]); }break ;
@@ -937,7 +935,7 @@ static void dec_load(DisasContext *dc) }if (size >4 && (dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK )) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK )) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP );return ;
@@ -995,7 +993,7 @@ static void dec_load(DisasContext *dc) }break ;default : -cpu_abort (CPU (mb_env_get_cpu (dc->env)),"Invalid reverse size\n" ); +cpu_abort (CPU (dc->cpu),"Invalid reverse size\n" );break ; } }
@@ -1022,9 +1020,9 @@ static void dec_load(DisasContext *dc)* address and if that succeeds we write into the destination reg. */ v =tcg_temp_new (); -tcg_gen_qemu_ld_tl (v, *addr,cpu_mmu_index (dc->env), mop); +tcg_gen_qemu_ld_tl (v, *addr,cpu_mmu_index (&dc->cpu->env), mop); -if ((dc->env->pvr.regs[2 ] &PVR2_UNALIGNED_EXC_MASK ) && size >1 ) { +if ((dc->cpu->env.pvr.regs[2 ] &PVR2_UNALIGNED_EXC_MASK ) && size >1 ) {tcg_gen_movi_tl (cpu_SR[SR_PC ], dc->pc);gen_helper_memalign (cpu_env, *addr,tcg_const_tl (dc->rd),tcg_const_tl (0 ),tcg_const_tl (size -1 ));
@@ -1067,7 +1065,7 @@ static void dec_store(DisasContext *dc) }if (size >4 && (dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK )) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK )) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP );return ;
@@ -1100,7 +1098,8 @@ static void dec_store(DisasContext *dc)this compare and the following write to be atomic. For user emulation we need to add atomicity between threads. */ tval =tcg_temp_new (); -tcg_gen_qemu_ld_tl (tval, swx_addr,cpu_mmu_index (dc->env),MO_TEUL ); +tcg_gen_qemu_ld_tl (tval, swx_addr,cpu_mmu_index (&dc->cpu->env), +MO_TEUL );tcg_gen_brcond_tl (TCG_COND_NE , env_res_val, tval, swx_skip);write_carryi (dc,0 );tcg_temp_free (tval);
@@ -1146,14 +1145,14 @@ static void dec_store(DisasContext *dc) }break ;default : -cpu_abort (CPU (mb_env_get_cpu (dc->env)),"Invalid reverse size\n" ); +cpu_abort (CPU (dc->cpu),"Invalid reverse size\n" );break ; } } -tcg_gen_qemu_st_tl (cpu_R[dc->rd], *addr,cpu_mmu_index (dc->env), mop); +tcg_gen_qemu_st_tl (cpu_R[dc->rd], *addr,cpu_mmu_index (&dc->cpu->env), mop);/* Verify alignment if needed. */ -if ((dc->env->pvr.regs[2 ] &PVR2_UNALIGNED_EXC_MASK ) && size >1 ) { +if ((dc->cpu->env.pvr.regs[2 ] &PVR2_UNALIGNED_EXC_MASK ) && size >1 ) {tcg_gen_movi_tl (cpu_SR[SR_PC ], dc->pc);/* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe
@@ -1197,7 +1196,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc,tcg_gen_setcond_tl (TCG_COND_GT , d, a, b);break ;default : -cpu_abort (CPU (mb_env_get_cpu (dc->env)),"Unknown condition code %x.\n" , cc); +cpu_abort (CPU (dc->cpu),"Unknown condition code %x.\n" , cc);break ; } }
@@ -1248,7 +1247,7 @@ static void dec_bcc(DisasContext *dc)static void dec_br (DisasContext *dc) {unsigned int dslot, link, abs, mbar; -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env); dslot = dc->ir & (1 <<20 ); abs = dc->ir & (1 <<19 );
@@ -1380,7 +1379,7 @@ static inline void do_rte(DisasContext *dc)static void dec_rts (DisasContext *dc) {unsigned int b_bit, i_bit, e_bit; -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env); i_bit = dc->ir & (1 <<21 ); b_bit = dc->ir & (1 <<22 );
@@ -1427,7 +1426,7 @@ static int dec_check_fpuv2(DisasContext *dc) {int r; - r = dc->env->pvr.regs[2 ] &PVR2_USE_FPU2_MASK ; + r = dc->cpu->env.pvr.regs[2 ] &PVR2_USE_FPU2_MASK ;if (!r && (dc->tb_flags &MSR_EE_FLAG )) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_FPU );
@@ -1441,8 +1440,8 @@ static void dec_fpu(DisasContext *dc)unsigned int fpu_insn;if ((dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) - && !((dc->env->pvr.regs[2 ] &PVR2_USE_FPU_MASK ))) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) + && !((dc->cpu->env.pvr.regs[2 ] &PVR2_USE_FPU_MASK ))) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP );return ;
@@ -1544,7 +1543,7 @@ static void dec_fpu(DisasContext *dc)static void dec_null (DisasContext *dc) {if ((dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK )) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK )) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP );return ;
@@ -1556,7 +1555,7 @@ static void dec_null(DisasContext *dc)/* Insns connected to FSL or AXI stream attached devices. */ static void dec_stream (DisasContext *dc) { -int mem_index =cpu_mmu_index (dc->env); +int mem_index =cpu_mmu_index (&dc->cpu->env);TCGv_i32 t_id, t_ctrl;int ctrl;
@@ -1632,8 +1631,8 @@ static inline void decode(DisasContext *dc, uint32_t ir) dc->nr_nops =0 ; else {if ((dc->tb_flags &MSR_EE_FLAG ) - && (dc->env->pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) - && (dc->env->pvr.regs[2 ] & PVR2_OPCODE_0x0_ILL_MASK)) { + && (dc->cpu->env.pvr.regs[2 ] &PVR2_ILL_OPCODE_EXC_MASK ) + && (dc->cpu->env.pvr.regs[2 ] & PVR2_OPCODE_0x0_ILL_MASK)) {tcg_gen_movi_tl (cpu_SR[SR_ESR ],ESR_EC_ILLEGAL_OP );t_gen_raise_exception (dc,EXCP_HW_EXCP );return ;
@@ -1642,7 +1641,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)LOG_DIS ("nr_nops=%d\t" , dc->nr_nops); dc->nr_nops++;if (dc->nr_nops >4 ) { -cpu_abort (CPU (mb_env_get_cpu (dc->env)),"fetching nop sequence\n" ); +cpu_abort (CPU (dc->cpu),"fetching nop sequence\n" ); } }/* bit 2 seems to indicate insn type. */
@@ -1696,7 +1695,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,int max_insns; pc_start = tb->pc; - dc->env = env; + dc->cpu = cpu; dc->tb = tb; org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 55/58] cputlb: Change tlb_flush_page() argument to CPUState
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- cputlb.c | 4 +-- exec.c | 7 ++---- include/exec/exec-all.h | 4 +-- target-alpha/sys_helper.c | 2 +- target-arm/helper.c | 14 ++++++++--- target-cris/mmu.c | 3 ++- target-cris/op_helper.c | 12 ++++++--- target-i386/misc_helper.c | 4 ++- target-i386/svm_helper.c | 3 ++- target-microblaze/mmu.c | 3 ++- target-mips/helper.c | 8 ++++-- target-openrisc/sys_helper.c | 4 +-- target-ppc/mmu_helper.c | 58 +++++++++++++++++++++++++------------------- target-s390x/mem_helper.c | 6 ++--- target-s390x/misc_helper.c | 6 +++-- target-sh4/helper.c | 19 +++++++++------ target-sparc/ldst_helper.c | 9 ++++--- target-xtensa/op_helper.c | 10 +++++--- 18 files changed, 106 insertions(+), 70 deletions(-)
cputlb.c +2 -2
@@ -77,9 +77,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) } } -void tlb_flush_page (CPUArchState *env,target_ulong addr) +void tlb_flush_page (CPUState *cpu,target_ulong addr) { -CPUState *cpu =ENV_GET_CPU (env); +CPUArchState *env = cpu->env_ptr;int i;int mmu_idx;
exec.c +2 -5
@@ -543,7 +543,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,int cpu_watchpoint_insert (CPUState *cpu,vaddr addr,vaddr len,int flags,CPUWatchpoint **watchpoint) { -CPUArchState *env = cpu->env_ptr;vaddr len_mask = ~(len -1 );CPUWatchpoint *wp;
@@ -567,7 +566,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,QTAILQ_INSERT_TAIL (&cpu->watchpoints, wp, entry); } -tlb_flush_page (env, addr); +tlb_flush_page (cpu, addr);if (watchpoint) *watchpoint = wp;
@@ -594,11 +593,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,/* Remove a specific watchpoint by reference. */ void cpu_watchpoint_remove_by_ref (CPUState *cpu,CPUWatchpoint *watchpoint) { -CPUArchState *env = cpu->env_ptr; -QTAILQ_REMOVE (&cpu->watchpoints, watchpoint, entry); -tlb_flush_page (env, watchpoint->vaddr); +tlb_flush_page (cpu, watchpoint->vaddr);g_free (watchpoint); }
include/exec/exec-all.h +2 -2
@@ -98,14 +98,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,#if !defined(CONFIG_USER_ONLY )void tcg_cpu_address_space_init (CPUState *cpu,AddressSpace *as);/* cputlb.c */ -void tlb_flush_page (CPUArchState *env,target_ulong addr); +void tlb_flush_page (CPUState *cpu,target_ulong addr);void tlb_flush (CPUArchState *env,int flush_global);void tlb_set_page (CPUArchState *env,target_ulong vaddr,hwaddr paddr,int prot,int mmu_idx,target_ulong size);void tb_invalidate_phys_addr (AddressSpace *as,hwaddr addr);#else -static inline void tlb_flush_page (CPUArchState *env,target_ulong addr) +static inline void tlb_flush_page (CPUState *cpu,target_ulong addr) { }
target-alpha/sys_helper.c +1 -1
@@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env)void helper_tbis (CPUAlphaState *env,uint64_t p) { -tlb_flush_page (env, p); +tlb_flush_page (CPU (alpha_env_get_cpu (env)), p); }void helper_tb_flush (CPUAlphaState *env)
target-arm/helper.c +10 -4
@@ -342,7 +342,9 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) {/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ -tlb_flush_page (env, value &TARGET_PAGE_MASK ); +ARMCPU *cpu =arm_env_get_cpu (env); + +tlb_flush_page (CPU (cpu), value &TARGET_PAGE_MASK ); } static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -356,7 +358,9 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) {/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ -tlb_flush_page (env, value &TARGET_PAGE_MASK ); +ARMCPU *cpu =arm_env_get_cpu (env); + +tlb_flush_page (CPU (cpu), value &TARGET_PAGE_MASK ); }static const ARMCPRegInfo cp_reginfo[] = {
@@ -1686,16 +1690,18 @@ static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) {/* Invalidate by VA (AArch64 version) */ +ARMCPU *cpu =arm_env_get_cpu (env);uint64_t pageaddr = value <<12 ; -tlb_flush_page (env, pageaddr); +tlb_flush_page (CPU (cpu), pageaddr); }static void tlbi_aa64_vaa_write (CPUARMState *env,const ARMCPRegInfo *ri,uint64_t value) {/* Invalidate by VA, all ASIDs (AArch64 version) */ +ARMCPU *cpu =arm_env_get_cpu (env);uint64_t pageaddr = value <<12 ; -tlb_flush_page (env, pageaddr); +tlb_flush_page (CPU (cpu), pageaddr); } static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
target-cris/mmu.c +2 -1
@@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,void cris_mmu_flush_pid (CPUCRISState *env,uint32_t pid) { +CRISCPU *cpu =cris_env_get_cpu (env);target_ulong vaddr;unsigned int idx;uint32_t lo, hi;
@@ -315,7 +316,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) vaddr = tlb_vpn <<TARGET_PAGE_BITS ;D_LOG ("flush pid=%x vaddr=%x\n" , pid, vaddr); -tlb_flush_page (env, vaddr); +tlb_flush_page (CPU (cpu), vaddr); } } }
target-cris/op_helper.c +9 -3
@@ -98,8 +98,11 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)void helper_spc_write (CPUCRISState *env,uint32_t new_spc) {#if !defined(CONFIG_USER_ONLY ) -tlb_flush_page (env, env->pregs[PR_SPC ]); -tlb_flush_page (env, new_spc); +CRISCPU *cpu =cris_env_get_cpu (env); +CPUState *cs =CPU (cpu); + +tlb_flush_page (cs, env->pregs[PR_SPC ]); +tlb_flush_page (cs, new_spc);#endif }
@@ -114,6 +117,9 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)void helper_movl_sreg_reg (CPUCRISState *env,uint32_t sreg,uint32_t reg) { +#if !defined(CONFIG_USER_ONLY ) +CRISCPU *cpu =cris_env_get_cpu (env); +#endif uint32_t srs; srs = env->pregs[PR_SRS ]; srs &=3 ;
@@ -155,7 +161,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)D_LOG ("tlb flush vaddr=%x v=%d pc=%x\n" , vaddr, tlb_v, env->pc);if (tlb_v) { -tlb_flush_page (env, vaddr); +tlb_flush_page (CPU (cpu), vaddr); } } }
target-i386/misc_helper.c +3 -1
@@ -221,8 +221,10 @@ void helper_lmsw(CPUX86State *env, target_ulong t0)void helper_invlpg (CPUX86State *env,target_ulong addr) { +X86CPU *cpu =x86_env_get_cpu (env); +cpu_svm_check_intercept_param (env,SVM_EXIT_INVLPG ,0 ); -tlb_flush_page (env, addr); +tlb_flush_page (CPU (cpu), addr); }void helper_rdtsc (CPUX86State *env)
target-i386/svm_helper.c +2 -1
@@ -469,6 +469,7 @@ void helper_skinit(CPUX86State *env)void helper_invlpga (CPUX86State *env,int aflag) { +X86CPU *cpu =x86_env_get_cpu (env);target_ulong addr;cpu_svm_check_intercept_param (env,SVM_EXIT_INVLPGA ,0 );
@@ -481,7 +482,7 @@ void helper_invlpga(CPUX86State *env, int aflag)/* XXX: could use the ASID to see if it is needed to do the flush */ -tlb_flush_page (env, addr); +tlb_flush_page (CPU (cpu), addr); } void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
target-microblaze/mmu.c +2 -1
@@ -34,6 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f)static void mmu_flush_idx (CPUMBState *env,unsigned int idx) { +CPUState *cs =CPU (mb_env_get_cpu (env));struct microblaze_mmu *mmu = &env->mmu;unsigned int tlb_size;uint32_t tlb_tag, end, t;
@@ -47,7 +48,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx) end = tlb_tag + tlb_size;while (tlb_tag < end) { -tlb_flush_page (env, tlb_tag); +tlb_flush_page (cs, tlb_tag); tlb_tag +=TARGET_PAGE_SIZE ; } }
target-mips/helper.c +6 -2
@@ -653,6 +653,8 @@ void mips_cpu_do_interrupt(CPUState *cs)#if !defined(CONFIG_USER_ONLY )void r4k_invalidate_tlb (CPUMIPSState *env,int idx,int use_extra) { +MIPSCPU *cpu =mips_env_get_cpu (env); +CPUState *cs;r4k_tlb_t *tlb;target_ulong addr;target_ulong end;
@@ -678,6 +680,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)/* 1k pages are not supported. */ mask = tlb->PageMask | ~(TARGET_PAGE_MASK <<1 );if (tlb->V0) { + cs =CPU (cpu); addr = tlb->VPN & ~mask;#if defined(TARGET_MIPS64 )if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@@ -686,11 +689,12 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)#endif end = addr | (mask >>1 );while (addr < end) { -tlb_flush_page (env, addr); +tlb_flush_page (cs, addr); addr +=TARGET_PAGE_SIZE ; } }if (tlb->V1) { + cs =CPU (cpu); addr = (tlb->VPN & ~mask) | ((mask >>1 ) +1 );#if defined(TARGET_MIPS64 )if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@@ -699,7 +703,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)#endif end = addr | mask;while (addr -1 < end) { -tlb_flush_page (env, addr); +tlb_flush_page (cs, addr); addr +=TARGET_PAGE_SIZE ; } }
target-openrisc/sys_helper.c +2 -2
@@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr -TO_SPR (1 ,512 );if (!(rb &1 )) { -tlb_flush_page (env, env->tlb->dtlb[0 ][idx].mr &TARGET_PAGE_MASK ); +tlb_flush_page (cs, env->tlb->dtlb[0 ][idx].mr &TARGET_PAGE_MASK ); } env->tlb->dtlb[0 ][idx].mr = rb;break ;
@@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr -TO_SPR (2 ,512 );if (!(rb &1 )) { -tlb_flush_page (env, env->tlb->itlb[0 ][idx].mr &TARGET_PAGE_MASK ); +tlb_flush_page (cs, env->tlb->itlb[0 ][idx].mr &TARGET_PAGE_MASK ); } env->tlb->itlb[0 ][idx].mr = rb;break ;
target-ppc/mmu_helper.c +33 -25
157 lines not on this page · raw message
target-s390x/mem_helper.c +3 -3
@@ -1027,13 +1027,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)/* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ -tlb_flush_page (env, page); +tlb_flush_page (cs, page);/* XXX 31-bit hack */ if (page &0x80000000 ) { -tlb_flush_page (env, page & ~0x80000000 ); +tlb_flush_page (cs, page & ~0x80000000 ); }else { -tlb_flush_page (env, page |0x80000000 ); +tlb_flush_page (cs, page |0x80000000 ); } }
target-s390x/misc_helper.c +4 -2
@@ -237,11 +237,13 @@ uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,/* Set Prefix */ void HELPER (spx )(CPUS390XState *env,uint64_t a1) { +CPUState *cs =CPU (s390_env_get_cpu (env));uint32_t prefix = a1 &0x7fffe000 ; + env->psa = prefix;qemu_log ("prefix: %#x\n" , prefix); -tlb_flush_page (env,0 ); -tlb_flush_page (env,TARGET_PAGE_SIZE ); +tlb_flush_page (cs,0 ); +tlb_flush_page (cs,TARGET_PAGE_SIZE ); }static inline uint64_t clock_value (CPUS390XState *env)
target-sh4/helper.c +11 -8
@@ -304,7 +304,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) itlb =itlb_replacement (env); ientry = &env->itlb[itlb];if (ientry->v) { -tlb_flush_page (env, ientry->vpn <<10 ); +tlb_flush_page (CPU (sh_env_get_cpu (env)), ientry->vpn <<10 ); } *ientry = env->utlb[utlb];update_itlb_use (env, itlb);
@@ -535,7 +535,7 @@ void cpu_load_tlb(CPUSH4State * env)if (entry->v) {/* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn <<10 ; -tlb_flush_page (env, address); +tlb_flush_page (CPU (cpu), address); }/* Take values into cpu status from registers. */
@@ -611,7 +611,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,if (entry->v) {/* Overwriting valid entry in itlb. */ target_ulong address = entry->vpn <<10 ; -tlb_flush_page (s, address); +tlb_flush_page (CPU (sh_env_get_cpu (s)), address); } entry->asid = asid; entry->vpn = vpn;
@@ -653,7 +653,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,if (entry->v) {/* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn <<10 ; -tlb_flush_page (s, address); +tlb_flush_page (CPU (sh_env_get_cpu (s)), address); } entry->ppn = (mem_value &0x1ffffc00 ) >>10 ; entry->v = (mem_value &0x00000100 ) >>8 ;
@@ -737,16 +737,19 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, } } -if (needs_tlb_flush) -tlb_flush_page (s, vpn <<10 ); +if (needs_tlb_flush) { +tlb_flush_page (CPU (sh_env_get_cpu (s)), vpn <<10 ); + } }else {int index = (addr &0x00003f00 ) >>8 ;tlb_t * entry = &s->utlb[index];if (entry->v) { +CPUState *cs =CPU (sh_env_get_cpu (s)); +/* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn <<10 ; -tlb_flush_page (s, address); +tlb_flush_page (cs, address); } entry->asid = asid; entry->vpn = vpn;
@@ -797,7 +800,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,if (entry->v) {/* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn <<10 ; -tlb_flush_page (s, address); +tlb_flush_page (CPU (sh_env_get_cpu (s)), address); } entry->ppn = (mem_value &0x1ffffc00 ) >>10 ; entry->v = (mem_value &0x00000100 ) >>8 ;
target-sparc/ldst_helper.c +6 -3
@@ -141,6 +141,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,/* flush page range if translation is valid */ if (TTE_IS_VALID (tlb->tte)) { +CPUState *cs =CPU (sparc_env_get_cpu (env1)); mask =0xffffffffffffe000ULL ; mask <<=3 * ((tlb->tte >>61 ) &3 );
@@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb, va = tlb->tag & mask;for (offset =0 ; offset < size; offset +=TARGET_PAGE_SIZE ) { -tlb_flush_page (env1, va + offset); +tlb_flush_page (cs, va + offset); } }
@@ -716,7 +717,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,void helper_st_asi (CPUSPARCState *env,target_ulong addr,uint64_t val,int asi,int size) { -CPUState *cs =CPU (sparc_env_get_cpu (env)); +SPARCCPU *cpu =sparc_env_get_cpu (env); +CPUState *cs =CPU (cpu); +helper_check_align (env, addr, size -1 );switch (asi) {case 2 :/* SuperSparc MXCC registers and Leon3 cache control */
@@ -862,7 +865,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,DPRINTF_MMU ("mmu flush level %d\n" , mmulev);switch (mmulev) {case 0 :/* flush page */ -tlb_flush_page (env, addr &0xfffff000 ); +tlb_flush_page (CPU (cpu), addr &0xfffff000 );break ;case 1 :/* flush segment (256k) */ case 2 :/* flush region (16M) */
target-xtensa/op_helper.c +6 -4
@@ -687,7 +687,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)uint32_t wi;xtensa_tlb_entry *entry =get_tlb_entry (env, v, dtlb, &wi);if (entry->variable && entry->asid) { -tlb_flush_page (env, entry->vaddr); +tlb_flush_page (CPU (xtensa_env_get_cpu (env)), entry->vaddr); entry->asid =0 ; } }
@@ -732,21 +732,23 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,void xtensa_tlb_set_entry (CPUXtensaState *env,bool dtlb,unsigned wi,unsigned ei,uint32_t vpn,uint32_t pte) { +XtensaCPU *cpu =xtensa_env_get_cpu (env); +CPUState *cs =CPU (cpu);xtensa_tlb_entry *entry =xtensa_tlb_get_entry (env, dtlb, wi, ei);if (xtensa_option_enabled (env->config,XTENSA_OPTION_MMU )) {if (entry->variable) {if (entry->asid) { -tlb_flush_page (env, entry->vaddr); +tlb_flush_page (cs, entry->vaddr); }xtensa_tlb_set_entry_mmu (env, entry, dtlb, wi, ei, vpn, pte); -tlb_flush_page (env, entry->vaddr); +tlb_flush_page (cs, entry->vaddr); }else {qemu_log ("%s %d, %d, %d trying to set immutable entry\n" , __func__, dtlb, wi, ei); } }else { -tlb_flush_page (env, entry->vaddr); +tlb_flush_page (cs, entry->vaddr);if (xtensa_option_enabled (env->config,XTENSA_OPTION_REGION_TRANSLATION )) { entry->paddr = pte ®ION_PAGE_MASK ;
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 56/58] cputlb: Change tlb_flush() argument to CPUState
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- cputlb.c | 6 +++--- exec.c | 4 +--- hw/sh4/sh7750.c | 2 +- include/exec/exec-all.h | 4 ++-- target-alpha/cpu.c | 2 +- target-alpha/sys_helper.c | 2 +- target-arm/cpu.c | 2 +- target-arm/helper.c | 39 ++++++++++++++++++++++++--------- target-cris/cpu.c | 2 +- target-i386/cpu.c | 2 +- target-i386/helper.c | 17 ++++++++++----- target-i386/machine.c | 2 +- target-i386/svm_helper.c | 2 +- target-lm32/cpu.c | 2 +- target-m68k/cpu.c | 2 +- target-microblaze/cpu.c | 2 +- target-microblaze/mmu.c | 3 ++- target-mips/cpu.c | 2 +- target-mips/machine.c | 3 ++- target-mips/op_helper.c | 4 +++- target-moxie/cpu.c | 2 +- target-openrisc/cpu.c | 2 +- target-openrisc/interrupt.c | 2 +- target-openrisc/interrupt_helper.c | 2 +- target-openrisc/sys_helper.c | 2 +- target-ppc/excp_helper.c | 4 ++-- target-ppc/helper_regs.h | 2 +- target-ppc/misc_helper.c | 4 +++- target-ppc/mmu-hash64.c | 6 ++++-- target-ppc/mmu_helper.c | 44 ++++++++++++++++++++++++-------------- target-ppc/translate_init.c | 2 +- target-s390x/cpu.c | 4 ++-- target-s390x/mem_helper.c | 13 +++++++---- target-sh4/cpu.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/cpu.c | 2 +- target-sparc/ldst_helper.c | 18 +++++++++------- target-sparc/machine.c | 3 ++- target-unicore32/cpu.c | 2 +- target-unicore32/helper.c | 4 +++- target-xtensa/op_helper.c | 4 +++- 41 files changed, 143 insertions(+), 87 deletions(-)
cputlb.c +3 -3
@@ -46,9 +46,9 @@ int tlb_flush_count;* entries from the TLB at any time, so flushing more entries than * required is only an efficiency issue, not a correctness issue. */ -void tlb_flush (CPUArchState *env,int flush_global) +void tlb_flush (CPUState *cpu,int flush_global) { -CPUState *cpu =ENV_GET_CPU (env); +CPUArchState *env = cpu->env_ptr;#if defined(DEBUG_TLB )printf ("tlb_flush:\n" );
@@ -93,7 +93,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) TARGET_FMT_lx"/" TARGET_FMT_lx")\n" , env->tlb_flush_addr, env->tlb_flush_mask);#endif -tlb_flush (env,1 ); +tlb_flush (cpu,1 );return ; }/* must reset current TB so that interrupts cannot modify the
exec.c +1 -3
@@ -1834,14 +1834,12 @@ static void tcg_commit(MemoryListener *listener)reset the modified entries */ /* XXX: slow ! */ CPU_FOREACH (cpu) { -CPUArchState *env = cpu->env_ptr; -/* FIXME: Disentangle the cpu.h circular files deps so we can directly get the right CPU from listener. */ if (cpu->tcg_as_listener != listener) {continue ; } -tlb_flush (env,1 ); +tlb_flush (cpu,1 ); } }
hw/sh4/sh7750.c +1 -1
@@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,case SH7750_PTEH_A7 :/* If asid changes, clear all registered tlb entries. */ if ((s->cpu->env.pteh &0xff ) != (mem_value &0xff )) { -tlb_flush (&s->cpu->env,1 ); +tlb_flush (CPU (s->cpu),1 ); } s->cpu->env.pteh = mem_value;return ;
include/exec/exec-all.h +2 -2
@@ -99,7 +99,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,void tcg_cpu_address_space_init (CPUState *cpu,AddressSpace *as);/* cputlb.c */ void tlb_flush_page (CPUState *cpu,target_ulong addr); -void tlb_flush (CPUArchState *env,int flush_global); +void tlb_flush (CPUState *cpu,int flush_global);void tlb_set_page (CPUArchState *env,target_ulong vaddr,hwaddr paddr,int prot,int mmu_idx,target_ulong size);
@@ -109,7 +109,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } -static inline void tlb_flush (CPUArchState *env,int flush_global) +static inline void tlb_flush (CPUState *cpu,int flush_global) { }#endif
target-alpha/cpu.c +1 -1
@@ -258,7 +258,7 @@ static void alpha_cpu_initfn(Object *obj) cs->env_ptr = env;cpu_exec_init (env); -tlb_flush (env,1 ); +tlb_flush (cs,1 );alpha_translate_init ();
target-alpha/sys_helper.c +1 -1
@@ -64,7 +64,7 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs)void helper_tbia (CPUAlphaState *env) { -tlb_flush (env,1 ); +tlb_flush (CPU (alpha_env_get_cpu (env)),1 ); }void helper_tbis (CPUAlphaState *env,uint64_t p)
target-arm/cpu.c +1 -1
@@ -149,7 +149,7 @@ static void arm_cpu_reset(CPUState *s) &env->vfp.fp_status);set_float_detect_tininess (float_tininess_before_rounding, &env->vfp.standard_fp_status); -tlb_flush (env,1 ); +tlb_flush (s,1 );/* Reset is a state change for some CPUARMState fields which we * bake assumptions about into translated code, so we need to * tb_flush().
target-arm/helper.c +29 -10
@@ -303,17 +303,21 @@ void init_cpreg_list(ARMCPU *cpu)static void dacr_write (CPUARMState *env,const ARMCPRegInfo *ri,uint64_t value) { +ARMCPU *cpu =arm_env_get_cpu (env); + env->cp15.c3 = value; -tlb_flush (env,1 );/* Flush TLB as domain not tracked in TLB */ +tlb_flush (CPU (cpu),1 );/* Flush TLB as domain not tracked in TLB */ }static void fcse_write (CPUARMState *env,const ARMCPRegInfo *ri,uint64_t value) { +ARMCPU *cpu =arm_env_get_cpu (env); +if (env->cp15.c13_fcse != value) {/* Unlike real hardware the qemu TLB uses virtual addresses, * not modified virtual addresses, so this causes a TLB flush. */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); env->cp15.c13_fcse = value; } }
@@ -321,12 +325,14 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)static void contextidr_write (CPUARMState *env,const ARMCPRegInfo *ri,uint64_t value) { +ARMCPU *cpu =arm_env_get_cpu (env); +if (env->cp15.c13_context != value && !arm_feature (env,ARM_FEATURE_MPU )) {/* For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); } env->cp15.c13_context = value; }
@@ -335,7 +341,9 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) {/* Invalidate all (TLBIALL) */ -tlb_flush (env,1 ); +ARMCPU *cpu =arm_env_get_cpu (env); + +tlb_flush (CPU (cpu),1 ); } static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -351,7 +359,9 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) {/* Invalidate by ASID (TLBIASID) */ -tlb_flush (env, value ==0 ); +ARMCPU *cpu =arm_env_get_cpu (env); + +tlb_flush (CPU (cpu), value ==0 ); } static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1352,11 +1362,13 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,static void vmsa_ttbcr_write (CPUARMState *env,const ARMCPRegInfo *ri,uint64_t value) { +ARMCPU *cpu =arm_env_get_cpu (env); +if (arm_feature (env,ARM_FEATURE_LPAE )) {/* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }vmsa_ttbcr_raw_write (env, ri, value); }
@@ -1371,8 +1383,10 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)static void vmsa_tcr_el1_write (CPUARMState *env,const ARMCPRegInfo *ri,uint64_t value) { +ARMCPU *cpu =arm_env_get_cpu (env); +/* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); env->cp15.c2_control = value; }
@@ -1383,7 +1397,9 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,* must flush the TLB. */ if (cpreg_field_is_64bit (ri)) { -tlb_flush (env,1 ); +ARMCPU *cpu =arm_env_get_cpu (env); + +tlb_flush (CPU (cpu),1 ); }raw_write (env, ri, value); }
@@ -1708,8 +1724,9 @@ static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) {/* Invalidate by ASID (AArch64 version) */ +ARMCPU *cpu =arm_env_get_cpu (env);int asid =extract64 (value,48 ,16 ); -tlb_flush (env, asid ==0 ); +tlb_flush (CPU (cpu), asid ==0 ); }static const ARMCPRegInfo v8_cp_reginfo[] = {
@@ -1835,10 +1852,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {static void sctlr_write (CPUARMState *env,const ARMCPRegInfo *ri,uint64_t value) { +ARMCPU *cpu =arm_env_get_cpu (env); + env->cp15.c1_sys = value;/* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }static CPAccessResult ctr_el0_access (CPUARMState *env,const ARMCPRegInfo *ri)
target-cris/cpu.c +1 -1
@@ -51,7 +51,7 @@ static void cris_cpu_reset(CPUState *s) vr = env->pregs[PR_VR ];memset (env,0 , offsetof(CPUCRISState , load_info)); env->pregs[PR_VR ] = vr; -tlb_flush (env,1 ); +tlb_flush (s,1 );#if defined(CONFIG_USER_ONLY )/* start in user mode with interrupts enabled. */
target-i386/cpu.c +1 -1
@@ -2408,7 +2408,7 @@ static void x86_cpu_reset(CPUState *s)memset (env,0 , offsetof(CPUX86State , pat)); -tlb_flush (env,1 ); +tlb_flush (s,1 ); env->old_exception =-1 ;
target-i386/helper.c +12 -5
@@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) a20_state = (a20_state !=0 );if (a20_state != ((env->a20_mask >>20 ) &1 )) { +CPUState *cs =CPU (cpu); +#if defined(DEBUG_MMU )printf ("A20 update: a20=%d\n" , a20_state);#endif /* if the cpu is currently executing code, we must unlink it and all the potentially executing TB */ -cpu_interrupt (CPU (cpu),CPU_INTERRUPT_EXITTB ); +cpu_interrupt (cs,CPU_INTERRUPT_EXITTB );/* when a20 is changed, all the MMU mappings are invalid, so we must flush everything */ -tlb_flush (env,1 ); +tlb_flush (cs,1 ); env->a20_mask = ~(1 <<20 ) | (a20_state <<20 ); } }void cpu_x86_update_cr0 (CPUX86State *env,uint32_t new_cr0) { +X86CPU *cpu =x86_env_get_cpu (env);int pe_state;#if defined(DEBUG_MMU )
@@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)#endif if ((new_cr0 & (CR0_PG_MASK |CR0_WP_MASK |CR0_PE_MASK )) != (env->cr[0 ] & (CR0_PG_MASK |CR0_WP_MASK |CR0_PE_MASK ))) { -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }#ifdef TARGET_X86_64
@@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)the PDPT */ void cpu_x86_update_cr3 (CPUX86State *env,target_ulong new_cr3) { +X86CPU *cpu =x86_env_get_cpu (env); + env->cr[3 ] = new_cr3;if (env->cr[0 ] &CR0_PG_MASK ) {#if defined(DEBUG_MMU )printf ("CR3 update: CR3=" TARGET_FMT_lx"\n" , new_cr3);#endif -tlb_flush (env,0 ); +tlb_flush (CPU (cpu),0 ); } }void cpu_x86_update_cr4 (CPUX86State *env,uint32_t new_cr4) { +X86CPU *cpu =x86_env_get_cpu (env); +#if defined(DEBUG_MMU )printf ("CR4 update: CR4=%08x\n" , (uint32_t )env->cr[4 ]);#endif if ((new_cr4 ^ env->cr[4 ]) & (CR4_PGE_MASK |CR4_PAE_MASK |CR4_PSE_MASK |CR4_SMEP_MASK |CR4_SMAP_MASK )) { -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }/* SSE handling */ if (!(env->features[FEAT_1_EDX ] &CPUID_SSE )) {
target-i386/machine.c +1 -1
@@ -325,7 +325,7 @@ static int cpu_post_load(void *opaque, int version_id)for (i =0 ; i <DR7_MAX_BP ; i++) {hw_breakpoint_insert (env, i); } -tlb_flush (env,1 ); +tlb_flush (cs,1 );return 0 ; }
target-i386/svm_helper.c +1 -1
@@ -294,7 +294,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)break ;case TLB_CONTROL_FLUSH_ALL_ASID :/* FIXME: this is not 100% correct but should work for now */ -tlb_flush (env,1 ); +tlb_flush (cs,1 );break ; }
target-lm32/cpu.c +1 -1
@@ -128,7 +128,7 @@ static void lm32_cpu_reset(CPUState *s)memset (env,0 , offsetof(CPULM32State , eba));lm32_cpu_init_cfg_reg (cpu); -tlb_flush (env,1 ); +tlb_flush (s,1 ); }static void lm32_cpu_realizefn (DeviceState *dev,Error **errp)
target-m68k/cpu.c +1 -1
@@ -58,7 +58,7 @@ static void m68k_cpu_reset(CPUState *s) env->cc_op =CC_OP_FLAGS ;/* TODO: We should set PC from the interrupt vector. */ env->pc =0 ; -tlb_flush (env,1 ); +tlb_flush (s,1 ); }/* CPU models */
target-microblaze/cpu.c +1 -1
@@ -65,7 +65,7 @@ static void mb_cpu_reset(CPUState *s)memset (env,0 ,sizeof (CPUMBState)); env->res_addr =RES_ADDR_NONE ; -tlb_flush (env,1 ); +tlb_flush (s,1 );/* Disable stack protector. */ env->shr = ~0 ;
target-microblaze/mmu.c +2 -1
@@ -219,6 +219,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)void mmu_write (CPUMBState *env,uint32_t rn,uint32_t v) { +MicroBlazeCPU *cpu =mb_env_get_cpu (env);unsigned int i;D (qemu_log ("%s rn=%d=%x old=%x\n" , __func__, rn, v, env->mmu.regs[rn]));
@@ -252,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)/* Changes to the zone protection reg flush the QEMU TLB. Fortunately, these are very uncommon. */ if (v != env->mmu.regs[rn]) { -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); } env->mmu.regs[rn] = v;break ;
target-mips/cpu.c +1 -1
@@ -84,7 +84,7 @@ static void mips_cpu_reset(CPUState *s) mcc->parent_reset (s);memset (env,0 , offsetof(CPUMIPSState , mvp)); -tlb_flush (env,1 ); +tlb_flush (s,1 );cpu_state_reset (env); }
target-mips/machine.c +2 -1
@@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)int cpu_load (QEMUFile *f,void *opaque,int version_id) {CPUMIPSState *env = opaque; +MIPSCPU *cpu =mips_env_get_cpu (env);int i;if (version_id !=3 )
@@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)load_fpu (f, &env->fpus[i]);/* XXX: ensure compatibility for halted bit ? */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 );return 0 ; }
target-mips/op_helper.c +3 -1
@@ -1787,8 +1787,10 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)/* TLB management */ static void cpu_mips_tlb_flush (CPUMIPSState *env,int flush_global) { +MIPSCPU *cpu =mips_env_get_cpu (env); +/* Flush qemu's TLB and discard all shadowed entries. */ -tlb_flush (env, flush_global); +tlb_flush (CPU (cpu), flush_global); env->tlb->tlb_in_use = env->tlb->nb_tlb; }
target-moxie/cpu.c +1 -1
@@ -45,7 +45,7 @@ static void moxie_cpu_reset(CPUState *s)memset (env,0 ,sizeof (CPUMoxieState)); env->pc =0x1000 ; -tlb_flush (env,1 ); +tlb_flush (s,1 ); }static void moxie_cpu_realizefn (DeviceState *dev,Error **errp)
target-openrisc/cpu.c +1 -1
@@ -47,7 +47,7 @@ static void openrisc_cpu_reset(CPUState *s)memset (&cpu->env,0 , offsetof(CPUOpenRISCState , irq));#endif -tlb_flush (&cpu->env,1 ); +tlb_flush (s,1 );/*tb_flush(&cpu->env); FIXME: Do we need it? */ cpu->env.pc =0x100 ;
target-openrisc/interrupt.c +1 -1
@@ -43,7 +43,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)/* For machine-state changed between user-mode and supervisor mode, we need flush TLB when we enter&exit EXCP. */ -tlb_flush (env,1 ); +tlb_flush (cs,1 ); env->esr = env->sr; env->sr &= ~SR_DME ;
target-openrisc/interrupt_helper.c +1 -1
@@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) }if (need_flush_tlb) { -tlb_flush (&cpu->env,1 ); +tlb_flush (cs,1 ); }#endif cs->interrupt_request |=CPU_INTERRUPT_EXITTB ;
target-openrisc/sys_helper.c +1 -1
@@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,case TO_SPR (0 ,17 ):/* SR */ if ((env->sr & (SR_IME |SR_DME |SR_SM )) ^ (rb & (SR_IME |SR_DME |SR_SM ))) { -tlb_flush (env,1 ); +tlb_flush (cs,1 ); } env->sr = rb; env->sr |=SR_FO ;/* FO is const equal to 1 */
target-ppc/excp_helper.c +2 -2
@@ -616,7 +616,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) }/* If we disactivated any translation, flush TLBs */ if (msr & ((1 <<MSR_IR ) | (1 <<MSR_DR ))) { -tlb_flush (env,1 ); +tlb_flush (cs,1 ); }#ifdef TARGET_PPC64
@@ -671,7 +671,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)/* XXX: The BookE changes address space when switching modes, we should probably implement that as different MMU indexes, but for the moment we do it the slow way and flush all. */ -tlb_flush (env,1 ); +tlb_flush (cs,1 ); } }
target-ppc/helper_regs.h +1 -1
@@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,if (((value >>MSR_IR ) &1 ) != msr_ir || ((value >>MSR_DR ) &1 ) != msr_dr) {/* Flush all tlb when changing translation mode */ -tlb_flush (env,1 ); +tlb_flush (cs,1 ); excp =POWERPC_EXCP_NONE ; cs->interrupt_request |=CPU_INTERRUPT_EXITTB ; }
target-ppc/misc_helper.c +3 -1
@@ -62,10 +62,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)void helper_store_403_pbr (CPUPPCState *env,uint32_t num,target_ulong value) { +PowerPCCPU *cpu =ppc_env_get_cpu (env); +if (likely (env->pb[num] != value)) { env->pb[num] = value;/* Should be optimized */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); } }
target-ppc/mmu-hash64.c +4 -2
@@ -99,6 +99,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)void helper_slbia (CPUPPCState *env) { +PowerPCCPU *cpu =ppc_env_get_cpu (env);int n, do_invalidate; do_invalidate =0 ;
@@ -116,12 +117,13 @@ void helper_slbia(CPUPPCState *env) } }if (do_invalidate) { -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); } }void helper_slbie (CPUPPCState *env,target_ulong addr) { +PowerPCCPU *cpu =ppc_env_get_cpu (env);ppc_slb_t *slb; slb =slb_lookup (env, addr);
@@ -136,7 +138,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)* and we still don't have a tlb_flush_mask(env, n, mask) * in QEMU, we just invalidate all TLBs */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); } }
target-ppc/mmu_helper.c +28 -16
184 lines not on this page · raw message
target-ppc/translate_init.c +1 -1
@@ -8435,7 +8435,7 @@ static void ppc_cpu_reset(CPUState *s)#endif /* TARGET_PPC64 */ /* Flush all TLBs */ -tlb_flush (env,1 ); +tlb_flush (s,1 ); }static void ppc_cpu_initfn (Object *obj)
target-s390x/cpu.c +2 -2
@@ -98,7 +98,7 @@ static void s390_cpu_reset(CPUState *s)#if !defined(CONFIG_USER_ONLY ) s->halted =1 ;#endif -tlb_flush (env,1 ); +tlb_flush (s,1 ); }/* S390CPUClass::initial_reset() */
@@ -153,7 +153,7 @@ static void s390_cpu_full_reset(CPUState *s)#if !defined(CONFIG_USER_ONLY ) s->halted =1 ;#endif -tlb_flush (env,1 ); +tlb_flush (s,1 ); }#if !defined(CONFIG_USER_ONLY )
target-s390x/mem_helper.c +9 -4
@@ -810,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array,#if !defined(CONFIG_USER_ONLY )void HELPER (lctlg )(CPUS390XState *env,uint32_t r1,uint64_t a2,uint32_t r3) { +S390CPU *cpu =s390_env_get_cpu (env);int i;uint64_t src = a2;
@@ -824,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }void HELPER (lctl )(CPUS390XState *env,uint32_t r1,uint64_t a2,uint32_t r3) { +S390CPU *cpu =s390_env_get_cpu (env);int i;uint64_t src = a2;
@@ -842,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } } -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }void HELPER (stctg )(CPUS390XState *env,uint32_t r1,uint64_t a2,uint32_t r3)
@@ -935,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)/* compare and swap and purge */ uint32_t HELPER (csp )(CPUS390XState *env,uint32_t r1,uint64_t r2) { +S390CPU *cpu =s390_env_get_cpu (env);uint32_t cc;uint32_t o1 = env->regs[r1];uint64_t a2 = r2 & ~3ULL ;
@@ -944,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)cpu_stl_data (env, a2, env->regs[(r1 +1 ) &15 ]);if (r2 &0x3 ) {/* flush TLB / ALB */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); } cc =0 ; }else {
@@ -1040,7 +1043,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)/* flush local tlb */ void HELPER (ptlb )(CPUS390XState *env) { -tlb_flush (env,1 ); +S390CPU *cpu =s390_env_get_cpu (env); + +tlb_flush (CPU (cpu),1 ); }/* store using real address */
target-sh4/cpu.c +1 -1
@@ -54,7 +54,7 @@ static void superh_cpu_reset(CPUState *s) scc->parent_reset (s);memset (env,0 , offsetof(CPUSH4State , id)); -tlb_flush (env,1 ); +tlb_flush (s,1 ); env->pc =0xA0000000 ;#if defined(CONFIG_USER_ONLY )
target-sh4/helper.c +1 -1
@@ -585,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->v =0 ; } -tlb_flush (s,1 ); +tlb_flush (CPU (sh_env_get_cpu (s)),1 ); } uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
target-sparc/cpu.c +1 -1
@@ -34,7 +34,7 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset (s);memset (env,0 , offsetof(CPUSPARCState , version)); -tlb_flush (env,1 ); +tlb_flush (s,1 ); env->cwp =0 ;#ifndef TARGET_SPARC64 env->wim =1 ;
target-sparc/ldst_helper.c +10 -8
@@ -871,7 +871,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,case 2 :/* flush region (16M) */ case 3 :/* flush context (4G) */ case 4 :/* flush entire */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 );break ;default :break ;
@@ -896,7 +896,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,disabled mode are invalid in normal mode */ if ((oldreg & (MMU_E |MMU_NF | env->def->mmu_bm)) != (env->mmuregs[reg] & (MMU_E |MMU_NF | env->def->mmu_bm))) { -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }break ;case 1 :/* Context Table Pointer Register */
@@ -907,7 +907,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,if (oldreg != env->mmuregs[reg]) {/* we flush when the MMU context changes because QEMU has no MMU context support */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }break ;case 3 :/* Synchronous Fault Status Register with Clear */
@@ -1663,7 +1663,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,void helper_st_asi (CPUSPARCState *env,target_ulong addr,target_ulong val,int asi,int size) { -CPUState *cs =CPU (sparc_env_get_cpu (env)); +SPARCCPU *cpu =sparc_env_get_cpu (env); +CPUState *cs =CPU (cpu); +#ifdef DEBUG_ASI dump_asi ("write" , addr, asi, size, val);#endif
@@ -1872,7 +1874,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,#ifdef DEBUG_MMU dump_mmu (stdout, fprintf, env);#endif -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); }return ; }
@@ -1961,13 +1963,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.mmu_primary_context = val;/* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 );break ;case 2 :/* Secondary context */ env->dmmu.mmu_secondary_context = val;/* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 );break ;case 5 :/* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
@@ -2397,7 +2399,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,/* flush neverland mappings created during no-fault mode, so the sequential MMU faults report proper fault types */ if (env->mmuregs[0 ] &MMU_NF ) { -tlb_flush (env,1 ); +tlb_flush (cs,1 ); } }#else
target-sparc/machine.c +2 -1
@@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque)int cpu_load (QEMUFile *f,void *opaque,int version_id) {CPUSPARCState *env = opaque; +SPARCCPU *cpu =sparc_env_get_cpu (env);int i;uint32_t tmp;
@@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)qemu_get_be64s (f, &env->ssr);cpu_get_timer (f, env->hstick);#endif -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 );return 0 ; }
target-unicore32/cpu.c +1 -1
@@ -121,7 +121,7 @@ static void uc32_cpu_initfn(Object *obj) env->regs[31 ] =0x03000000 ;#endif -tlb_flush (env,1 ); +tlb_flush (cs,1 );if (tcg_enabled () && !inited) { inited = true;
target-unicore32/helper.c +3 -1
@@ -50,6 +50,8 @@ uint32_t HELPER(clz)(uint32_t x)void helper_cp0_set (CPUUniCore32State *env,uint32_t val,uint32_t creg,uint32_t cop) { +UniCore32CPU *cpu =uc32_env_get_cpu (env); +/* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D
@@ -118,7 +120,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,case 6 :if ((cop <=6 ) && (cop >=2 )) {/* invalid all tlb */ -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 );return ; }break ;
target-xtensa/op_helper.c +3 -1
@@ -487,10 +487,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)void HELPER (wsr_rasid )(CPUXtensaState *env,uint32_t v) { +XtensaCPU *cpu =xtensa_env_get_cpu (env); + v = (v &0xffffff00 ) |0x1 ;if (v != env->sregs[RASID ]) { env->sregs[RASID ] = v; -tlb_flush (env,1 ); +tlb_flush (CPU (cpu),1 ); } }
Signature · 1 line
1.8.4.5
PATCH 1/1 : exec: fix cpu rework fallout (was cputlb: Change tlb_flush() argument to CPUState)
I need the following to not crash on migration post load:
tlb_flush wants an CPUState. This was unnoticed by gcc because env_ptr is a void pointer.
Signed-off-by Christian Borntraeger <[email protected]>
--- exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
exec.c +1 -1
@@ -420,7 +420,7 @@ static int cpu_common_post_load(void *opaque, int version_id)/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the version_id is increased. */ cpu->interrupt_request &= ~0x01 ; -tlb_flush (cpu->env_ptr,1 ); +tlb_flush (cpu,1 );return 0 ; }
Andreas Färber
AppliedRe: [Qemu-devel] [PATCH]: exec: fix cpu rework fallout (was cputlb: Change tlb_flush() argument to CPUState)
Am 17.03.2014 17:13, schrieb Christian Borntraeger:
Quoted 6 lines
I need the following to not crash on migration post load:
tlb_flushwants an CPUState. This was unnoticed by gcc becauseenv_ptris a void pointer.Signed-off-by Christian Borntraeger <[email protected]>
Thanks, applied to qom-cpu with reworked commit message:
https://github.com/afaerber/qemu-cpu/commits/qom-cpu
Andreas
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PULL for-2.0-rc0 57/58] cputlb: Change tlb_set_page() argument to CPUState
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- cputlb.c | 4 ++-- include/exec/exec-all.h | 2 +- target-alpha/helper.c | 2 +- target-arm/helper.c | 2 +- target-cris/helper.c | 2 +- target-i386/helper.c | 2 +- target-lm32/helper.c | 6 +++--- target-m68k/helper.c | 3 +-- target-microblaze/helper.c | 4 ++-- target-mips/helper.c | 2 +- target-moxie/helper.c | 2 +- target-openrisc/mmu.c | 2 +- target-ppc/mmu-hash32.c | 8 ++++---- target-ppc/mmu-hash64.c | 4 ++-- target-ppc/mmu_helper.c | 2 +- target-s390x/helper.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/mmu_helper.c | 6 +++--- target-unicore32/softmmu.c | 2 +- target-xtensa/op_helper.c | 8 ++++---- 20 files changed, 33 insertions(+), 34 deletions(-)
cputlb.c +2 -2
@@ -221,10 +221,11 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,/* Add a new TLB entry. At most one entry for a given virtual address is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the supplied size is only used by tlb_flush_page. */ -void tlb_set_page (CPUArchState *env,target_ulong vaddr, +void tlb_set_page (CPUState *cpu,target_ulong vaddr,hwaddr paddr,int prot,int mmu_idx,target_ulong size) { +CPUArchState *env = cpu->env_ptr;MemoryRegionSection *section;unsigned int index;target_ulong address;
@@ -232,7 +233,6 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,uintptr_t addend;CPUTLBEntry *te;hwaddr iotlb, xlat, sz; -CPUState *cpu =ENV_GET_CPU (env);assert (size >=TARGET_PAGE_SIZE );if (size !=TARGET_PAGE_SIZE ) {
include/exec/exec-all.h +1 -1
@@ -100,7 +100,7 @@ void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);/* cputlb.c */ void tlb_flush_page (CPUState *cpu,target_ulong addr);void tlb_flush (CPUState *cpu,int flush_global); -void tlb_set_page (CPUArchState *env,target_ulong vaddr, +void tlb_set_page (CPUState *cpu,target_ulong vaddr,hwaddr paddr,int prot,int mmu_idx,target_ulong size);void tb_invalidate_phys_addr (AddressSpace *as,hwaddr addr);
target-alpha/helper.c +1 -1
@@ -345,7 +345,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,return 1 ; } -tlb_set_page (env, addr &TARGET_PAGE_MASK , phys &TARGET_PAGE_MASK , +tlb_set_page (cs, addr &TARGET_PAGE_MASK , phys &TARGET_PAGE_MASK , prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ; }
target-arm/helper.c +1 -1
@@ -3676,7 +3676,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,/* Map a single [sub]page. */ phys_addr &= ~(hwaddr )0x3ff ; address &= ~(uint32_t )0x3ff ; -tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); +tlb_set_page (cs, address, phys_addr, prot, mmu_idx, page_size);return 0 ; }
target-cris/helper.c +1 -1
@@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,*/ phy = res.phy & ~0x80000000 ; prot = res.prot; -tlb_set_page (env, address &TARGET_PAGE_MASK , phy, +tlb_set_page (cs, address &TARGET_PAGE_MASK , phy, prot, mmu_idx,TARGET_PAGE_SIZE ); r =0 ; }
target-i386/helper.c +1 -1
@@ -877,7 +877,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, paddr = (pte &TARGET_PAGE_MASK ) + page_offset; vaddr = virt_addr + page_offset; -tlb_set_page (env, vaddr, paddr, prot, mmu_idx, page_size); +tlb_set_page (cs, vaddr, paddr, prot, mmu_idx, page_size);return 0 ; do_fault_protect: error_code =PG_ERROR_P_MASK ;
target-lm32/helper.c +3 -3
@@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, address &=TARGET_PAGE_MASK ; prot =PAGE_BITS ;if (env->flags &LM32_FLAG_IGNORE_MSB ) { -tlb_set_page (env, address, address &0x7fffffff , prot, mmu_idx, -TARGET_PAGE_SIZE ); +tlb_set_page (cs, address, address &0x7fffffff , prot, mmu_idx, +TARGET_PAGE_SIZE ); }else { -tlb_set_page (env, address, address, prot, mmu_idx,TARGET_PAGE_SIZE ); +tlb_set_page (cs, address, address, prot, mmu_idx,TARGET_PAGE_SIZE ); }return 0 ;
target-m68k/helper.c +1 -2
@@ -303,12 +303,11 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)int m68k_cpu_handle_mmu_fault (CPUState *cs,vaddr address,int rw,int mmu_idx) { -M68kCPU *cpu =M68K_CPU (cs);int prot; address &=TARGET_PAGE_MASK ; prot =PAGE_READ |PAGE_WRITE |PAGE_EXEC ; -tlb_set_page (&cpu->env, address, address, prot, mmu_idx,TARGET_PAGE_SIZE ); +tlb_set_page (cs, address, address, prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ; }
target-microblaze/helper.c +2 -2
@@ -77,7 +77,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,DMMU (qemu_log ("MMU map mmu=%d v=%x p=%x prot=%x\n" , mmu_idx, vaddr, paddr, lu.prot)); -tlb_set_page (env, vaddr, paddr, lu.prot, mmu_idx,TARGET_PAGE_SIZE ); +tlb_set_page (cs, vaddr, paddr, lu.prot, mmu_idx,TARGET_PAGE_SIZE ); r =0 ; }else { env->sregs[SR_EAR ] = address;
@@ -108,7 +108,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,/* MMU disabled or not available. */ address &=TARGET_PAGE_MASK ; prot =PAGE_BITS ; -tlb_set_page (env, address, address, prot, mmu_idx,TARGET_PAGE_SIZE ); +tlb_set_page (cs, address, address, prot, mmu_idx,TARGET_PAGE_SIZE ); r =0 ; }return r;
target-mips/helper.c +1 -1
@@ -300,7 +300,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw," prot %d\n" , __func__, address, ret, physical, prot);if (ret ==TLBRET_MATCH ) { -tlb_set_page (env, address &TARGET_PAGE_MASK , +tlb_set_page (cs, address &TARGET_PAGE_MASK , physical &TARGET_PAGE_MASK , prot |PAGE_EXEC , mmu_idx,TARGET_PAGE_SIZE ); ret =0 ;
target-moxie/helper.c +1 -1
@@ -148,7 +148,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, phy = res.phy; r =0 ; } -tlb_set_page (env, address, phy, prot, mmu_idx,TARGET_PAGE_SIZE ); +tlb_set_page (cs, address, phy, prot, mmu_idx,TARGET_PAGE_SIZE );return r; }
target-openrisc/mmu.c +1 -1
@@ -187,7 +187,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, address, rw);if (ret ==TLBRET_MATCH ) { -tlb_set_page (&cpu->env, address &TARGET_PAGE_MASK , +tlb_set_page (cs, address &TARGET_PAGE_MASK , physical &TARGET_PAGE_MASK , prot, mmu_idx,TARGET_PAGE_SIZE ); ret =0 ;
target-ppc/mmu-hash32.c +4 -4
@@ -400,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,if (((rwx ==2 ) && (msr_ir ==0 )) || ((rwx !=2 ) && (msr_dr ==0 ))) {/* Translation is off */ raddr = eaddr; -tlb_set_page (env, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , +tlb_set_page (cs, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK ,PAGE_READ |PAGE_WRITE |PAGE_EXEC , mmu_idx,TARGET_PAGE_SIZE );return 0 ;
@@ -427,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,return 1 ; } -tlb_set_page (env, eaddr &TARGET_PAGE_MASK , +tlb_set_page (cs, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ;
@@ -441,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,if (sr &SR32_T ) {if (ppc_hash32_direct_store (env, sr, eaddr, rwx, &raddr, &prot) ==0 ) { -tlb_set_page (env, eaddr &TARGET_PAGE_MASK , +tlb_set_page (cs, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ;
@@ -522,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, raddr =ppc_hash32_pte_raddr (sr, pte, eaddr); -tlb_set_page (env, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , +tlb_set_page (cs, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ;
target-ppc/mmu-hash64.c +2 -2
@@ -476,7 +476,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,/* Translation is off */ /* In real mode the top 4 effective address bits are ignored */ raddr = eaddr &0x0FFFFFFFFFFFFFFFULL ; -tlb_set_page (env, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , +tlb_set_page (cs, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK ,PAGE_READ |PAGE_WRITE |PAGE_EXEC , mmu_idx,TARGET_PAGE_SIZE );return 0 ;
@@ -578,7 +578,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, raddr =ppc_hash64_pte_raddr (slb, pte, eaddr); -tlb_set_page (env, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , +tlb_set_page (cs, eaddr &TARGET_PAGE_MASK , raddr &TARGET_PAGE_MASK , prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ;
target-ppc/mmu_helper.c +1 -1
@@ -1514,7 +1514,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, } ret =get_physical_address (env, &ctx, address, rw, access_type);if (ret ==0 ) { -tlb_set_page (env, address &TARGET_PAGE_MASK , +tlb_set_page (cs, address &TARGET_PAGE_MASK , ctx.raddr &TARGET_PAGE_MASK , ctx.prot, mmu_idx,TARGET_PAGE_SIZE ); ret =0 ;
target-s390x/helper.c +1 -1
@@ -417,7 +417,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,DPRINTF ("%s: set tlb %" PRIx64" -> %" PRIx64" (%x)\n" , __func__, (uint64_t )vaddr, (uint64_t )raddr, prot); -tlb_set_page (env, orig_vaddr, raddr, prot, +tlb_set_page (cs, orig_vaddr, raddr, prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ;
target-sh4/helper.c +1 -1
@@ -512,7 +512,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, address &=TARGET_PAGE_MASK ; physical &=TARGET_PAGE_MASK ; -tlb_set_page (env, address, physical, prot, mmu_idx,TARGET_PAGE_SIZE ); +tlb_set_page (cs, address, physical, prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ; }
target-sparc/mmu_helper.c +3 -3
@@ -217,7 +217,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,printf ("Translate at %" VADDR_PRIx" -> " TARGET_FMT_plx", vaddr " TARGET_FMT_lx"\n" , address, paddr, vaddr);#endif -tlb_set_page (env, vaddr, paddr, prot, mmu_idx, page_size); +tlb_set_page (cs, vaddr, paddr, prot, mmu_idx, page_size);return 0 ; }
@@ -233,7 +233,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ prot =PAGE_READ |PAGE_WRITE |PAGE_EXEC ; -tlb_set_page (env, vaddr, paddr, prot, mmu_idx,TARGET_PAGE_SIZE ); +tlb_set_page (cs, vaddr, paddr, prot, mmu_idx,TARGET_PAGE_SIZE );return 0 ; }else {if (rw &2 ) {
@@ -729,7 +729,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); -tlb_set_page (env, vaddr, paddr, prot, mmu_idx, page_size); +tlb_set_page (cs, vaddr, paddr, prot, mmu_idx, page_size);return 0 ; }/* XXX */
target-unicore32/softmmu.c +1 -1
@@ -253,7 +253,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,/* Map a single page. */ phys_addr &=TARGET_PAGE_MASK ; address &=TARGET_PAGE_MASK ; -tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size); +tlb_set_page (cs, address, phys_addr, prot, mmu_idx, page_size);return 0 ; }
target-xtensa/op_helper.c +4 -4
@@ -77,10 +77,10 @@ void tlb_fill(CPUState *cs, vaddr, is_write, mmu_idx, paddr, ret);if (ret ==0 ) { -tlb_set_page (env, - vaddr &TARGET_PAGE_MASK , - paddr &TARGET_PAGE_MASK , - access, mmu_idx, page_size); +tlb_set_page (cs, + vaddr &TARGET_PAGE_MASK , + paddr &TARGET_PAGE_MASK , + access, mmu_idx, page_size); }else {cpu_restore_state (cs, retaddr);HELPER (exception_cause_vaddr)(env, env->pc, ret, vaddr);
Signature · 1 line
1.8.4.5
[Qemu-devel] [PULL for-2.0-rc0 58/58] user-exec: Change exception_action() argument to CPUState
In reply to Andreas FärberSigned-off-by Andreas Färber <[email protected]>
--- user-exec.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
user-exec.c +5 -6
@@ -38,11 +38,12 @@//#define DEBUG_SIGNAL -static void exception_action (CPUArchState *env1) +static void exception_action (CPUState *cpu) { -CPUState *cpu =ENV_GET_CPU (env1); -#if defined(TARGET_I386 ) +X86CPU *x86_cpu =X86_CPU (cpu); +CPUX86State *env1 = &x86_cpu->env; +raise_exception_err (env1, cpu->exception_index, env1->error_code);#else cpu_loop_exit (cpu);
@@ -86,7 +87,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, {CPUState *cpu;CPUClass *cc; -CPUArchState *env;int ret;#if defined(DEBUG_SIGNAL )
@@ -105,7 +105,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, cpu = current_cpu; cc =CPU_GET_CLASS (cpu); - env = cpu->env_ptr;/* see if it is an MMU fault */ g_assert (cc->handle_mmu_fault); ret = cc->handle_mmu_fault (cpu, address, is_write,MMU_USER_IDX );
@@ -121,7 +120,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,/* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ sigprocmask (SIG_SETMASK , old_set,NULL ); -exception_action (env); +exception_action (cpu);/* never comes here */ return 1 ;
Signature · 1 line
1.8.4.5
Quoted 7 lines · Andreas Färber
Hello Peter,
This is my current QOM CPU patch queue. Please pull.
Since this touches on bsd-user code, request to apply the build fix first.
NB: I was only able to test x86/ppc/arm KVM this time; s390x KVM was re-reviewed only.
A basic start of a guest on s390 was successful. No further testing done, though.
Quoted 22 lines · Andreas Färber
Hello Peter,
This is my current QOM CPU patch queue. Please pull.
Since this touches on bsd-user code, request to apply the build fix first.
NB: I was only able to test x86/ppc/arm KVM this time; s390x KVM was re-reviewed only.
Regards,
AndreasCc Peter Maydell <[email protected]>Cc Anthony Liguori <[email protected]>Cc Eduardo Habkost <[email protected]>Cc Igor Mammedov <[email protected]>Cc Christian Borntraeger <[email protected]>The following changes since commit
be86c53c058d75fc3938b1b54f363259f282b3d5:Merge remote-tracking branch 'remotes/afaerber/tags/ppc-for-2.0' into staging (2014-03-13 13:19:46 +0000)
Quoted 8 lines
are available in the git repository at:
git://github.com/afaerber/qemu-cpu.gittags/qom-cpu-for-2.0for you to fetch changes up to
98f11363e7add1e750f76e3d81750348f0470c29:user-exec: Change
exception_action()argument to CPUState (2014-03-13 15:35:04 +0100)
Fails to compile on systems without CONFIG_INT128 (eg 32 bit host):
/root/qemu/target-s390x/int_helper.c: In function ‘helper_divu64’:/root/qemu/target-s390x/int_helper.c:111:9: error: passing argument 1 of ‘cpu_abort’ from incompatible pointer type [-Werror]
In file included from /root/qemu/include/exec/cpu-all.h:26:0,
from /root/qemu/target-s390x/cpu.h:41,
from /root/qemu/target-s390x/int_helper.c:21:/root/qemu/include/qom/cpu.h:620:37: note: expected ‘struct CPUState *’ but argument is of type ‘struct CPUS390XState *’
cc1: all warnings being treated as errors
thanks
-- PMM
Am 13.03.2014 18:10, schrieb Peter Maydell:
Quoted 38 lines · Andreas Färber
Quoted 22 lines
Hello Peter,
This is my current QOM CPU patch queue. Please pull.
Since this touches on bsd-user code, request to apply the build fix first.
NB: I was only able to test x86/ppc/arm KVM this time; s390x KVM was re-reviewed only.
Regards,
AndreasCc Peter Maydell <[email protected]>Cc Anthony Liguori <[email protected]>Cc Eduardo Habkost <[email protected]>Cc Igor Mammedov <[email protected]>Cc Christian Borntraeger <[email protected]>The following changes since commit
be86c53c058d75fc3938b1b54f363259f282b3d5:Merge remote-tracking branch 'remotes/afaerber/tags/ppc-for-2.0' into staging (2014-03-13 13:19:46 +0000)
Quoted 8 lines
are available in the git repository at:
git://github.com/afaerber/qemu-cpu.gittags/qom-cpu-for-2.0for you to fetch changes up to
98f11363e7add1e750f76e3d81750348f0470c29:user-exec: Change
exception_action()argument to CPUState (2014-03-13 15:35:04 +0100)Fails to compile on systems without
CONFIG_INT128(eg 32 bit host):
/root/qemu/target-s390x/int_helper.c: In function ‘helper_divu64’:/root/qemu/target-s390x/int_helper.c:111:9: error: passing argument 1 of ‘cpu_abort’ from incompatible pointer type [-Werror]
In file included from/root/qemu/include/exec/cpu-all.h:26:0,
Quoted 5 lines
from /root/qemu/target-s390x/cpu.h:41, from /root/qemu/target-s390x/int_helper.c:21:
/root/qemu/include/qom/cpu.h:620:37: note: expected ‘struct CPUState *’ but argument is of type ‘struct CPUS390XState *’
cc1: all warnings being treated as errors
Thanks for catching that, the following seems to fix:
target-s390x/int_helper.c +0 -0
@@ -106,9 +106,10 @@ uint64_t HELPER(divu64)(CPUS390XState *env,
uint64_t ah, uint64_t al,
runtime_exception(env, PGM_FIXPT_DIVIDE, GETPC());
}
#else
+ S390CPU *cpu = s390_env_get_cpu(env);
/* 32-bit hosts would need special wrapper functionality - justabort if
we encounter such a case; it's very unlikely anyways. */
- cpu_abort(env, "128 -> 64/64 division not implemented\n");
+ cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n");
#endif
}
return ret;git-grep showed no further missed occurrences of cpu_abort().
Will submit v2 once my testing completes.
Regards,
Andreas
Signature · 2 lines
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