ARM: dts: msm8974: Move arch-timer out of soc node
Subsystems (2)
PATCH 1/1 ARM: dts: msm8974: Move arch-timer out of soc node
The architected timer is not a register addressable piece of hardware. Instead it's accessed through cp15 accessors. Move it to the root of the devicetree to reflect this.
--- arch/arm/boot/dts/qcom-msm8974.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
arch/arm/boot/dts/qcom-msm8974.dtsi +9 -9
@@ -52,6 +52,15 @@ }; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <19200000>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>;
@@ -66,15 +75,6 @@ <0xf9002000 0x1000>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - timer at f9020000 { #address-cells = <1>; #size-cells = <1>;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Hi Stephen,
Quoted 3 lines · Stephen Boyd
The architected timer is not a register addressable piece of hardware. Instead it's accessed through cp15 accessors. Move it to the root of the devicetree to reflect this.
I find this confusing, perhaps due to overloading of the word "register". Aren't CP15's a class of coprocessor _registers_? Could it perhaps be clearer to talk about memory-mapped versus CP15-mapped timers?
Is "soc" documented somewhere or is it just a name for a container? Assuming the latter, it's not obvious to me why being a child of a system on chip node would imply having memory mapped registers.
Thanks,
Christopher
Signature · 3 lines
Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation.
Quoted 7 lines · Christopher Covington
Hi Stephen,
Quoted 3 lines · Stephen Boyd
The architected timer is not a register addressable piece of hardware. Instead it's accessed through cp15 accessors. Move it to the root of the devicetree to reflect this.
Quoted 7 lines
I find this confusing, perhaps due to overloading of the word "register". Aren't CP15's a class of coprocessor _registers_? Could it perhaps be clearer to talk about memory-mapped versus CP15-mapped timers?
Is "soc" documented somewhere or is it just a name for a container? Assuming the latter, it's not obvious to me why being a child of a system on chip node would imply having memory mapped registers.
?soc? is a container, since its compatible = "simple-bus?, this implies memory mapped register access for nodes inside of it.
- k
Signature · 2 lines
Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Hi Kumar,
Quoted 14 lines · Kumar Gala
Quoted 11 lines · Christopher Covington
Hi Stephen,
Quoted 3 lines · Stephen Boyd
The architected timer is not a register addressable piece of hardware. Instead it's accessed through cp15 accessors. Move it to the root of the devicetree to reflect this.
I find this confusing, perhaps due to overloading of the word "register". Aren't CP15's a class of coprocessor _registers_? Could it perhaps be clearer to talk about memory-mapped versus CP15-mapped timers?
Quoted 6 lines
Quoted 3 lines
Is "soc" documented somewhere or is it just a name for a container? Assuming the latter, it's not obvious to me why being a child of a system on chip node would imply having memory mapped registers.
?soc? is a container, since its compatible = "simple-bus?, this implies memory mapped register access for nodes inside of it.
That makes sense. Thanks for explaining it.
Christopher
Signature · 3 lines
Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation.