Skip to contentSkip to conversation

arm: exynos: pinmux: add sdmmc4 gpio configratuion

PATCH New Beomho Seo 1 participant 1 message Mar 20, 2014

Subsystems (2)
Arm (32-bit) Arm Samsung Exynos
lore
Share & tools
lore

Beomho Seo

author
#0 lore raw

PATCH v3 2/4 arm: exynos: pinmux: add sdmmc4 gpio configratuion

For use dwmmc controller at exynos4, add SDMMC4 gpio configuration. In case SDMMC2, do not use 8 bit mode at exynos4.

Signed-off-by Beomho Seo <[email protected]>
Signed-off-by Jaehoon Chung <[email protected]>
Tested-by Piotr Wilczek <[email protected]>
Cc Lukasz Majewski <[email protected]>
Cc Piotr Wilczek <[email protected]>
Cc Minkyu Kang <[email protected]>

---
Changes for v3:
- Set bank_ext of SDMMC2 for prevent compile warning.

Changes for v2:
- Fixed value initialinse.
- Comment add in function.

 arch/arm/cpu/armv7/exynos/pinmux.c |   18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +15 -3
index 9edb475..55c1c95 100644
@@ -632,16 +632,27 @@ static int exynos4_mmc_config(int peripheral, int flags)
 	struct exynos4_gpio_part2 *gpio2 =
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 	struct s5p_gpio_bank *bank, *bank_ext;
+	unsigned int  func, func_ext;
 	int i;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
 		bank = &gpio2->k0;
 		bank_ext = &gpio2->k1;
+		func = GPIO_FUNC(0x2);
+		func_ext = GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC2:
 		bank = &gpio2->k2;
 		bank_ext = &gpio2->k3;
+		func = GPIO_FUNC(0x2);
+		func_ext = GPIO_FUNC(0x3);
+		break;
+	case PERIPH_ID_SDMMC4:
+		bank = &gpio2->k0;
+		bank_ext = &gpio2->k1;
+		func = GPIO_FUNC(0x3);
+		func_ext = GPIO_FUNC(0x4);
 		break;
 	default:
 		return -1;

@@ -649,13 +660,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
 	for (i = 0; i < 7; i++) {
 		if (i == 2)
 			continue;
-		s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(bank, i,  func);
 		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
 		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
 	}
+	/* SDMMC2 do not use 8bit mode@exynos4 */
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = 3; i < 7; i++) {
-			s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
+			s5p_gpio_cfg_pin(bank_ext, i,  func_ext);
 			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
 			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
 		}

@@ -722,10 +734,10 @@ static int exynos4_pinmux_config(int peripheral, int flags)
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC4:
 		return exynos4_mmc_config(peripheral, flags);
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC3:
-	case PERIPH_ID_SDMMC4:
 		debug("SDMMC device %d not implemented\n", peripheral);
 		return -1;
 	default:
Signature · 1 line
1.7.9.5