clk: exynos: add support for exynos5260 SoC

PATCH Superseded Rahul Sharma 3 participants 6 messages Mar 23, 2014 – Apr 28, 2014

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Device tree bindings Common clk Arm Samsung Exynos Samsung SoC clock drivers

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Rahul Sharma

author

2014-03-23 20:45 UTC #0 lore raw

v6 cover clk: exynos: add support for exynos5260 SoC

From: Rahul Sharma <[email protected]>

Add clock support for exynos5260 SoC.

This series is based on Tomasz Figa's samsung-next branch.

V6:
1) Listed external Clocks in documentation file.
2) Listed Input Clocks for each clock controller in exynos5260-clock.txt.
3) Added Clock and Clock-names properties.
4) Assigned IDs to all clocks in the clock file.
5) Moved all PHY clocks as fixed rate to the driver file.
6) Reorder clocks to maintain acscending order on the basis of clock register offset and bit numer.

V5:
1) Include S3c2412 and S3c2443 in clock provider patch.
2) Added SCLK_TOP_FIMD with CLK_IGNORE_UNUSED due to Suspend failure.
3) Moved exynos5260-clk.h to include/dt-bindings/clock.
4) Fix exynos5260_clk_sleep_init protoype for PM disabled.W
5) Moved fixed clock registeration to DT.
6) Removed CLK_IGNORE_UNUSED flags from UART clocks. Earlier facing issues because of RFS probing all TTYs.

V4:
1) Rework clock file as per Tomasz review comments at

        http://www.spinics.net/lists/arm-kernel/msg310116.html.

V3:
1) Removed "samsung,exynos5260-clock" property from clock files.
2) Replaced "__SPIN_LOCK_UNLOCKED(lock)" with spin_lock_init.
3) Removed '(' and ')' around numeric constants in macros.

V2:
1) Move suspend resume handling to Exynos5410 Clock file.
2) Removed Unused Macros and Condition checks for Exynos5260.
3) Add spin lock to clock provider context.
4) Add clock provider context for Exynos5410.
5) Uniform implementation for callbacks for PLL2550xx.
6) Split Exynos5260 clock file patch to bring it under 100 Kb limit.
7) Replace aclk/pclk/hclk gates with combined gates.
8) Remove CLK_IGNORE_UNUSED flag for gate clocks.

Rahul Sharma (2):
clk/exynos5260: add macros and documentation for exynos5260 clk/exynos5260: add clock file for exynos5260

 .../devicetree/bindings/clock/exynos5260-clock.txt |  190 ++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos5260.c               | 1980 ++++++++++++++++++++
 drivers/clk/samsung/clk-exynos5260.h               |  459 +++++
 include/dt-bindings/clock/exynos5260-clk.h         |  469 +++++
 5 files changed, 3099 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
 create mode 100644 drivers/clk/samsung/clk-exynos5260.c
 create mode 100644 drivers/clk/samsung/clk-exynos5260.h
 create mode 100644 include/dt-bindings/clock/exynos5260-clk.h

Signature · 1 line

1.7.9.5

Rahul Sharma

author

2014-03-23 20:45 UTC #1 lore raw

PATCH v6 1/2 clk/exynos5260: add macros and documentation for exynos5260

Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.

Signed-off-by Rahul Sharma <[email protected]>

---
 .../devicetree/bindings/clock/exynos5260-clock.txt |  190 ++++++++
 include/dt-bindings/clock/exynos5260-clk.h         |  469 ++++++++++++++++++++
 2 files changed, 659 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
 create mode 100644 include/dt-bindings/clock/exynos5260-clk.h

Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +190 -0

new file mode 100644
index 0000000..5496b2f
@@ -0,0 +1,190 @@
+* Samsung Exynos5260 Clock Controller
+
+Exynos5260 has 13 clock controllers which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5260-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - "fin_pll" - PLL input clock from XXTI
+ - "xrtcxti" - input clock from XRTCXTI
+ - "ioclk_pcm_extclk" - pcm external operation clock
+ - "ioclk_spdif_extclk" - spdif external operation clock
+ - "ioclk_i2s_cdclk" - i2s0 codec clock
+
+Phy clocks:
+
+There are several clocks which are generated by specific PHYs.
+These clocks are fed into the clock controller and then routed to
+the hardware blocks. These clocks are defined as fixed clocks in the
+driver with following names:
+
+ - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
+ - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
+ - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
+ - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
+ - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
+ - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
+ - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
+ - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
+ - "phyclk_dptx_phy_clk_div2"
+ - "phyclk_mipi_dphy_4l_m_rxclkesc0"
+ - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
+ - "phyclk_usbhost20_phy_freeclk"
+ - "phyclk_usbhost20_phy_clk48mohci"
+ - "phyclk_usbdrd30_udrd30_pipe_pclk"
+ - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
+
+Required Properties for Clock Controller:
+
+ - compatible: should be one of the following.
+	1) "samsung,exynos5260-clock-top"
+	2) "samsung,exynos5260-clock-peri"
+	3) "samsung,exynos5260-clock-egl"
+	4) "samsung,exynos5260-clock-kfc"
+	5) "samsung,exynos5260-clock-g2d"
+	6) "samsung,exynos5260-clock-mif"
+	7) "samsung,exynos5260-clock-mfc"
+	8) "samsung,exynos5260-clock-g3d"
+	9) "samsung,exynos5260-clock-fsys"
+	10) "samsung,exynos5260-clock-aud"
+	11) "samsung,exynos5260-clock-isp"
+	12) "samsung,exynos5260-clock-gscl"
+	13) "samsung,exynos5260-clock-disp"
+
+ - reg: physical base address of the controller and the length of
+	memory mapped region.
+
+ - #clock-cells: should be 1.
+
+ - clocks: list of clock identifiers which are fed as the input to
+	the given clock controller. Please refer the next section to find
+	the input clocks for a given controller.
+
+ - clock-names: list of names of clocks which are fed as the input
+	to the given clock controller.
+
+Input clocks for top clock controller:
+	- fin_pll
+	- dout_mem_pll
+	- dout_bus_pll
+	- dout_media_pll
+
+Input clocks for peri clock controller:
+	- fin_pll
+	- ioclk_pcm_extclk
+	- ioclk_i2s_cdclk
+	- ioclk_spdif_extclk
+	- phyclk_hdmi_phy_ref_cko
+	- dout_aclk_peri_66
+	- dout_sclk_peri_uart0
+	- dout_sclk_peri_uart1
+	- dout_sclk_peri_uart2
+	- dout_sclk_peri_spi0_b
+	- dout_sclk_peri_spi1_b
+	- dout_sclk_peri_spi2_b
+	- dout_aclk_peri_aud
+	- dout_sclk_peri_spi0_b
+
+Input clocks for egl clock controller:
+	- fin_pll
+	- dout_bus_pll
+
+Input clocks for kfc clock controller:
+	- fin_pll
+	- dout_media_pll
+
+Input clocks for g2d clock controller:
+	- fin_pll
+	- dout_aclk_g2d_333
+
+Input clocks for mif clock controller:
+	- fin_pll
+
+Input clocks for mfc clock controller:
+	- fin_pll
+	- dout_aclk_mfc_333
+
+Input clocks for g3d clock controller:
+	- fin_pll
+
+Input clocks for fsys clock controller:
+	- fin_pll
+	- phyclk_usbhost20_phy_phyclock
+	- phyclk_usbhost20_phy_freeclk
+	- phyclk_usbhost20_phy_clk48mohci
+	- phyclk_usbdrd30_udrd30_pipe_pclk
+	- phyclk_usbdrd30_udrd30_phyclock
+	- dout_aclk_fsys_200
+
+Input clocks for aud clock controller:
+	- fin_pll
+	- fout_aud_pll
+	- ioclk_i2s_cdclk
+	- ioclk_pcm_extclk
+
+Input clocks for isp clock controller:
+	- fin_pll
+	- dout_aclk_isp1_266
+	- dout_aclk_isp1_400
+	- mout_aclk_isp1_266
+
+Input clocks for gscl clock controller:
+	- fin_pll
+	- dout_aclk_gscl_400
+	- dout_aclk_gscl_333
+
+Input clocks for disp clock controller:
+	- fin_pll
+	- phyclk_dptx_phy_ch3_txd_clk
+	- phyclk_dptx_phy_ch2_txd_clk
+	- phyclk_dptx_phy_ch1_txd_clk
+	- phyclk_dptx_phy_ch0_txd_clk
+	- phyclk_hdmi_phy_tmds_clko
+	- phyclk_hdmi_phy_ref_clko
+	- phyclk_hdmi_phy_pixel_clko
+	- phyclk_hdmi_link_o_tmds_clkhi
+	- phyclk_mipi_dphy_4l_m_txbyte_clkhs
+	- phyclk_dptx_phy_o_ref_clk_24m
+	- phyclk_dptx_phy_clk_div2
+	- phyclk_mipi_dphy_4l_m_rxclkesc0
+	- phyclk_hdmi_phy_ref_cko
+	- ioclk_spdif_extclk
+	- dout_aclk_peri_aud
+	- dout_aclk_disp_222
+	- dout_sclk_disp_pixel
+	- dout_aclk_disp_333
+
+Example 1: An example of a clock controller node is listed below.
+
+	clock_mfc: clock-controller at 11090000 {
+		compatible = "samsung,exynos5260-clock-mfc";
+		clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
+		clock-names = "fin_pll", "dout_aclk_mfc_333";
+		reg = <0x11090000 0x10000>;
+		#clock-cells = <1>;
+	};
+
+Example 2: UART controller node that consumes the clock generated by the
+		peri clock controller. Refer to the standard clock bindings for
+		information about 'clocks' and 'clock-names' property.
+
+	serial at 12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 146 0>;
+		clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+	};
+

include/dt-bindings/clock/exynos5260-clk.h new file +469 -0

469 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Rahul Sharma

author

2014-03-23 20:45 UTC #2 lore raw

PATCH v6 2/2 clk/exynos5260: add clock file for exynos5260

In reply to Rahul Sharma

Add support for exynos5260 clocks in clock driver.

Signed-off-by Rahul Sharma <[email protected]>

Signed-off-by Pankaj Dubey <[email protected]>

---
 drivers/clk/samsung/Makefile         |    1 +
 drivers/clk/samsung/clk-exynos5260.c | 1980 ++++++++++++++++++++++++++++++++++
 drivers/clk/samsung/clk-exynos5260.h |  459 ++++++++
 3 files changed, 2440 insertions(+)
 create mode 100644 drivers/clk/samsung/clk-exynos5260.c
 create mode 100644 drivers/clk/samsung/clk-exynos5260.h

drivers/clk/samsung/Makefile +1 -0

index 77313e2..56e7d38 100644
@@ -5,6 +5,7 @@
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o
 obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
 obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o

drivers/clk/samsung/clk-exynos5260.c new file +1980 -0

1,980 lines not on this page · raw message

drivers/clk/samsung/clk-exynos5260.h new file +459 -0

459 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-03-23 22:20 UTC #3 lore raw

v6 cover clk: exynos: add support for exynos5260 SoC

In reply to Rahul Sharma

Hi Rahul,

Quoted 54 lines · Rahul Sharma

From: Rahul Sharma <[email protected]>
Add clock support for exynos5260 SoC.
This series is based on Tomasz Figa's samsung-next branch.
V6:
1) Listed external Clocks in documentation file.
2) Listed Input Clocks for each clock controller in exynos5260-clock.txt.
3) Added Clock and Clock-names properties.
4) Assigned IDs to all clocks in the clock file.
5) Moved all PHY clocks as fixed rate to the driver file.
6) Reorder clocks to maintain acscending order on the basis of clock register offset and bit numer.
V5:
1) Include S3c2412 and S3c2443 in clock provider patch.
2) Added SCLK_TOP_FIMD with CLK_IGNORE_UNUSED due to Suspend failure.
3) Moved exynos5260-clk.h to include/dt-bindings/clock.
4) Fix exynos5260_clk_sleep_init protoype for PM disabled.W
5) Moved fixed clock registeration to DT.
6) Removed CLK_IGNORE_UNUSED flags from UART clocks. Earlier facing issues because of RFS probing all TTYs.
V4:
1) Rework clock file as per Tomasz review comments at
         http://www.spinics.net/lists/arm-kernel/msg310116.html.
V3:
1) Removed "samsung,exynos5260-clock" property from clock files.
2) Replaced "__SPIN_LOCK_UNLOCKED(lock)" with spin_lock_init.
3) Removed '(' and ')' around numeric constants in macros.
V2:
1) Move suspend resume handling to Exynos5410 Clock file.
2) Removed Unused Macros and Condition checks for Exynos5260.
3) Add spin lock to clock provider context.
4) Add clock provider context for Exynos5410.
5) Uniform implementation for callbacks for PLL2550xx.
6) Split Exynos5260 clock file patch to bring it under 100 Kb limit.
7) Replace aclk/pclk/hclk gates with combined gates.
8) Remove CLK_IGNORE_UNUSED flag for gate clocks.
Rahul Sharma (2):
clk/exynos5260: add macros and documentation for exynos5260 clk/exynos5260: add clock file for exynos5260
  .../devicetree/bindings/clock/exynos5260-clock.txt |  190 ++
  drivers/clk/samsung/Makefile                       |    1 +
  drivers/clk/samsung/clk-exynos5260.c               | 1980 ++++++++++++++++++++
  drivers/clk/samsung/clk-exynos5260.h               |  459 +++++
  include/dt-bindings/clock/exynos5260-clk.h         |  469 +++++
  5 files changed, 3099 insertions(+)

Quoted 5 lines

create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5260.c
create mode 100644 drivers/clk/samsung/clk-exynos5260.h
create mode 100644 include/dt-bindings/clock/exynos5260-clk.h

Looks good to me, will apply if no comments show up for few more days.

Best regards,
Tomasz

Rahul Sharma

2014-03-24 03:28 UTC #4 lore raw

v6 cover clk: exynos: add support for exynos5260 SoC

Thanks Tomasz,

Please let me know if any concern.
Meanwhile I will post dt patches with "clock" and "clock-names" properties added for each controller node.

Regards,
Rahul Sharma.

Quoted 72 lines · Tomasz Figa

Hi Rahul,
Quoted 57 lines · Rahul Sharma
From: Rahul Sharma <[email protected]>
Add clock support for exynos5260 SoC.
This series is based on Tomasz Figa's samsung-next branch.
V6:
1) Listed external Clocks in documentation file.
2) Listed Input Clocks for each clock controller in
exynos5260-clock.txt.
3) Added Clock and Clock-names properties.
4) Assigned IDs to all clocks in the clock file.
5) Moved all PHY clocks as fixed rate to the driver file.
6) Reorder clocks to maintain acscending order on the basis of clock register offset and bit numer.
V5:
1) Include S3c2412 and S3c2443 in clock provider patch.
2) Added SCLK_TOP_FIMD with CLK_IGNORE_UNUSED due to Suspend failure.
3) Moved exynos5260-clk.h to include/dt-bindings/clock.
4) Fix exynos5260_clk_sleep_init protoype for PM disabled.W
5) Moved fixed clock registeration to DT.
6) Removed CLK_IGNORE_UNUSED flags from UART clocks. Earlier facing issues because of RFS probing all TTYs.
V4:
1) Rework clock file as per Tomasz review comments at
         http://www.spinics.net/lists/arm-kernel/msg310116.html.
V3:
1) Removed "samsung,exynos5260-clock" property from clock files.
2) Replaced "__SPIN_LOCK_UNLOCKED(lock)" with spin_lock_init.
3) Removed '(' and ')' around numeric constants in macros.
V2:
1) Move suspend resume handling to Exynos5410 Clock file.
2) Removed Unused Macros and Condition checks for Exynos5260.
3) Add spin lock to clock provider context.
4) Add clock provider context for Exynos5410.
5) Uniform implementation for callbacks for PLL2550xx.
6) Split Exynos5260 clock file patch to bring it under 100 Kb limit.
7) Replace aclk/pclk/hclk gates with combined gates.
8) Remove CLK_IGNORE_UNUSED flag for gate clocks.
Rahul Sharma (2):
clk/exynos5260: add macros and documentation for exynos5260 clk/exynos5260: add clock file for exynos5260
  .../devicetree/bindings/clock/exynos5260-clock.txt |  190 ++
  drivers/clk/samsung/Makefile                       |    1 +
  drivers/clk/samsung/clk-exynos5260.c               | 1980
++++++++++++++++++++
  drivers/clk/samsung/clk-exynos5260.h               |  459 +++++
  include/dt-bindings/clock/exynos5260-clk.h         |  469 +++++
  5 files changed, 3099 insertions(+)
Quoted 6 lines
create mode 100644
Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h create mode 100644 include/dt-bindings/clock/exynos5260-clk.h
Looks good to me, will apply if no comments show up for few more days.
Best regards,
Tomasz

Rahul Sharma

2014-04-28 06:27 UTC #5 lore raw

v6 cover clk: exynos: add support for exynos5260 SoC

Hi Tomasz,

Is there anything pending with this patchset? Please consider this for 3.16.

Regards,
Rahul Sharma.

Quoted 14 lines · Rahul Sharma

Thanks Tomasz,
Please let me know if any concern.
Meanwhile I will post dt patches with "clock" and "clock-names" properties added for each controller node.
Regards,
Rahul Sharma.
Quoted 3 lines · Tomasz Figa
Hi Rahul,

[snip]

Quoted 5 lines

Quoted 5 lines
Looks good to me, will apply if no comments show up for few more days.
Best regards,
Tomasz