Add workaround for Cortex-A9 errata

PATCH New nitin.garg at freescale.com 3 participants 8 messages Apr 2, 2014 Arm (32-bit)

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nitin.garg at freescale.com

author

2014-04-02 03:33 UTC #0 lore raw

cover Add workaround for Cortex-A9 errata

From: Nitin Garg <[email protected]>

These patches implement workaround for 2 Cortex-A9 erratas.

Nitin Garg (2):
ARM: Add workaround for Cortex-A9 errata 794072
ARM: Add workaround for Cortex-A9 errata 761320

 README                     |    2 ++
 arch/arm/cpu/armv7/start.S |   10 ++++++++++
 2 files changed, 12 insertions(+), 0 deletions(-)

Signature · 1 line

1.7.4.1

nitin.garg at freescale.com

author

2014-04-02 03:33 UTC #1 lore raw

PATCH 1/2 ARM: Add workaround for Cortex-A9 errata 794072

From: Nitin Garg <[email protected]>

A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.

Signed-off-by Nitin Garg <[email protected]>

---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+), 0 deletions(-)

README +1 -0

index 7cb7c4f..a496c65 100644
@@ -566,6 +566,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the

arch/arm/cpu/armv7/start.S +5 -0

index ac1e55a..b87a378 100644
@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 11	@ set bit #11
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_794072
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 4		@ set bit #4
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)

Signature · 1 line

1.7.4.1

Dirk Behme

2014-04-02 06:41 UTC #2 lore raw

PATCH 1/2 ARM: Add workaround for Cortex-A9 errata 794072

Quoted 29 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by Nitin Garg <[email protected]>
---
  README                     |    1 +
  arch/arm/cpu/armv7/start.S |    5 +++++
  2 files changed, 6 insertions(+), 0 deletions(-)
README +1 -0
index 7cb7c4f..a496c65 100644
@@ -566,6 +566,7 @@ The following options need to be configured:
  		CONFIG_ARM_ERRATA_742230
  		CONFIG_ARM_ERRATA_743622
  		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
 
  		If set, the workarounds for these ARM errata are applied early
  		during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/start.S +0 -0
index ac1e55a..b87a378 100644

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 229

Quoted 8 lines

arch/arm/cpu/armv7/start.S +5 -0

@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
  	orr	r0, r0, #1 << 11	@ set bit #11
  	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
  #endif
+#ifdef CONFIG_ARM_ERRATA_794072
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 4		@ set bit #4
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif

Where is the difference between the errata code for above new CONFIG_ARM_ERRATA_794072 and the existing

#ifdef CONFIG_ARM_ERRATA_742230
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 4		@ set bit #4
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register

#endif

Maybe we should just do a

#if (defined(CONFIG_ARM_ERRATA_794072) || defined(CONFIG_ARM_ERRATA_742230))

Best regards

Dirk

Nitin Garg

author

2014-04-02 12:43 UTC #3 lore raw

PATCH 1/2 ARM: Add workaround for Cortex-A9 errata 794072

Good point! I will do that.

Regards,
Nitin Garg

-----Original Message-----
From: Dirk Behme [mailto:dirk.behme at de.bosch.com]
Sent: Wednesday, April 02, 2014 1:42 AM
To: Garg Nitin-B37173
Cc: trini at ti.com; Estevam Fabio-R49496; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 1/2] ARM: Add workaround for Cortex-A9 errata 794072

Quoted 29 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by Nitin Garg <[email protected]>
---
  README                     |    1 +
  arch/arm/cpu/armv7/start.S |    5 +++++
  2 files changed, 6 insertions(+), 0 deletions(-)
README +1 -1
index 7cb7c4f..a496c65 100644
@@ -566,6 +566,7 @@ The following options need to be configured:
  		CONFIG_ARM_ERRATA_742230
  		CONFIG_ARM_ERRATA_743622
  		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
 
  		If set, the workarounds for these ARM errata are applied early
  		during U-Boot startup. Note that these options force the diff 
--git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 
ac1e55a..b87a378 100644

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 229

Quoted 8 lines

arch/arm/cpu/armv7/start.S +5 -0

@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
  	orr	r0, r0, #1 << 11	@ set bit #11
  	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
  #endif
+#ifdef CONFIG_ARM_ERRATA_794072
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 4		@ set bit #4
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif

Where is the difference between the errata code for above new CONFIG_ARM_ERRATA_794072 and the existing

#ifdef CONFIG_ARM_ERRATA_742230
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 4		@ set bit #4
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register

#endif

Maybe we should just do a

#if (defined(CONFIG_ARM_ERRATA_794072) || defined(CONFIG_ARM_ERRATA_742230))

Best regards

Dirk

nitin.garg at freescale.com

author

2014-04-02 03:33 UTC #4 lore raw

PATCH 2/2 ARM: Add workaround for Cortex-A9 errata 761320

In reply to nitin.garg at freescale.com

From: Nitin Garg <[email protected]>

Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.

Signed-off-by Nitin Garg <[email protected]>

---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+), 0 deletions(-)

README +1 -0

index a496c65..b7c0f68 100644
@@ -567,6 +567,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the

arch/arm/cpu/armv7/start.S +5 -0

index b87a378..1229476 100644
@@ -227,6 +227,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 4		@ set bit #4
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)

Signature · 1 line

1.7.4.1

Dirk Behme

2014-04-02 06:45 UTC #5 lore raw

PATCH 2/2 ARM: Add workaround for Cortex-A9 errata 761320

Quoted 29 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
Signed-off-by Nitin Garg <[email protected]>
---
  README                     |    1 +
  arch/arm/cpu/armv7/start.S |    5 +++++
  2 files changed, 6 insertions(+), 0 deletions(-)
README +1 -0
index a496c65..b7c0f68 100644
@@ -567,6 +567,7 @@ The following options need to be configured:
  		CONFIG_ARM_ERRATA_743622
  		CONFIG_ARM_ERRATA_751472
  		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
  		If set, the workarounds for these ARM errata are applied early
  		during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/start.S +0 -0
index b87a378..1229476 100644

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 234

Quoted 8 lines

arch/arm/cpu/armv7/start.S +5 -0

@@ -227,6 +227,11 @@ ENTRY(cpu_init_cp15)
  	orr	r0, r0, #1 << 4		@ set bit #4
  	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
  #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif

Is there any reason why you dropped the check for r4p0

cmp r6, #0x40 @ present prior to r4p0

which you still had in

http://www.spinics.net/lists/arm-kernel/msg319223.html

Best regards

Dirk

Nitin Garg

author

2014-04-02 12:44 UTC #6 lore raw

PATCH 2/2 ARM: Add workaround for Cortex-A9 errata 761320

Hi Dirk,

There is no revision and variant in this cpu_init_cp15 function. I think this function is common unlike kernel code which was cortex specific.

Regards,
Nitin Garg

-----Original Message-----
From: Dirk Behme [mailto:dirk.behme at de.bosch.com]
Sent: Wednesday, April 02, 2014 1:46 AM
To: Garg Nitin-B37173
Cc: trini at ti.com; Estevam Fabio-R49496; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 2/2] ARM: Add workaround for Cortex-A9 errata 761320

Quoted 29 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>

Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.

Signed-off-by Nitin Garg <[email protected]>

---
  README                     |    1 +
  arch/arm/cpu/armv7/start.S |    5 +++++
  2 files changed, 6 insertions(+), 0 deletions(-)

README +1 -1

index a496c65..b7c0f68 100644
@@ -567,6 +567,7 @@ The following options need to be configured:
  		CONFIG_ARM_ERRATA_743622
  		CONFIG_ARM_ERRATA_751472
  		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
  		If set, the workarounds for these ARM errata are applied early
  		during U-Boot startup. Note that these options force the diff 
--git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index

b87a378..1229476 100644

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 234

Quoted 8 lines

arch/arm/cpu/armv7/start.S +5 -0

@@ -227,6 +227,11 @@ ENTRY(cpu_init_cp15)
  	orr	r0, r0, #1 << 4		@ set bit #4
  	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
  #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif

Is there any reason why you dropped the check for r4p0

cmp r6, #0x40 @ present prior to r4p0

which you still had in

http://www.spinics.net/lists/arm-kernel/msg319223.html

Best regards

Dirk

Fabio Estevam

2014-04-02 04:27 UTC #7 lore raw

cover Add workaround for Cortex-A9 errata

In reply to nitin.garg at freescale.com

Hi Nitin,

Quoted 11 lines · On Wed, Apr 2, 2014 at 12:33 AM, <[email protected]> wrote:

From: Nitin Garg <[email protected]>
These patches implement workaround for 2 Cortex-A9 erratas.
Nitin Garg (2):
ARM: Add workaround for Cortex-A9 errata 794072
ARM: Add workaround for Cortex-A9 errata 761320
 README                     |    2 ++
 arch/arm/cpu/armv7/start.S |   10 ++++++++++
 2 files changed, 12 insertions(+), 0 deletions(-)

I would expect a third patch in this series that would actually define the new errata configuration (like include/configs/mx6_common.h, for example), otherwise this series just adds dead code.

Regards,

Fabio Estevam