Add workaround for Cortex-A9 errata
cover Add workaround for Cortex-A9 errata
From: Nitin Garg <[email protected]>
These patches implement workaround for 2 Cortex-A9 erratas. Enable these errata workaround for MX6.
Nitin Garg (3):
ARM: Add workaround for Cortex-A9 errata 794072
ARM: Add workaround for Cortex-A9 errata 761320
MX6: Enable ARM errata workaround 794072 and 761320
README | 2 ++ arch/arm/cpu/armv7/start.S | 7 ++++++- include/configs/mx6_common.h | 2 ++ 3 files changed, 10 insertions(+), 1 deletions(-)
Signature · 1 line
1.7.4.1
PATCH 1/3 ARM: Add workaround for Cortex-A9 errata 794072
From: Nitin Garg <[email protected]>
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
--- README | 1 + arch/arm/cpu/armv7/start.S | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-)
README +1 -0
@@ -566,6 +566,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/start.S +1 -1
@@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
Signature · 1 line
1.7.4.1
PATCH 1/3 ARM: Add workaround for Cortex-A9 errata 794072
Quoted 30 lines · nitin.garg at freescale.com
From: Nitin Garg <[email protected]>
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by Nitin Garg <[email protected]>--- README | 1 + arch/arm/cpu/armv7/start.S | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-)README +1
-0@@ -566,6 +566,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force thearch/arm/cpu/armv7/start.S +0
-0
arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 211
Quoted 8 lines
arch/arm/cpu/armv7/start.S +1
-1@@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
Best regards
Dirk
PATCH 2/3 ARM: Add workaround for Cortex-A9 errata 761320
In reply to nitin.garg at freescale.comFrom: Nitin Garg <[email protected]>
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
--- README | 1 + arch/arm/cpu/armv7/start.S | 5 +++++ 2 files changed, 6 insertions(+), 0 deletions(-)
README +1 -0
@@ -567,6 +567,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/start.S +5 -0
@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)
Signature · 1 line
1.7.4.1
PATCH 3/3 MX6: Enable ARM errata workaround 794072 and 761320
In reply to nitin.garg at freescale.comFrom: Nitin Garg <[email protected]>
Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 794072 and 761320.
--- include/configs/mx6_common.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
include/configs/mx6_common.h +2 -0
@@ -20,6 +20,8 @@#define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 +#define CONFIG_ARM_ERRATA_794072 +#define CONFIG_ARM_ERRATA_761320 #define CONFIG_BOARD_POSTCLK_INIT #ifndef CONFIG_SYS_L2CACHE_OFF
Signature · 1 line
1.7.4.1