Add workaround for Cortex-A9 errata

PATCH New nitin.garg at freescale.com 3 participants 12 messages Apr 2, 2014 – Apr 7, 2014 Arm (32-bit)

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nitin.garg at freescale.com

author

2014-04-02 13:55 UTC #0 lore raw

v3 cover Add workaround for Cortex-A9 errata

From: Nitin Garg <[email protected]>

These patches implement workaround for 2 Cortex-A9 erratas. Enable these errata workaround for MX6.

Changes since v2:
- Added Acked-by Dirk Behme for PATCH 1/3
- Added Stefano for review

Changes since v1:
- Enabled these erratas for MX6 as suggested by Fabio Estevam
- Reused code for errata 794072 as suggested by Dirk Behme

Nitin Garg (3):
ARM: Add workaround for Cortex-A9 errata 794072
ARM: Add workaround for Cortex-A9 errata 761320
MX6: Enable ARM errata workaround 794072 and 761320

 README                       |    2 ++
 arch/arm/cpu/armv7/start.S   |    7 ++++++-
 include/configs/mx6_common.h |    2 ++
 3 files changed, 10 insertions(+), 1 deletions(-)

Signature · 1 line

1.7.4.1

nitin.garg at freescale.com

author

2014-04-02 13:55 UTC #1 lore raw

PATCH v3 1/3 ARM: Add workaround for Cortex-A9 errata 794072

From: Nitin Garg <[email protected]>

A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.

Signed-off-by Nitin Garg <[email protected]>

Acked-by Dirk Behme <[email protected]>

---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)

README +1 -0

index 7cb7c4f..a496c65 100644
@@ -566,6 +566,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the

arch/arm/cpu/armv7/start.S +1 -1

index ac1e55a..f3830c8 100644
@@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15)
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register

Signature · 1 line

1.7.4.1

Stefano Babic

2014-04-02 15:26 UTC #2 lore raw

PATCH v3 1/3 ARM: Add workaround for Cortex-A9 errata 794072

Hi Nitin,

Quoted 31 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by Nitin Garg <[email protected]>
Acked-by Dirk Behme <[email protected]>
---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)
README +1 -0
index 7cb7c4f..a496c65 100644
@@ -566,6 +566,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/start.S +0 -0
index ac1e55a..f3830c8 100644

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 211

Quoted 8 lines

arch/arm/cpu/armv7/start.S +1 -1

@@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15)
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register

Apart having an additional errata number, which is the contribute of CONFIG_ARM_ERRATA_794072 ? We are already covered with CONFIG_ARM_ERRATA_742230 and the work-around for dmb is already implemented.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Nitin Garg

author

2014-04-02 15:46 UTC #3 lore raw

PATCH v3 1/3 ARM: Add workaround for Cortex-A9 errata 794072

Hi Stefano,

Errata 742230 applies to r1p0, r1p1, r1p2, r1p3, r2p0, r2p1, r2p2 revision of Cortex-A9. Errata 794072 applies to r1, 2, r3, r4 revisions. Software workaround is same for both.

Since diff products use diff revisions of core, I would suggest to have it this way. Otherwise it might lead to confusion if one has to enable 742230 (for 794072 workaround) even though the core revision does not need it.

Regards,
Nitin Garg

-----Original Message-----
From: Stefano Babic [mailto:sbabic at denx.de]
Sent: Wednesday, April 02, 2014 10:26 AM
To: Garg Nitin-B37173; trini at ti.com; Estevam Fabio-R49496; sbabic at denx.de
Cc: u-boot at lists.denx.de
Subject: Re: [PATCH v3 1/3] ARM: Add workaround for Cortex-A9 errata 794072

Hi Nitin,

Quoted 31 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by Nitin Garg <[email protected]>
Acked-by Dirk Behme <[email protected]>
---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)
README +1 -0
index 7cb7c4f..a496c65 100644
@@ -566,6 +566,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_742230
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
+		CONFIG_ARM_ERRATA_794072
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the diff --git 
a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ac1e55a..f3830c8 100644

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 211

Quoted 9 lines

arch/arm/cpu/armv7/start.S +2 -1

@@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15)
 	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_742230
+#if (defined(CONFIG_ARM_ERRATA_742230) || 
+defined(CONFIG_ARM_ERRATA_794072))
 	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
 	orr	r0, r0, #1 << 4		@ set bit #4
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register

Best regards,
Stefano Babic

--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================

Stefano Babic

2014-04-07 16:16 UTC #4 lore raw

PATCH v3 1/3 ARM: Add workaround for Cortex-A9 errata 794072

In reply to nitin.garg at freescale.com

Quoted 9 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions.
Signed-off-by Nitin Garg <[email protected]>
Acked-by Dirk Behme <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

nitin.garg at freescale.com

author

2014-04-02 13:55 UTC #5 lore raw

PATCH v3 2/3 ARM: Add workaround for Cortex-A9 errata 761320

In reply to nitin.garg at freescale.com

From: Nitin Garg <[email protected]>

Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.

Signed-off-by Nitin Garg <[email protected]>

---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+), 0 deletions(-)

README +1 -0

index a496c65..b7c0f68 100644
@@ -567,6 +567,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the

arch/arm/cpu/armv7/start.S +5 -0

index f3830c8..27be451 100644
@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 11	@ set bit #11
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)

Signature · 1 line

1.7.4.1

Stefano Babic

2014-04-02 15:28 UTC #6 lore raw

PATCH v3 2/3 ARM: Add workaround for Cortex-A9 errata 761320

Hi Nitin,

Quoted 31 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>

Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.

Signed-off-by Nitin Garg <[email protected]>

---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+), 0 deletions(-)

README +1 -0

index a496c65..b7c0f68 100644
@@ -567,6 +567,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the

arch/arm/cpu/armv7/start.S +0 -0

index f3830c8..27be451 100644
@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 11	@ set bit #11

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 232

Quoted 10 lines

arch/arm/cpu/armv7/start.S +5 -0

 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)

I admit I am not able to find the documentation for this errata neither the ARM center nor in the i.MX6 errata. Do you have a link to get some more infos about it ?

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Nitin Garg

author

2014-04-02 15:47 UTC #7 lore raw

PATCH v3 2/3 ARM: Add workaround for Cortex-A9 errata 761320

Sorry, I don't have a link. We are in the process of updating the i.MX6 Chip errata document to include this.

Regards,
Nitin Garg

-----Original Message-----
From: Stefano Babic [mailto:sbabic at denx.de]
Sent: Wednesday, April 02, 2014 10:29 AM
To: Garg Nitin-B37173; trini at ti.com; Estevam Fabio-R49496; sbabic at denx.de
Cc: u-boot at lists.denx.de
Subject: Re: [PATCH v3 2/3] ARM: Add workaround for Cortex-A9 errata 761320

Hi Nitin,

Quoted 31 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
Signed-off-by Nitin Garg <[email protected]>
---
 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+), 0 deletions(-)
README +1 -0
index a496c65..b7c0f68 100644
@@ -567,6 +567,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_743622
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
+		CONFIG_ARM_ERRATA_761320
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the diff --git 
a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f3830c8..27be451 100644
arch/arm/cpu/armv7/start.S +0 -0
@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 11	@ set bit #11

arch/arm/cpu/armv7/start.S ENTRY(cpu_init_cp15) · line 232

Quoted 10 lines

arch/arm/cpu/armv7/start.S +5 -0

 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)

I admit I am not able to find the documentation for this errata neither the ARM center nor in the i.MX6 errata. Do you have a link to get some more infos about it ?

Best regards,
Stefano Babic

Fabio Estevam

2014-04-03 01:27 UTC #8 lore raw

PATCH v3 2/3 ARM: Add workaround for Cortex-A9 errata 761320

In reply to nitin.garg at freescale.com

Quoted 7 lines · On Wed, Apr 2, 2014 at 10:55 AM, <[email protected]> wrote:

From: Nitin Garg <[email protected]>
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
Signed-off-by Nitin Garg <[email protected]>

Acked-by Fabio Estevam <[email protected]>

Stefano Babic

2014-04-07 16:16 UTC #9 lore raw

PATCH v3 2/3 ARM: Add workaround for Cortex-A9 errata 761320

In reply to nitin.garg at freescale.com

Quoted 8 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions.
Signed-off-by Nitin Garg <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

nitin.garg at freescale.com

author

2014-04-02 13:55 UTC #10 lore raw

PATCH v3 3/3 MX6: Enable ARM errata workaround 794072 and 761320

In reply to nitin.garg at freescale.com

From: Nitin Garg <[email protected]>

Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 794072 and 761320.

Signed-off-by Nitin Garg <[email protected]>

---
 include/configs/mx6_common.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

include/configs/mx6_common.h +2 -0

index eb107d3..8a8920f 100644
@@ -20,6 +20,8 @@
 #define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
+#define CONFIG_ARM_ERRATA_794072
+#define CONFIG_ARM_ERRATA_761320
 #define CONFIG_BOARD_POSTCLK_INIT
 
 #ifndef CONFIG_SYS_L2CACHE_OFF

Signature · 1 line

1.7.4.1

Stefano Babic

2014-04-07 16:16 UTC #11 lore raw

PATCH v3 3/3 MX6: Enable ARM errata workaround 794072 and 761320

Quoted 7 lines · nitin.garg at freescale.com

From: Nitin Garg <[email protected]>
Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 794072 and 761320.
Signed-off-by Nitin Garg <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================