ARM: shmobile: r8a7790: link PCI USb devices to USB PHY
Subsystems (2)
PATCH 1/1 ARM: shmobile: r8a7790: link PCI USb devices to USB PHY
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device.
Based on the original work by Ben Dooks <[email protected]>.
---
This patch is against 'renesas-devel-v3.14-20140408' tag of Simon Horman's 'renesas.git' repo plus R8A7790/Lager PCI and USB PHY support patches posted yesterday and day before. The patch requires the internal PCI and USB PHY drivers (also already posted) in order to work...
arch/arm/boot/dts/r8a7790.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
arch/arm/boot/dts/r8a7790.dtsi +28 -0
@@ -841,6 +841,20 @@ bus-range = <0 0>; #address-cells = <3>; #size-cells = <2>; + + pci at 0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 0 0>; + phy-names = "usb"; + }; + + pci at 0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 0 0>; + phy-names = "usb"; + }; }; pci1: pci at ee0b0000 {
@@ -867,5 +881,19 @@ bus-range = <2 2>; #address-cells = <3>; #size-cells = <2>; + + pci at 0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 2 0>; + phy-names = "usb"; + }; + + pci at 0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 2 0>; + phy-names = "usb"; + }; }; };
PATCH 1/1 ARM: shmobile: r8a7790: link PCI USb devices to USB PHY
Hi Sergei,
Thanks for this patch, good to see that the relationship between the USB Host and the PHY is described via DT.
This patch seems to cover USB0 and USB2 that both require special control in the PHY. How about USB1? Can you explain about the reason why you omit that?
I somehow expected USB1 to be tied to the PHY via DT as well, this so the PHY driver can be able to disable the hardware if no ports are registered. In detail, I'm thinking that the register.bit UGCTL.CONNECT wants to be set to 0 by default but be set to 1 once one or more USB controllers are hooked up to the PHY.
Cheers,
/ magnus
Quoted 61 lines · Sergei Shtylyov
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device.
Based on the original work by Ben Dooks <[email protected]>.
Signed-off-by Sergei Shtylyov <[email protected]>---
This patch is against 'renesas-devel-v3.14-20140408' tag of Simon Horman's 'renesas.git' repo plus R8A7790/Lager PCI and USB PHY support patches posted yesterday and day before. The patch requires the internal PCI and USB PHY drivers (also already posted) in order to work...arch/arm/boot/dts/r8a7790.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)Index:
renesas/arch/arm/boot/dts/r8a7790.dtsi
===================================================================arch/arm/boot/dts/r8a7790.dtsi +28
-0@@ -841,6 +841,20 @@ bus-range = <0 0>; #address-cells = <3>; #size-cells = <2>; + + pci at 0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 0 0>; + phy-names = "usb"; + }; + + pci at 0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 0 0>; + phy-names = "usb"; + }; }; pci1: pci at ee0b0000 {@@ -867,5 +881,19 @@ bus-range = <2 2>; #address-cells = <3>; #size-cells = <2>; + + pci at 0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 2 0>; + phy-names = "usb"; + }; + + pci at 0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usbphy 2 0>; + phy-names = "usb"; + }; }; };
PATCH 1/1 ARM: shmobile: r8a7790: link PCI USb devices to USB PHY
Hello.
Quoted 6 lines · Magnus Damm
Thanks for this patch, good to see that the relationship between the USB Host and the PHY is described via DT.
This patch seems to cover USB0 and USB2 that both require special control in the PHY. How about USB1? Can you explain about the reason why you omit that?
Because the driver does nothing for USB1 anyway.
Quoted 5 lines
I somehow expected USB1 to be tied to the PHY via DT as well, this so the PHY driver can be able to disable the hardware if no ports are registered. In detail, I'm thinking that the register.bit UGCTL.CONNECT wants to be set to 0 by default but be set to 1 once one or more USB controllers are hooked up to the PHY.
I don't think this bit has any sense for non-USBHS controllers. EHCI/OHCI
drivers happily work without setting it.
WBR, Sergei
PATCH 1/1 ARM: shmobile: r8a7790: link PCI USb devices to USB PHY
Quoted 8 lines · Sergei Shtylyov
Quoted 6 lines
Thanks for this patch, good to see that the relationship between the USB Host and the PHY is described via DT.
This patch seems to cover USB0 and USB2 that both require special control in the PHY. How about USB1? Can you explain about the reason why you omit that?
Because the driver does nothing for USB1 anyway.
Looks like I should have tested that last minute change: kernel oopses due
to NULL pointer dereference somewhere in phy_get() once it gets called for EHCI on the channel #1. At least doesn't seem to be my mistake...
WBR, Sergei
PATCH 1/1 ARM: shmobile: r8a7790: link PCI USb devices to USB PHY
Hi Sergei,
Quoted 11 lines · Sergei Shtylyov
Quoted 7 lines · Sergei Shtylyov
Quoted 7 lines
Thanks for this patch, good to see that the relationship between the USB Host and the PHY is described via DT.
This patch seems to cover USB0 and USB2 that both require special control in the PHY. How about USB1? Can you explain about the reason why you omit that?
Quoted 6 lines
Quoted 1 line
Because the driver does nothing for USB1 anyway.
Looks like I should have tested that last minute change: kernel oopses
due to NULL pointer dereference somewhere inphy_get()once it gets called for EHCI on the channel #1. At least doesn't seem to be my mistake...
No worries, thanks for looking into fixing that.
Regarding the USB ports on R-Car Gen2 in general and especially USB1, it is my impression that even though there is no USB controller selection available for USB1 I still believe the UGCTL.CONNECT bit shall be used for power management purpose.
I may of course be wrong, but since the PHY hardware is shared between USB0, USB1 and USB2 it makes sense to have some kind of usage counter and manage the hardware enable bit based on registered users somehow. There is no need to manage this bit at this point IMO, but in the future we may want to add such handling to improve power management. And that can only happen if DT is used to connect all USB controllers with the PHY, so please make sure to describe the complete dependencies in DT.
Thanks,
/ magnus
PATCH 1/1 ARM: shmobile: r8a7790: link PCI USb devices to USB PHY
Quoted 13 lines · Magnus Damm
Quoted 7 lines
Quoted 6 lines
Quoted 6 lines
Thanks for this patch, good to see that the relationship between the USB Host and the PHY is described via DT.
This patch seems to cover USB0 and USB2 that both require special control in the PHY. How about USB1? Can you explain about the reason why you omit that?
Quoted 5 lines
Quoted 1 line
Because the driver does nothing for USB1 anyway.
Looks like I should have tested that last minute change: kernel oopses
due to NULL pointer dereference somewhere inphy_get()once it gets called for EHCI on the channel #1. At least doesn't seem to be my mistake...
Quoted 6 lines
No worries, thanks for looking into fixing that.
Regarding the USB ports on R-Car Gen2 in general and especially USB1, it is my impression that even though there is no USB controller selection available for USB1 I still believe the UGCTL.CONNECT bit shall be used for power management purpose.
I don't think so. As I said the EHCI driver happily works without touching
this bit.
Quoted 2 lines
I may of course be wrong, but since the PHY hardware is shared between USB0, USB1 and USB2
I believe it's a wrong impression (which probably my and Valentine's PHY
drivers have created). The PHY actually belongs to USBHS only; UGCTRL2 register is some kind of ad-hockery in this PHY.
Quoted 1 line
it makes sense to have some kind of usage counter
Generic PHY core already maintains such counters for phy_{init|exit}() and
phy_power_{on|off}() calls.
Quoted 3 lines
and manage the hardware enable bit based on registered users somehow. There is no need to manage this bit at this point IMO, but in the future we may want to add such handling to improve power management.
I handle this bit but only for USBHS. What is actually necessary for all
USB controllers is enabling the USBHS clocks in order for UGCTRL2 to work.
Quoted 3 lines
And that can only happen if DT is used to connect all USB controllers with the PHY, so please make sure to describe the complete dependencies in DT.
I cannnot represent USBHS in the device tree yet. I think I can represent
xHCI there but I was told it needs the firmware in order to work -- which we don't have, so I'm not sure about xHCI testing.
Quoted 3 lines
Thanks,
/ magnus
WBR, Sergei