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clk: exynos4: Use single clock ID for CLK_MDMA gate clocks

PATCH New Sylwester Nawrocki 2 participants 3 messages Apr 15, 2014 – Apr 30, 2014

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Device tree bindings Common clk Arm Samsung Exynos Samsung SoC clock drivers
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Sylwester Nawrocki

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#0 lore raw

PATCH 1/1 clk: exynos4: Use single clock ID for CLK_MDMA gate clocks

Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs.

Suggested-by Tomasz Figa <[email protected]>
Signed-off-by Sylwester Nawrocki <[email protected]>
Acked-by Kyungmin Park <[email protected]>
---
 drivers/clk/samsung/clk-exynos4.c   |    2 +-
 include/dt-bindings/clock/exynos4.h |    1 -
 2 files changed, 1 insertion(+), 2 deletions(-)
drivers/clk/samsung/clk-exynos4.c +1 -1
index b4f9672..5247caa 100644
@@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 	GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
 	GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
 	GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
-	GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+	GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
 	GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
 		0),
 	GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
include/dt-bindings/clock/exynos4.h +0 -1
index 75aff33..3ff13bc 100644
@@ -181,7 +181,6 @@
 #define CLK_KEYIF		347
 #define CLK_AUDSS		348
 #define CLK_MIPI_HSI		349 /* Exynos4210 only */
-#define CLK_MDMA2		350 /* Exynos4210 only */
 #define CLK_PIXELASYNCM0	351
 #define CLK_PIXELASYNCM1	352
 #define CLK_FIMC_LITE0		353 /* Exynos4x12 only */
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 clk: exynos4: Use single clock ID for CLK_MDMA gate clocks

Hi Sylwester,

Quoted 34 lines · Sylwester Nawrocki

Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs.

Suggested-by Tomasz Figa <[email protected]>
Signed-off-by Sylwester Nawrocki <[email protected]>
Acked-by Kyungmin Park <[email protected]>
---
  drivers/clk/samsung/clk-exynos4.c   |    2 +-
  include/dt-bindings/clock/exynos4.h |    1 -
  2 files changed, 1 insertion(+), 2 deletions(-)
drivers/clk/samsung/clk-exynos4.c +1 -1
index b4f9672..5247caa 100644
@@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
  	GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
  	GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
  	GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
-	GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+	GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
  	GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
  		0),
  	GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
include/dt-bindings/clock/exynos4.h +0 -0
index 75aff33..3ff13bc 100644

include/dt-bindings/clock/exynos4.h line 186

Quoted 7 lines
include/dt-bindings/clock/exynos4.h +0 -1
@@ -181,7 +181,6 @@
  #define CLK_KEYIF		347
  #define CLK_AUDSS		348
  #define CLK_MIPI_HSI		349 /* Exynos4210 only */
-#define CLK_MDMA2		350 /* Exynos4210 only */
  #define CLK_PIXELASYNCM0	351
  #define CLK_PIXELASYNCM1	352
  #define CLK_FIMC_LITE0		353 /* Exynos4x12 only */

Looks good, will apply. Thanks.

Best regards,
Tomasz

Applied
#2 lore raw

PATCH 1/1 clk: exynos4: Use single clock ID for CLK_MDMA gate clocks

In reply to Sylwester Nawrocki
Quoted 34 lines · Sylwester Nawrocki

Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs.

Suggested-by Tomasz Figa <[email protected]>
Signed-off-by Sylwester Nawrocki <[email protected]>
Acked-by Kyungmin Park <[email protected]>
---
  drivers/clk/samsung/clk-exynos4.c   |    2 +-
  include/dt-bindings/clock/exynos4.h |    1 -
  2 files changed, 1 insertion(+), 2 deletions(-)
drivers/clk/samsung/clk-exynos4.c +1 -1
index b4f9672..5247caa 100644
@@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
  	GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
  	GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
  	GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
-	GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+	GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
  	GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
  		0),
  	GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
include/dt-bindings/clock/exynos4.h +0 -0
index 75aff33..3ff13bc 100644

include/dt-bindings/clock/exynos4.h line 186

Quoted 7 lines
include/dt-bindings/clock/exynos4.h +0 -1
@@ -181,7 +181,6 @@
  #define CLK_KEYIF		347
  #define CLK_AUDSS		348
  #define CLK_MIPI_HSI		349 /* Exynos4210 only */
-#define CLK_MDMA2		350 /* Exynos4210 only */
  #define CLK_PIXELASYNCM0	351
  #define CLK_PIXELASYNCM1	352
  #define CLK_FIMC_LITE0		353 /* Exynos4x12 only */

Applied.

Best regards,
Tomasz