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Add initial support of PMU for exynos5260

PATCH New Vikas Sajjan 6 participants 13 messages Mar 17, 2014 – Apr 17, 2014

Subsystems (5)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm Samsung Exynos +1 more subsystems
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Vikas Sajjan

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#0 lore raw

v2 cover Add initial support of PMU for exynos5260

From: Vikas Sajjan <[email protected]>

1) Added initial PMU support for exynos5260

2) Added S2R(single CPU) support on exynos5260

3) Added PMU mapping via DT.

rebased on
1) kgene tree for-next branch
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

2) Rahul's patches for basic support of exynos5260
http://www.spinics.net/lists/linux-samsung-soc/msg27282.html

3) Rahul's clk patches http://www.spinics.net/lists/linux-samsung-soc/msg27275.html

4) Tomasz Figa's http://permalink.gmane.org/gmane.linux.ports.arm.kernel/299340

Changes since v1:
-- Addressed Tomasz Figa's comments. -- removed CMU patch
-- Added PMU mapping via DT

Vikas Sajjan (3):
ARM: EXYNOS: Map PMU address through DT
ARM: EXYNOS: Add initial support of PMU for Exynos5260
arm: exynos5260: add support for S2R

 .../devicetree/bindings/arm/samsung/pmu.txt        |    5 +-
 arch/arm/boot/dts/exynos4.dtsi                     |    5 +
 arch/arm/boot/dts/exynos5260.dtsi                  |    5 +
 arch/arm/mach-exynos/common.c                      |   51 ++--
 arch/arm/mach-exynos/common.h                      |   26 +++
 arch/arm/mach-exynos/include/mach/map.h            |    3 -
 arch/arm/mach-exynos/pm.c                          |   96 ++++++--
 arch/arm/mach-exynos/pmu.c                         |  238 +++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h                    |  244 ++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/cpu.h           |    8 +
 10 files changed, 637 insertions(+), 44 deletions(-)
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v2 1/3 ARM: EXYNOS: Map PMU address through DT

Instead of hardcoding the PMU details for each SoC, pass this information through device tree (DT).

Signed-off-by Vikas Sajjan <[email protected]>
---
 .../devicetree/bindings/arm/samsung/pmu.txt        |    5 +-
 arch/arm/boot/dts/exynos4.dtsi                     |    5 ++
 arch/arm/boot/dts/exynos5260.dtsi                  |    5 ++
 arch/arm/mach-exynos/common.c                      |   51 +++++++++++++-------
 arch/arm/mach-exynos/include/mach/map.h            |    3 --
 5 files changed, 47 insertions(+), 22 deletions(-)
Documentation/devicetree/bindings/arm/samsung/pmu.txt +3 -2
index f1f1552..667a7f0 100644
@@ -2,14 +2,15 @@ SAMSUNG Exynos SoC series PMU Registers
 
 Properties:
  - compatible : should contain two values. First value must be one from following list:
+		   - "samsung,exynos4210-pmu" - for Exynos4210 and Exynos4x12 SoC,
 		   - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
-		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+		   - "samsung,exynos5420-pmu" - for Exynos5420 and Exynos5260 SoC.
 		second value must be always "syscon".
 
  - reg : offset and length of the register set.
 
 Example :
 pmu_system_controller: system-controller@10040000 {
-	compatible = "samsung,exynos5250-pmu", "syscon";
+	compatible = "samsung,exynos5250-pmu";
 	reg = <0x10040000 0x5000>;
 };
arch/arm/boot/dts/exynos4.dtsi +5 -0
index 08452e1..94cbafa 100644
@@ -55,6 +55,11 @@
 		#phy-cells = <1>;
 	};
 
+	pmu_system_controller: system-controller@10020000 {
+		compatible = "samsung,exynos4210-pmu";
+		reg = <0x10020000 0x4000>;
+	};
+
 	pd_mfc: mfc-power-domain@10023C40 {
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x10023C40 0x20>;
arch/arm/boot/dts/exynos5260.dtsi +5 -0
index a93fea8..2a4dace 100644
@@ -264,6 +264,11 @@
 			};
 		};
 
+		pmu_system_controller: system-controller@10D50000 {
+			compatible = "samsung,exynos5420-pmu";
+			reg = <0x10D50000 0x5000>;
+		};
+
 		pinctrl_0: pinctrl@11600000 {
 			compatible = "samsung,exynos5260-pinctrl";
 			reg = <0x11600000 0x1000>;
arch/arm/mach-exynos/common.c +34 -17

94 lines not on this page · raw message

arch/arm/mach-exynos/include/mach/map.h +0 -3
index 548269a..34eee6e 100644
@@ -28,9 +28,6 @@
 #define EXYNOS4_PA_SYSCON		0x10010000
 #define EXYNOS5_PA_SYSCON		0x10050100
 
-#define EXYNOS4_PA_PMU			0x10020000
-#define EXYNOS5_PA_PMU			0x10040000
-
 #define EXYNOS4_PA_CMU			0x10030000
 #define EXYNOS5_PA_CMU			0x10010000
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH v2 1/3 ARM: EXYNOS: Map PMU address through DT

Hi Vikas,

Quoted 22 lines · Vikas Sajjan

Instead of hardcoding the PMU details for each SoC, pass this information through device tree (DT).

Signed-off-by Vikas Sajjan <[email protected]>
---
 .../devicetree/bindings/arm/samsung/pmu.txt        |    5 +-
 arch/arm/boot/dts/exynos4.dtsi                     |    5 ++
 arch/arm/boot/dts/exynos5260.dtsi                  |    5 ++
 arch/arm/mach-exynos/common.c                      |   51 +++++++++++++-------
 arch/arm/mach-exynos/include/mach/map.h            |    3 --
 5 files changed, 47 insertions(+), 22 deletions(-)
Documentation/devicetree/bindings/arm/samsung/pmu.txt +1 -0
index f1f1552..667a7f0 100644
@@ -2,14 +2,15 @@ SAMSUNG Exynos SoC series PMU Registers
 
 Properties:
  - compatible : should contain two values. First value must be one from following list:
+                  - "samsung,exynos4210-pmu" - for Exynos4210 and Exynos4x12 SoC,
                   - "samsung,exynos5250-pmu" - for Exynos5250 SoC,

Documentation/devicetree/bindings/arm/samsung/pmu.txt SAMSUNG Exynos SoC series PMU Registers · line 14

Quoted 10 lines
Documentation/devicetree/bindings/arm/samsung/pmu.txt +2 -2
-                  - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+                  - "samsung,exynos5420-pmu" - for Exynos5420 and Exynos5260 SoC.
                second value must be always "syscon".
 
  - reg : offset and length of the register set.
 
 Example :
 pmu_system_controller: system-controller at 10040000 {
-       compatible = "samsung,exynos5250-pmu", "syscon";
+       compatible = "samsung,exynos5250-pmu";

If you have removed "syscon" deliberately above, then you should also remove the same in the
binding description which says "second value must be always "syscon".".

Signature · 2 lines
With warm regards,
Sachin
#3 lore raw

PATCH v2 1/3 ARM: EXYNOS: Map PMU address through DT

Quoted 31 lines · Sachin Kamat

Hi Vikas,

Quoted 28 lines · Vikas Sajjan

Instead of hardcoding the PMU details for each SoC, pass this information through device tree (DT).

Signed-off-by Vikas Sajjan <[email protected]>
---
  .../devicetree/bindings/arm/samsung/pmu.txt        |    5 +-
  arch/arm/boot/dts/exynos4.dtsi                     |    5 ++
  arch/arm/boot/dts/exynos5260.dtsi                  |    5 ++
  arch/arm/mach-exynos/common.c                      |   51 +++++++++++++-------
  arch/arm/mach-exynos/include/mach/map.h            |    3 --
  5 files changed, 47 insertions(+), 22 deletions(-)
Documentation/devicetree/bindings/arm/samsung/pmu.txt +2 -1
index f1f1552..667a7f0 100644
@@ -2,14 +2,15 @@ SAMSUNG Exynos SoC series PMU Registers
 
  Properties:
   - compatible : should contain two values. First value must be one from following list:
+                  - "samsung,exynos4210-pmu" - for Exynos4210 and Exynos4x12 SoC,
                    - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
-                  - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+                  - "samsung,exynos5420-pmu" - for Exynos5420 and Exynos5260 SoC.
                 second value must be always "syscon".
 
   - reg : offset and length of the register set.
Quoted 9 lines

Documentation/devicetree/bindings/arm/samsung/pmu.txt SAMSUNG Exynos SoC series PMU Registers · line 14

Quoted 4 lines
Documentation/devicetree/bindings/arm/samsung/pmu.txt +1 -1
  Example :
  pmu_system_controller: system-controller at 10040000 {
-       compatible = "samsung,exynos5250-pmu", "syscon";
+       compatible = "samsung,exynos5250-pmu";

If you have removed "syscon" deliberately above, then you should also remove the same in the
binding description which says "second value must be always "syscon".".

I believe that "syscon" should be still present as I don't see any code providing access to PMU registers to other drivers, that could replace the standard syscon interface, being added by this series.

Best regards,
Tomasz

#4 lore raw

PATCH v2 1/3 ARM: EXYNOS: Map PMU address through DT

In reply to Vikas Sajjan

Hi Vikas,

Quoted 17 lines · Vikas Sajjan

Instead of hardcoding the PMU details for each SoC, pass this information through device tree (DT).

Signed-off-by Vikas Sajjan <[email protected]>
---
  .../devicetree/bindings/arm/samsung/pmu.txt        |    5 +-
  arch/arm/boot/dts/exynos4.dtsi                     |    5 ++
  arch/arm/boot/dts/exynos5260.dtsi                  |    5 ++
  arch/arm/mach-exynos/common.c                      |   51 +++++++++++++-------
  arch/arm/mach-exynos/include/mach/map.h            |    3 --
  5 files changed, 47 insertions(+), 22 deletions(-)
Documentation/devicetree/bindings/arm/samsung/pmu.txt +0 -0
index f1f1552..667a7f0 100644

Documentation/devicetree/bindings/arm/samsung/pmu.txt SAMSUNG Exynos SoC series PMU Registers · line 7

Quoted 7 lines
Documentation/devicetree/bindings/arm/samsung/pmu.txt +2 -1
@@ -2,14 +2,15 @@ SAMSUNG Exynos SoC series PMU Registers
 
  Properties:
   - compatible : should contain two values. First value must be one from following list:
+		   - "samsung,exynos4210-pmu" - for Exynos4210 and Exynos4x12 SoC,
  		   - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
-		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+		   - "samsung,exynos5420-pmu" - for Exynos5420 and Exynos5260 SoC.

Do Exynos5420 and 5260 really have identical PMU blocks with the same register layouts? If not, they should have different compatible strings.

Quoted 15 lines
Documentation/devicetree/bindings/arm/samsung/pmu.txt +1 -1
  		second value must be always "syscon".
 
   - reg : offset and length of the register set.
 
  Example :
  pmu_system_controller: system-controller at 10040000 {
-	compatible = "samsung,exynos5250-pmu", "syscon";
+	compatible = "samsung,exynos5250-pmu";
  	reg = <0x10040000 0x5000>;
  };
arch/arm/boot/dts/exynos4.dtsi +0 -0
index 08452e1..94cbafa 100644

arch/arm/boot/dts/exynos4.dtsi line 59

Quoted 5 lines
arch/arm/boot/dts/exynos4.dtsi +2 -0
@@ -55,6 +55,11 @@
  		#phy-cells = <1>;
  	};
 
+	pmu_system_controller: system-controller at 10020000 {
+		compatible = "samsung,exynos4210-pmu";

Missing "syscon" compatible string.

Quoted 11 lines
arch/arm/boot/dts/exynos4.dtsi +3 -0
+		reg = <0x10020000 0x4000>;
+	};
+
  	pd_mfc: mfc-power-domain at 10023C40 {
  		compatible = "samsung,exynos4210-pd";
  		reg = <0x10023C40 0x20>;
arch/arm/boot/dts/exynos5260.dtsi +0 -0
index a93fea8..2a4dace 100644

arch/arm/boot/dts/exynos5260.dtsi line 268

Quoted 5 lines
arch/arm/boot/dts/exynos5260.dtsi +2 -0
@@ -264,6 +264,11 @@
  			};
  		};
 
+		pmu_system_controller: system-controller at 10D50000 {
+			compatible = "samsung,exynos5420-pmu";

Missing "syscon" compatible string.

Quoted 102 lines
arch/arm/boot/dts/exynos5260.dtsi +3 -0
+			reg = <0x10D50000 0x5000>;
+		};
+
  		pinctrl_0: pinctrl at 11600000 {
  			compatible = "samsung,exynos5260-pinctrl";
  			reg = <0x11600000 0x1000>;
arch/arm/mach-exynos/common.c +33 -16
index 1df81ff..c75733b 100644
@@ -79,11 +79,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
  		.length		= SZ_4K,
  		.type		= MT_DEVICE,
  	}, {
-		.virtual	= (unsigned long)S5P_VA_PMU,
-		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE,
-	}, {
  		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
  		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
  		.length		= SZ_4K,

@@ -157,11 +152,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
  		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
  		.length		= 144 * SZ_1K,
  		.type		= MT_DEVICE,
-	}, {
-		.virtual	= (unsigned long)S5P_VA_PMU,
-		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE,
  	},
  };
 

@@ -243,12 +233,12 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  	return 1;
  }
 
-struct __sysram_desc {
+struct __exynos_reg_desc {
  	char name[32];
  	unsigned long addr;
  };
 
-static struct __sysram_desc sysram_desc[] __initdata = {
+static struct __exynos_reg_desc exynos_sysram_desc[] __initdata = {
  	{
  		.name = "samsung,exynos4210-sysram",
  		.addr = (unsigned long)S5P_VA_SYSRAM,

@@ -258,7 +248,20 @@ static struct __sysram_desc sysram_desc[] __initdata = {
  	},
  };
 
-static int __init exynos_fdt_map_sysram(unsigned long node, const char *uname,
+static struct __exynos_reg_desc exynos_pmu_desc[] __initdata = {
+	{
+		.name = "samsung,exynos4210-pmu",
+		.addr = (unsigned long)S5P_VA_PMU,
+	}, {
+		.name = "samsung,exynos5250-pmu",
+		.addr = (unsigned long)S5P_VA_PMU,
+	}, {
+		.name = "samsung,exynos5420-pmu",
+		.addr = (unsigned long)S5P_VA_PMU,
+	},
+};
+
+static int __init exynos_fdt_map_reg(unsigned long node, const char *uname,
  					int depth, void *data)
  {
  	struct map_desc iodesc;

@@ -266,12 +269,26 @@ static int __init exynos_fdt_map_sysram(unsigned long node, const char *uname,
  	unsigned long len;
  	int i;
 
-	for (i = 0; i < ARRAY_SIZE(sysram_desc); i++) {
-		if (of_flat_dt_is_compatible(node, sysram_desc[i].name)) {
+	for (i = 0; i < ARRAY_SIZE(exynos_sysram_desc); i++) {
+		if (of_flat_dt_is_compatible(node,
+					exynos_sysram_desc[i].name)) {
+			reg = of_get_flat_dt_prop(node, "reg", &len);
+			if (!reg || len != (sizeof(unsigned long) * 2))
+				return -ENODEV;
+			iodesc.virtual = exynos_sysram_desc[i].addr;
+			iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
+			iodesc.length = be32_to_cpu(reg[1]);
+			iodesc.type = MT_DEVICE;
+			iotable_init(&iodesc, 1);
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(exynos_pmu_desc); i++) {
+		if (of_flat_dt_is_compatible(node, exynos_pmu_desc[i].name)) {
  			reg = of_get_flat_dt_prop(node, "reg", &len);
  			if (!reg || len != (sizeof(unsigned long) * 2))
  				return -ENODEV;
-			iodesc.virtual = sysram_desc[i].addr;
+			iodesc.virtual = exynos_pmu_desc[i].addr;
  			iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
  			iodesc.length = be32_to_cpu(reg[1]);
  			iodesc.type = MT_DEVICE;

arch/arm/mach-exynos/common.c void __init exynos_init_io(void) · line 318

Quoted 5 lines
arch/arm/mach-exynos/common.c +1 -1
@@ -298,7 +315,7 @@ void __init exynos_init_io(void)
 
  	exynos_map_io();
 
-	of_scan_flat_dt(exynos_fdt_map_sysram, NULL);
+	of_scan_flat_dt(exynos_fdt_map_reg, NULL);

Do you really need to map PMU statically using iotable_init() at fixed virtual address? Shouldn't rather actual users of PMU registers bind to PMU node and use of_iomap()?

Best regards,
Tomasz

#5 lore raw

PATCH v2 1/3 ARM: EXYNOS: Map PMU address through DT

In reply to Vikas Sajjan

Hi Vikas,

As you comment, I found the history of this patch in mailing list. It seems like that this patch stop the review.

Besides, Pankaj posted same patch to support PMU as following:
- https://lkml.org/lkml/2014/4/2/48

Do you have a plan to resend or not?
because I need this patch to remove PMU static memory mapping for Exynos3250.

Best Regards,
Chanwoo Choi

Quoted 185 lines · Vikas Sajjan

Instead of hardcoding the PMU details for each SoC, pass this information through device tree (DT).

Signed-off-by Vikas Sajjan <[email protected]>
---
 .../devicetree/bindings/arm/samsung/pmu.txt        |    5 +-
 arch/arm/boot/dts/exynos4.dtsi                     |    5 ++
 arch/arm/boot/dts/exynos5260.dtsi                  |    5 ++
 arch/arm/mach-exynos/common.c                      |   51 +++++++++++++-------
 arch/arm/mach-exynos/include/mach/map.h            |    3 --
 5 files changed, 47 insertions(+), 22 deletions(-)
Documentation/devicetree/bindings/arm/samsung/pmu.txt +3 -2
index f1f1552..667a7f0 100644
@@ -2,14 +2,15 @@ SAMSUNG Exynos SoC series PMU Registers
 
 Properties:
  - compatible : should contain two values. First value must be one from following list:
+		   - "samsung,exynos4210-pmu" - for Exynos4210 and Exynos4x12 SoC,
 		   - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
-		   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+		   - "samsung,exynos5420-pmu" - for Exynos5420 and Exynos5260 SoC.
 		second value must be always "syscon".
 
  - reg : offset and length of the register set.
 
 Example :
 pmu_system_controller: system-controller@10040000 {
-	compatible = "samsung,exynos5250-pmu", "syscon";
+	compatible = "samsung,exynos5250-pmu";
 	reg = <0x10040000 0x5000>;
 };
arch/arm/boot/dts/exynos4.dtsi +5 -0
index 08452e1..94cbafa 100644
@@ -55,6 +55,11 @@
 		#phy-cells = <1>;
 	};
 
+	pmu_system_controller: system-controller@10020000 {
+		compatible = "samsung,exynos4210-pmu";
+		reg = <0x10020000 0x4000>;
+	};
+
 	pd_mfc: mfc-power-domain@10023C40 {
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x10023C40 0x20>;
arch/arm/boot/dts/exynos5260.dtsi +5 -0
index a93fea8..2a4dace 100644
@@ -264,6 +264,11 @@
 			};
 		};
 
+		pmu_system_controller: system-controller@10D50000 {
+			compatible = "samsung,exynos5420-pmu";
+			reg = <0x10D50000 0x5000>;
+		};
+
 		pinctrl_0: pinctrl@11600000 {
 			compatible = "samsung,exynos5260-pinctrl";
 			reg = <0x11600000 0x1000>;
arch/arm/mach-exynos/common.c +34 -17
index 1df81ff..c75733b 100644
@@ -79,11 +79,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= (unsigned long)S5P_VA_PMU,
-		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE,
-	}, {
 		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
 		.length		= SZ_4K,

@@ -157,11 +152,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
 		.length		= 144 * SZ_1K,
 		.type		= MT_DEVICE,
-	}, {
-		.virtual	= (unsigned long)S5P_VA_PMU,
-		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE,
 	},
 };
 

@@ -243,12 +233,12 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 	return 1;
 }
 
-struct __sysram_desc {
+struct __exynos_reg_desc {
 	char name[32];
 	unsigned long addr;
 };
 
-static struct __sysram_desc sysram_desc[] __initdata = {
+static struct __exynos_reg_desc exynos_sysram_desc[] __initdata = {
 	{
 		.name = "samsung,exynos4210-sysram",
 		.addr = (unsigned long)S5P_VA_SYSRAM,

@@ -258,7 +248,20 @@ static struct __sysram_desc sysram_desc[] __initdata = {
 	},
 };
 
-static int __init exynos_fdt_map_sysram(unsigned long node, const char *uname,
+static struct __exynos_reg_desc exynos_pmu_desc[] __initdata = {
+	{
+		.name = "samsung,exynos4210-pmu",
+		.addr = (unsigned long)S5P_VA_PMU,
+	}, {
+		.name = "samsung,exynos5250-pmu",
+		.addr = (unsigned long)S5P_VA_PMU,
+	}, {
+		.name = "samsung,exynos5420-pmu",
+		.addr = (unsigned long)S5P_VA_PMU,
+	},
+};
+
+static int __init exynos_fdt_map_reg(unsigned long node, const char *uname,
 					int depth, void *data)
 {
 	struct map_desc iodesc;

@@ -266,12 +269,26 @@ static int __init exynos_fdt_map_sysram(unsigned long node, const char *uname,
 	unsigned long len;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(sysram_desc); i++) {
-		if (of_flat_dt_is_compatible(node, sysram_desc[i].name)) {
+	for (i = 0; i < ARRAY_SIZE(exynos_sysram_desc); i++) {
+		if (of_flat_dt_is_compatible(node,
+					exynos_sysram_desc[i].name)) {
+			reg = of_get_flat_dt_prop(node, "reg", &len);
+			if (!reg || len != (sizeof(unsigned long) * 2))
+				return -ENODEV;
+			iodesc.virtual = exynos_sysram_desc[i].addr;
+			iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
+			iodesc.length = be32_to_cpu(reg[1]);
+			iodesc.type = MT_DEVICE;
+			iotable_init(&iodesc, 1);
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(exynos_pmu_desc); i++) {
+		if (of_flat_dt_is_compatible(node, exynos_pmu_desc[i].name)) {
 			reg = of_get_flat_dt_prop(node, "reg", &len);
 			if (!reg || len != (sizeof(unsigned long) * 2))
 				return -ENODEV;
-			iodesc.virtual = sysram_desc[i].addr;
+			iodesc.virtual = exynos_pmu_desc[i].addr;
 			iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 			iodesc.length = be32_to_cpu(reg[1]);
 			iodesc.type = MT_DEVICE;

@@ -298,7 +315,7 @@ void __init exynos_init_io(void)
 
 	exynos_map_io();
 
-	of_scan_flat_dt(exynos_fdt_map_sysram, NULL);
+	of_scan_flat_dt(exynos_fdt_map_reg, NULL);
 }
 
 static void __init exynos_map_io(void)
arch/arm/mach-exynos/include/mach/map.h +0 -3
index 548269a..34eee6e 100644
@@ -28,9 +28,6 @@
 #define EXYNOS4_PA_SYSCON		0x10010000
 #define EXYNOS5_PA_SYSCON		0x10050100
 
-#define EXYNOS4_PA_PMU			0x10020000
-#define EXYNOS5_PA_PMU			0x10040000
-
 #define EXYNOS4_PA_CMU			0x10030000
 #define EXYNOS5_PA_CMU			0x10010000
author
#6 lore raw

PATCH v2 2/3 ARM: EXYNOS: Add initial support of PMU for Exynos5260

In reply to Vikas Sajjan

Adds PMU support of PMU for Exynos5260. Suspend-to-RAM can be built on top this.

Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Vikas Sajjan <[email protected]>
---
 arch/arm/mach-exynos/common.h            |   26 ++++
 arch/arm/mach-exynos/pm.c                |   34 +++--
 arch/arm/mach-exynos/pmu.c               |  238 ++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h          |  232 +++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/cpu.h |    8 +
 5 files changed, 529 insertions(+), 9 deletions(-)
arch/arm/mach-exynos/common.h +26 -0
index aba6a2a..a17f701 100644
@@ -56,6 +56,32 @@ enum sys_powerdown {
 	NUM_SYS_POWERDOWN,
 };
 
+enum running_cpu {
+	EXYNOS5_KFC,
+	EXYNOS5_ARM,
+};
+
+enum reg_op {
+	REG_INIT,	/* write new value */
+	REG_RESET,	/* clear with zero */
+	REG_SET,	/* bit set */
+	REG_CLEAR,	/* bit clear */
+};
+
+/* reg/value set */
+#define EXYNOS_PMU_REG(REG, VAL, OP)		\
+{						\
+	.reg	=	(void __iomem *)REG,	\
+	.val	=	VAL,			\
+	.op	=	OP,			\
+}
+
+struct exynos_pmu_init_reg {
+	void __iomem *reg;
+	unsigned int val;
+	enum reg_op op;
+};
+
 extern unsigned long l2x0_regs_phys;
 struct exynos_pmu_conf {
 	void __iomem *reg;
arch/arm/mach-exynos/pm.c +25 -9
index 15af0ce..dbe9670 100644
@@ -109,7 +109,7 @@ static int exynos_cpu_suspend(unsigned long arg)
 	outer_flush_all();
 #endif
 
-	if (soc_is_exynos5250())
+	if (soc_is_exynos5250() || soc_is_exynos5260())
 		flush_cache_all();
 
 	/* issue the standby signal into the pm unit. */

@@ -150,6 +150,7 @@ static void exynos_pm_prepare(void)
 static int exynos_pm_suspend(void)
 {
 	unsigned long tmp;
+	unsigned int cluster_id;
 
 	/* Setting Central Sequence Register for power down mode */
 

@@ -158,11 +159,21 @@ static int exynos_pm_suspend(void)
 	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
 	/* Setting SEQ_OPTION register */
+	if (soc_is_exynos5250()) {
+		tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+	} else if (soc_is_exynos5260()) {
+		cluster_id = (read_cpuid(CPUID_MPIDR) >> 8) & 0xf;
+		if (!cluster_id)
+			__raw_writel(EXYNOS5260_ARM_USE_STANDBY_WFI0,
+				     S5P_CENTRAL_SEQ_OPTION);
+		else
+			__raw_writel(EXYNOS5260_KFC_USE_STANDBY_WFI0,
+				     S5P_CENTRAL_SEQ_OPTION);
 
-	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
-	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+	}
 
-	if (!soc_is_exynos5250()) {
+	if (!soc_is_exynos5250() && !soc_is_exynos5260()) {
 		/* Save Power control register */
 		asm ("mrc p15, 0, %0, c15, c0, 0"
 		     : "=r" (tmp) : : "cc");

@@ -196,7 +207,7 @@ static void exynos_pm_resume(void)
 		/* No need to perform below restore code */
 		goto early_wakeup;
 	}
-	if (!soc_is_exynos5250()) {
+	if (!soc_is_exynos5250() && !soc_is_exynos5260()) {
 		/* Restore Power control register */
 		tmp = save_arm_register[0];
 		asm volatile ("mcr p15, 0, %0, c15, c0, 0"

@@ -312,10 +323,15 @@ void __init exynos_pm_init(void)
 	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 
 	/* All wakeup disable */
-	tmp = __raw_readl(S5P_WAKEUP_MASK);
-	tmp |= ((0xFF << 8) | (0x1F << 1));
-	__raw_writel(tmp, S5P_WAKEUP_MASK);
-
+	if (soc_is_exynos5260()) {
+		tmp = __raw_readl(EXYNOS5260_WAKEUP_MASK);
+		tmp |= ((0xE << 12) | (0xE << 8) | (0x3 << 1));
+		__raw_writel(tmp, EXYNOS5260_WAKEUP_MASK);
+	} else {
+		tmp = __raw_readl(S5P_WAKEUP_MASK);
+		tmp |= ((0xFF << 8) | (0x1F << 1));
+		__raw_writel(tmp, S5P_WAKEUP_MASK);
+	}
 	register_syscore_ops(&exynos_pm_syscore_ops);
 	suspend_set_ops(&exynos_suspend_ops);
 }
arch/arm/mach-exynos/pmu.c +238 -0

268 lines not on this page · raw message

arch/arm/mach-exynos/regs-pmu.h +232 -0

245 lines not on this page · raw message

arch/arm/plat-samsung/include/plat/cpu.h +8 -0
index d762533..d8fd9ed 100644
@@ -49,6 +49,7 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4_CPU_MASK	0xFFFE0000
 
 #define EXYNOS5250_SOC_ID	0x43520000
+#define EXYNOS5260_SOC_ID	0xE5260000
 #define EXYNOS5420_SOC_ID	0xE5420000
 #define EXYNOS5440_SOC_ID	0xE5440000
 #define EXYNOS5_SOC_MASK	0xFFFFF000

@@ -72,6 +73,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 

@@ -154,6 +156,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5250()	0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5260)
+# define soc_is_exynos5260()	is_samsung_exynos5260()
+#else
+# define soc_is_exynos5260()	0
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5420)
 # define soc_is_exynos5420()	is_samsung_exynos5420()
 #else
Signature · 1 line
1.7.9.5
#7 lore raw

PATCH v2 2/3 ARM: EXYNOS: Add initial support of PMU for Exynos5260

Hi Vikas,

Quoted 55 lines · Vikas Sajjan

Adds PMU support of PMU for Exynos5260. Suspend-to-RAM can be built on top this.

Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Vikas Sajjan <[email protected]>
---
  arch/arm/mach-exynos/common.h            |   26 ++++
  arch/arm/mach-exynos/pm.c                |   34 +++--
  arch/arm/mach-exynos/pmu.c               |  238 ++++++++++++++++++++++++++++++
  arch/arm/mach-exynos/regs-pmu.h          |  232 +++++++++++++++++++++++++++++
  arch/arm/plat-samsung/include/plat/cpu.h |    8 +
  5 files changed, 529 insertions(+), 9 deletions(-)
arch/arm/mach-exynos/common.h +26 -0
index aba6a2a..a17f701 100644
@@ -56,6 +56,32 @@ enum sys_powerdown {
  	NUM_SYS_POWERDOWN,
  };
 
+enum running_cpu {
+	EXYNOS5_KFC,
+	EXYNOS5_ARM,
+};
+
+enum reg_op {
+	REG_INIT,	/* write new value */
+	REG_RESET,	/* clear with zero */
+	REG_SET,	/* bit set */
+	REG_CLEAR,	/* bit clear */
+};
+
+/* reg/value set */
+#define EXYNOS_PMU_REG(REG, VAL, OP)		\
+{						\
+	.reg	=	(void __iomem *)REG,	\
+	.val	=	VAL,			\
+	.op	=	OP,			\
+}
+
+struct exynos_pmu_init_reg {
+	void __iomem *reg;
+	unsigned int val;
+	enum reg_op op;
+};
+
  extern unsigned long l2x0_regs_phys;
  struct exynos_pmu_conf {
  	void __iomem *reg;
arch/arm/mach-exynos/pm.c +0 -0
index 15af0ce..dbe9670 100644

arch/arm/mach-exynos/pm.c static int exynos_cpu_suspend(unsigned long arg) · line 113

Quoted 6 lines
arch/arm/mach-exynos/pm.c +1 -1
@@ -109,7 +109,7 @@ static int exynos_cpu_suspend(unsigned long arg)
  	outer_flush_all();
  #endif
 
-	if (soc_is_exynos5250())
+	if (soc_is_exynos5250() || soc_is_exynos5260())
  		flush_cache_all();

I think it's the right time for this code to be restructured. Adding more and more SoCs over this cruft is making this code worse and worse.

I believe this should be done as follows:

- a generic struct describing particular PMU variant should be
defined, with things like

	bool flush_cache_on_suspend;
	struct exynos_pmu_conf *pmu_conf;

or even function pointers, like

	void (*cpu_suspend)(unsigned long arg);

to handle things done currently using soc_is_*() macros, which we should get rid of.

- a DT match table would bind particular compatible strings with respective PMU variants structs,

- in general, this code should be made more like a normal driver, e.g. bind to a DT node and map registers dynamically.

Best regards,
Tomasz

#8 lore raw

PATCH v2 2/3 ARM: EXYNOS: Add initial support of PMU for Exynos5260

Hi Tomasz,

Quoted 65 lines · Tomasz Figa

Hi Vikas,

Quoted 61 lines · Vikas Sajjan

Adds PMU support of PMU for Exynos5260. Suspend-to-RAM can be built on top this.

Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Vikas Sajjan <[email protected]>
---
  arch/arm/mach-exynos/common.h            |   26 ++++
  arch/arm/mach-exynos/pm.c                |   34 +++--
  arch/arm/mach-exynos/pmu.c               |  238
++++++++++++++++++++++++++++++
  arch/arm/mach-exynos/regs-pmu.h          |  232
+++++++++++++++++++++++++++++
  arch/arm/plat-samsung/include/plat/cpu.h |    8 +
  5 files changed, 529 insertions(+), 9 deletions(-)
arch/arm/mach-exynos/common.h +26 -0
index aba6a2a..a17f701 100644
@@ -56,6 +56,32 @@ enum sys_powerdown {
        NUM_SYS_POWERDOWN,
  };
 
+enum running_cpu {
+       EXYNOS5_KFC,
+       EXYNOS5_ARM,
+};
+
+enum reg_op {
+       REG_INIT,       /* write new value */
+       REG_RESET,      /* clear with zero */
+       REG_SET,        /* bit set */
+       REG_CLEAR,      /* bit clear */
+};
+
+/* reg/value set */
+#define EXYNOS_PMU_REG(REG, VAL, OP)           \
+{                                              \
+       .reg    =       (void __iomem *)REG,    \
+       .val    =       VAL,                    \
+       .op     =       OP,                     \
+}
+
+struct exynos_pmu_init_reg {
+       void __iomem *reg;
+       unsigned int val;
+       enum reg_op op;
+};
+
  extern unsigned long l2x0_regs_phys;
  struct exynos_pmu_conf {
        void __iomem *reg;
arch/arm/mach-exynos/pm.c +0 -0
index 15af0ce..dbe9670 100644
@@ -109,7 +109,7 @@ static int exynos_cpu_suspend(unsigned long arg)
        outer_flush_all();
  #endif
Quoted 8 lines

arch/arm/mach-exynos/pm.c static int exynos_cpu_suspend(unsigned long arg) · line 113

Quoted 3 lines
arch/arm/mach-exynos/pm.c +1 -1
-       if (soc_is_exynos5250())
+       if (soc_is_exynos5250() || soc_is_exynos5260())
                flush_cache_all();

I think it's the right time for this code to be restructured. Adding more and more SoCs over this cruft is making this code worse and worse.

I recently came across RFC [1] posted by pankaj on similar lines, did
you get a chance to have look at this series.

[1] https://lkml.org/lkml/2014/4/2/69

Quoted 28 lines

I believe this should be done as follows:

- a generic struct describing particular PMU variant should be defined,
with things like

        bool flush_cache_on_suspend;
        struct exynos_pmu_conf *pmu_conf;

or even function pointers, like

        void (*cpu_suspend)(unsigned long arg);

to handle things done currently using soc_is_*() macros, which we should get rid of.

- a DT match table would bind particular compatible strings with respective PMU variants structs,

- in general, this code should be made more like a normal driver, e.g. bind to a DT node and map registers dynamically.

Best regards,
Tomasz
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#9 lore raw

PATCH v2 2/3 ARM: EXYNOS: Add initial support of PMU for Exynos5260

Hi Vikas,

Quoted 77 lines · Vikas Sajjan

Hi Tomasz,

Quoted 65 lines · Tomasz Figa

Hi Vikas,

Quoted 61 lines · Vikas Sajjan

Adds PMU support of PMU for Exynos5260. Suspend-to-RAM can be built on top this.

Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Vikas Sajjan <[email protected]>
---
   arch/arm/mach-exynos/common.h            |   26 ++++
   arch/arm/mach-exynos/pm.c                |   34 +++--
   arch/arm/mach-exynos/pmu.c               |  238
++++++++++++++++++++++++++++++
   arch/arm/mach-exynos/regs-pmu.h          |  232
+++++++++++++++++++++++++++++
   arch/arm/plat-samsung/include/plat/cpu.h |    8 +
   5 files changed, 529 insertions(+), 9 deletions(-)
arch/arm/mach-exynos/common.h +26 -0
index aba6a2a..a17f701 100644
@@ -56,6 +56,32 @@ enum sys_powerdown {
         NUM_SYS_POWERDOWN,
   };
 
+enum running_cpu {
+       EXYNOS5_KFC,
+       EXYNOS5_ARM,
+};
+
+enum reg_op {
+       REG_INIT,       /* write new value */
+       REG_RESET,      /* clear with zero */
+       REG_SET,        /* bit set */
+       REG_CLEAR,      /* bit clear */
+};
+
+/* reg/value set */
+#define EXYNOS_PMU_REG(REG, VAL, OP)           \
+{                                              \
+       .reg    =       (void __iomem *)REG,    \
+       .val    =       VAL,                    \
+       .op     =       OP,                     \
+}
+
+struct exynos_pmu_init_reg {
+       void __iomem *reg;
+       unsigned int val;
+       enum reg_op op;
+};
+
   extern unsigned long l2x0_regs_phys;
   struct exynos_pmu_conf {
         void __iomem *reg;
arch/arm/mach-exynos/pm.c +0 -0
index 15af0ce..dbe9670 100644
@@ -109,7 +109,7 @@ static int exynos_cpu_suspend(unsigned long arg)
         outer_flush_all();
   #endif
Quoted 8 lines

arch/arm/mach-exynos/pm.c static int exynos_cpu_suspend(unsigned long arg) · line 113

Quoted 3 lines
arch/arm/mach-exynos/pm.c +1 -1
-       if (soc_is_exynos5250())
+       if (soc_is_exynos5250() || soc_is_exynos5260())
                 flush_cache_all();

I think it's the right time for this code to be restructured. Adding more and more SoCs over this cruft is making this code worse and worse.

Quoted 5 lines

I recently came across RFC [1] posted by pankaj on similar lines, did
you get a chance to have look at this series.

[1] https://lkml.org/lkml/2014/4/2/69

Right. I noticed it once, but didn't get to review it yet, as I'm a bit busy with other things right now. Will try to take a look in next days.

Best regards,
Tomasz

author
#10 lore raw

PATCH v2 3/3 arm: exynos5260: add support for S2R

In reply to Vikas Sajjan

Adds Suspend to RAM (S2R) support to exynos5260.

Signed-off-by Abhilash Kesavan <[email protected]>
Signed-off-by Vikas Sajjan <[email protected]>
---
 arch/arm/mach-exynos/pm.c       |   62 +++++++++++++++++++++++++++++++--------
 arch/arm/mach-exynos/regs-pmu.h |   12 ++++++++
 2 files changed, 61 insertions(+), 13 deletions(-)
arch/arm/mach-exynos/pm.c +49 -13
index dbe9670..12cc241 100644
@@ -77,12 +77,20 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
 	{ /* sentinel */ },
 };
 
+static const struct exynos_wkup_irq exynos5260_wkup_irq[] = {
+	{ 105, BIT(1) }, /* RTC alarm */
+	{ 106, BIT(2) }, /* RTC tick */
+	{ /* sentinel */ },
+};
+
 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 {
 	const struct exynos_wkup_irq *wkup_irq;
 
 	if (soc_is_exynos5250())
 		wkup_irq = exynos5250_wkup_irq;
+	else if (soc_is_exynos5260())
+		wkup_irq = exynos5260_wkup_irq;
 	else
 		wkup_irq = exynos4_wkup_irq;
 

@@ -124,10 +132,20 @@ static void exynos_pm_prepare(void)
 	unsigned int tmp;
 
 	/* Set wake-up mask registers */
-	__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
-	__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+	if (soc_is_exynos5260()) {
+		__raw_writel(exynos_get_eint_wake_mask(),
+					EXYNOS5260_EINT_WAKEUP_MASK);
+		__raw_writel(exynos_irqwake_intmask & ~(1 << 31),
+					EXYNOS5260_WAKEUP_MASK);
+	} else {
+		__raw_writel(exynos_get_eint_wake_mask(),
+					S5P_EINT_WAKEUP_MASK);
+		__raw_writel(exynos_irqwake_intmask & ~(1 << 31),
+					S5P_WAKEUP_MASK);
+	}
 
-	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+	if (!soc_is_exynos5260())
+		s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
 	if (soc_is_exynos5250()) {
 		s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));

@@ -221,21 +239,39 @@ static void exynos_pm_resume(void)
 			      : "cc");
 	}
 
-	/* For release retention */
-
-	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+	if (soc_is_exynos5250()) {
+		/* For release retention */
+
+		__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+	} else if (soc_is_exynos5260()) {
+		/* For release retention */
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_LPDDR3_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RET_MAUDIO_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RET_JTAG_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MMC2_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_TOP_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_UART_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MMC0_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MMC1_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_SPI_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MIF_OPTION);
+		__raw_writel((1 << 28),
+				EXYNOS5260_PAD_RETENTION_BOOTLDO_OPTION);
+	}
 
 	if (soc_is_exynos5250())
 		s3c_pm_do_restore(exynos5_sys_save,
 			ARRAY_SIZE(exynos5_sys_save));
 
-	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+	if (!soc_is_exynos5260())
+		s3c_pm_do_restore_core(exynos_core_save,
+				ARRAY_SIZE(exynos_core_save));
 
 	if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
 		scu_enable(S5P_VA_SCU);
arch/arm/mach-exynos/regs-pmu.h +12 -0
index a81926b..906dc1e 100644
@@ -532,6 +532,18 @@
 #define EXYNOS5260_EAGLE_L2_STATUS			S5P_PMUREG(0x2604)
 #define EXYNOS5260_KFC_L2_STATUS			S5P_PMUREG(0x2624)
 
+#define EXYNOS5260_PAD_RETENTION_LPDDR3_OPTION	S5P_PMUREG(0x3008)
+#define EXYNOS5260_PAD_RET_MAUDIO_OPTION	S5P_PMUREG(0x3028)
+#define EXYNOS5260_PAD_RET_JTAG_OPTION		S5P_PMUREG(0x3048)
+#define EXYNOS5260_PAD_RETENTION_MMC2_OPTION	S5P_PMUREG(0x30C8)
+#define EXYNOS5260_PAD_RETENTION_TOP_OPTION	S5P_PMUREG(0x3108)
+#define EXYNOS5260_PAD_RETENTION_UART_OPTION	S5P_PMUREG(0x3128)
+#define EXYNOS5260_PAD_RETENTION_MMC0_OPTION	S5P_PMUREG(0x3148)
+#define EXYNOS5260_PAD_RETENTION_MMC1_OPTION	S5P_PMUREG(0x3168)
+#define EXYNOS5260_PAD_RETENTION_SPI_OPTION	S5P_PMUREG(0x31C8)
+#define EXYNOS5260_PAD_RETENTION_MIF_OPTION	S5P_PMUREG(0x31E8)
+#define EXYNOS5260_PAD_RETENTION_BOOTLDO_OPTION	S5P_PMUREG(0x3248)
+
 /* CENTRAL_SEQ_OPTION */
 #define EXYNOS5260_ARM_USE_STANDBY_WFI0			(1 << 16)
 #define EXYNOS5260_ARM_USE_STANDBY_WFI1			(1 << 17)
Signature · 1 line
1.7.9.5
#11 lore raw

PATCH v2 3/3 arm: exynos5260: add support for S2R

Hi Vikas,

Quoted 23 lines · Vikas Sajjan

Adds Suspend to RAM (S2R) support to exynos5260.

Signed-off-by Abhilash Kesavan <[email protected]>
Signed-off-by Vikas Sajjan <[email protected]>
---
  arch/arm/mach-exynos/pm.c       |   62 +++++++++++++++++++++++++++++++--------
  arch/arm/mach-exynos/regs-pmu.h |   12 ++++++++
  2 files changed, 61 insertions(+), 13 deletions(-)
arch/arm/mach-exynos/pm.c +6 -0
index dbe9670..12cc241 100644
@@ -77,12 +77,20 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  	{ /* sentinel */ },
  };
 
+static const struct exynos_wkup_irq exynos5260_wkup_irq[] = {
+	{ 105, BIT(1) }, /* RTC alarm */
+	{ 106, BIT(2) }, /* RTC tick */
+	{ /* sentinel */ },
+};
+

arch/arm/mach-exynos/pm.c static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { · line 95

Quoted 10 lines
arch/arm/mach-exynos/pm.c +2 -0
  static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
  {
  	const struct exynos_wkup_irq *wkup_irq;
 
  	if (soc_is_exynos5250())
  		wkup_irq = exynos5250_wkup_irq;
+	else if (soc_is_exynos5260())
+		wkup_irq = exynos5260_wkup_irq;
  	else
  		wkup_irq = exynos4_wkup_irq;

This should probably be tied to some DT match table as match data for particular compatible strings. Also to eliminate the need to add such change for every new SoC, the mapping between wake-up sources and GIC interrupts should be probably parsed from DT.

Adding some people on CC for further comments.

Quoted 8 lines
arch/arm/mach-exynos/pm.c +1 -2
@@ -124,10 +132,20 @@ static void exynos_pm_prepare(void)
  	unsigned int tmp;
 
  	/* Set wake-up mask registers */
-	__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
-	__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+	if (soc_is_exynos5260()) {

arch/arm/mach-exynos/pm.c static void exynos_pm_prepare(void) · line 145

Quoted 10 lines
arch/arm/mach-exynos/pm.c +10 -0
+		__raw_writel(exynos_get_eint_wake_mask(),
+					EXYNOS5260_EINT_WAKEUP_MASK);
+		__raw_writel(exynos_irqwake_intmask & ~(1 << 31),
+					EXYNOS5260_WAKEUP_MASK);
+	} else {
+		__raw_writel(exynos_get_eint_wake_mask(),
+					S5P_EINT_WAKEUP_MASK);
+		__raw_writel(exynos_irqwake_intmask & ~(1 << 31),
+					S5P_WAKEUP_MASK);
+	}

Same here. I wonder what we could do to eliminate the need for such changes.

By the way, don't you need to handle here EXYNOS5260_WAKEUP_MASK2 and EXYNOS5260_WAKEUP_MASK3 as well?

arch/arm/mach-exynos/pm.c static void exynos_pm_prepare(void) · line 148

Quoted 4 lines
arch/arm/mach-exynos/pm.c +2 -1
-	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+	if (!soc_is_exynos5260())
+		s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));

Ugly.

Quoted 32 lines
arch/arm/mach-exynos/pm.c +16 -9
  	if (soc_is_exynos5250()) {
  		s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));

@@ -221,21 +239,39 @@ static void exynos_pm_resume(void)
  			      : "cc");
  	}
 
-	/* For release retention */
-
-	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
-	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+	if (soc_is_exynos5250()) {
+		/* For release retention */
+
+		__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+		__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+	} else if (soc_is_exynos5260()) {
+		/* For release retention */
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_LPDDR3_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RET_MAUDIO_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RET_JTAG_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MMC2_OPTION);

arch/arm/mach-exynos/pm.c static void exynos_pm_resume(void) · line 267

Quoted 10 lines
arch/arm/mach-exynos/pm.c +9 -0
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_TOP_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_UART_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MMC0_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MMC1_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_SPI_OPTION);
+		__raw_writel((1 << 28), EXYNOS5260_PAD_RETENTION_MIF_OPTION);
+		__raw_writel((1 << 28),
+				EXYNOS5260_PAD_RETENTION_BOOTLDO_OPTION);
+	}

Ugly.

arch/arm/mach-exynos/pm.c static void exynos_pm_resume(void) · line 274

Quoted 8 lines
arch/arm/mach-exynos/pm.c +3 -1
  	if (soc_is_exynos5250())
  		s3c_pm_do_restore(exynos5_sys_save,
  			ARRAY_SIZE(exynos5_sys_save));
 
-	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+	if (!soc_is_exynos5260())
+		s3c_pm_do_restore_core(exynos_core_save,
+				ARRAY_SIZE(exynos_core_save));

Ugly.

I believe that exactly the same comments apply to this file as mentioned in my review of patch 2/3 for pmu.c. The code needs to be reworked to let us remove soc_is_exynos*() macros.

Best regards,
Tomasz

#12 lore raw

v2 cover Add initial support of PMU for exynos5260

In reply to Vikas Sajjan

Hi,

Any comments on this series.

Quoted 49 lines · Vikas Sajjan

From: Vikas Sajjan <[email protected]>

1) Added initial PMU support for exynos5260

2) Added S2R(single CPU) support on exynos5260

3) Added PMU mapping via DT.

rebased on
1) kgene tree for-next branch
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

2) Rahul's patches for basic support of exynos5260
http://www.spinics.net/lists/linux-samsung-soc/msg27282.html

3) Rahul's clk patches http://www.spinics.net/lists/linux-samsung-soc/msg27275.html

4) Tomasz Figa's http://permalink.gmane.org/gmane.linux.ports.arm.kernel/299340

Changes since v1:
-- Addressed Tomasz Figa's comments. -- removed CMU patch
-- Added PMU mapping via DT

Vikas Sajjan (3):
ARM: EXYNOS: Map PMU address through DT
ARM: EXYNOS: Add initial support of PMU for Exynos5260
arm: exynos5260: add support for S2R

 .../devicetree/bindings/arm/samsung/pmu.txt        |    5 +-
 arch/arm/boot/dts/exynos4.dtsi                     |    5 +
 arch/arm/boot/dts/exynos5260.dtsi                  |    5 +
 arch/arm/mach-exynos/common.c                      |   51 ++--
 arch/arm/mach-exynos/common.h                      |   26 +++
 arch/arm/mach-exynos/include/mach/map.h            |    3 -
 arch/arm/mach-exynos/pm.c                          |   96 ++++++--
 arch/arm/mach-exynos/pmu.c                         |  238 +++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h                    |  244 ++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/cpu.h           |    8 +
 10 files changed, 637 insertions(+), 44 deletions(-)

--
1.7.9.5

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