Exynos5: Add GPIO numbering feature
Subsystems (3)
v8 cover Exynos5: Add GPIO numbering feature
Did ./MAKEALL -a arm and found all Exynos/S5P related boards compiled successfully.
Couldn't test booting over all of them.
Tested U-Boot bootup over SMDK5420, SMDK5250, Snow. Requesting maintaners to test once over affected SoCs/boards.
Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass
and supported same for EXYNOS5.
Changes in V3:
- New patch added to rename S5P GPIO definitions
to S5P_GPIO.
- GPIO Table added to calculate the base address
of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver.
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Rebased on latest u-boot-samsung tree.
- Removed Exynos5 specific code in gpio driver api to get bank.
- Added #define HAVE_GENERIC_GPIO in config file
to remove conditinal CPU check in gpio driver.
Changes in V6:
- Isolated config changes in a new patch.
- Updated patches with corresponding changes for Exynos 5420.
Changes in V7:
- Added changes for other SoCs like Exynos 4412, 4210 etc.
Changes in V8:
- Changed Subject of patch 2/2 to reflect affected SoCs/boards.
- Fixed arndale board compile time errors introduced due to patch-set v7.
Akshay Saraswat (2):
S5P: Exynos: Add GPIO pin numbering and rename definitions
S5P: Exynos: Config: Enable Generic GPIO and CMD configs
arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++---- arch/arm/include/asm/arch-exynos/cpu.h | 17 +- arch/arm/include/asm/arch-exynos/gpio.h | 1778 +++++++++++++++++++++++++----- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +++++++++++++--- board/samsung/arndale/arndale.c | 11 +- board/samsung/goni/goni.c | 26 +- board/samsung/smdk5250/exynos5-dt.c | 20 +- board/samsung/smdk5250/smdk5250.c | 19 +- board/samsung/smdk5420/smdk5420.c | 15 +- board/samsung/smdkc100/smdkc100.c | 5 +- board/samsung/smdkv310/smdkv310.c | 17 +- board/samsung/trats/trats.c | 39 +- board/samsung/trats2/trats2.c | 74 +- board/samsung/universal_c210/universal.c | 51 +- drivers/gpio/s5p_gpio.c | 194 +++- include/configs/arndale.h | 1 + include/configs/exynos5-dt.h | 3 + include/configs/origen.h | 1 + include/configs/s5p_goni.h | 5 +- include/configs/s5pc210_universal.h | 17 +- include/configs/smdkc100.h | 1 + include/configs/smdkv310.h | 2 + include/configs/trats.h | 9 +- include/configs/trats2.h | 5 +- 24 files changed, 2807 insertions(+), 847 deletions(-)
Signature · 1 line
1.8.3.2
PATCH v8 1/2 S5P: Exynos: Add GPIO pin numbering and rename definitions
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
* Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation.
* Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00
Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
--- arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++---- arch/arm/include/asm/arch-exynos/cpu.h | 17 +- arch/arm/include/asm/arch-exynos/gpio.h | 1778 +++++++++++++++++++++++++----- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +++++++++++++--- board/samsung/arndale/arndale.c | 11 +- board/samsung/goni/goni.c | 26 +- board/samsung/smdk5250/exynos5-dt.c | 20 +- board/samsung/smdk5250/smdk5250.c | 19 +- board/samsung/smdk5420/smdk5420.c | 15 +- board/samsung/smdkc100/smdkc100.c | 5 +- board/samsung/smdkv310/smdkv310.c | 17 +- board/samsung/trats/trats.c | 39 +- board/samsung/trats2/trats2.c | 74 +- board/samsung/universal_c210/universal.c | 51 +- drivers/gpio/s5p_gpio.c | 194 +++- 15 files changed, 2779 insertions(+), 831 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +168 -235
@@ -13,30 +13,23 @@static void exynos5_uart_config (int peripheral) { -struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1 (); -struct s5p_gpio_bank *bank;int i, start, count;switch (peripheral) {case PERIPH_ID_UART0 : - bank = &gpio1->a0; - start =0 ; + start =EXYNOS5_GPIO_A00 ; count =4 ;break ;case PERIPH_ID_UART1 : - bank = &gpio1->d0; - start =0 ; + start =EXYNOS5_GPIO_D00 ; count =4 ;break ;case PERIPH_ID_UART2 : - bank = &gpio1->a1; - start =0 ; + start =EXYNOS5_GPIO_A10 ; count =4 ;break ;case PERIPH_ID_UART3 : - bank = &gpio1->a1; - start =4 ; + start =EXYNOS5_GPIO_A14 ; count =2 ;break ;default :
@@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral)return ; }for (i = start; i < start + count; i++) { -s5p_gpio_set_pull (bank, i,GPIO_PULL_NONE ); -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_NONE ); +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); } }static void exynos5420_uart_config (int peripheral) { -struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1 (); -struct s5p_gpio_bank *bank;int i, start, count;switch (peripheral) {case PERIPH_ID_UART0 : - bank = &gpio1->a0; - start =0 ; + start =EXYNOS5420_GPIO_A00 ; count =4 ;break ;case PERIPH_ID_UART1 : - bank = &gpio1->a0; - start =4 ; + start =EXYNOS5420_GPIO_A04 ; count =4 ;break ;case PERIPH_ID_UART2 : - bank = &gpio1->a1; - start =0 ; + start =EXYNOS5420_GPIO_A10 ; count =4 ;break ;case PERIPH_ID_UART3 : - bank = &gpio1->a1; - start =4 ; + start =EXYNOS5420_GPIO_A14 ; count =2 ;break ;default :
@@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral) }for (i = start; i < start + count; i++) { -s5p_gpio_set_pull (bank, i,GPIO_PULL_NONE ); -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_NONE ); +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); } }static int exynos5_mmc_config (int peripheral,int flags) { -struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1 (); -struct s5p_gpio_bank *bank, *bank_ext; -int i, start =0 , gpio_func =0 ; +int i, start, start_ext, gpio_func =0 ;switch (peripheral) {case PERIPH_ID_SDMMC0 : - bank = &gpio1->c0; - bank_ext = &gpio1->c1; - start =0 ; - gpio_func =GPIO_FUNC (0x2 ); + start =EXYNOS5_GPIO_C00 ; + start_ext =EXYNOS5_GPIO_C10 ; + gpio_func =S5P_GPIO_FUNC (0x2 );break ;case PERIPH_ID_SDMMC1 : - bank = &gpio1->c2; - bank_ext =NULL ; + start =EXYNOS5_GPIO_C20 ; + start_ext =0 ;break ;case PERIPH_ID_SDMMC2 : - bank = &gpio1->c3; - bank_ext = &gpio1->c4; - start =3 ; - gpio_func =GPIO_FUNC (0x3 ); + start =EXYNOS5_GPIO_C30 ; + start_ext =EXYNOS5_GPIO_C43 ; + gpio_func =S5P_GPIO_FUNC (0x3 );break ;case PERIPH_ID_SDMMC3 : - bank = &gpio1->c4; - bank_ext =NULL ; + start =EXYNOS5_GPIO_C40 ; + start_ext =0 ;break ;default :debug ("%s: invalid peripheral %d" , __func__, peripheral);return -1 ; } -if ((flags &PINMUX_FLAG_8BIT_MODE ) && !bank_ext) { +if ((flags &PINMUX_FLAG_8BIT_MODE ) && !start_ext) {debug ("SDMMC device %d does not support 8bit mode" , peripheral);return -1 ; }if (flags &PINMUX_FLAG_8BIT_MODE ) { -for (i = start; i <= (start +3 ); i++) { -s5p_gpio_cfg_pin (bank_ext, i, gpio_func); -s5p_gpio_set_pull (bank_ext, i,GPIO_PULL_UP ); -s5p_gpio_set_drv (bank_ext, i,GPIO_DRV_4X ); +for (i = start_ext; i <= (start_ext +3 ); i++) { +gpio_cfg_pin (i, gpio_func); +gpio_set_pull (i,S5P_GPIO_PULL_UP ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); } } -for (i =0 ; i <2 ; i++) { -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); -s5p_gpio_set_pull (bank, i,GPIO_PULL_NONE ); -s5p_gpio_set_drv (bank, i,GPIO_DRV_4X ); +for (i = start; i < (start +2 ); i++) { +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_NONE ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); } -for (i =3 ; i <=6 ; i++) { -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); -s5p_gpio_set_pull (bank, i,GPIO_PULL_UP ); -s5p_gpio_set_drv (bank, i,GPIO_DRV_4X ); +for (i = (start +3 ); i <= (start +6 ); i++) { +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_UP ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); }return 0 ;
@@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags)static int exynos5420_mmc_config (int peripheral,int flags) { -struct exynos5420_gpio_part3 *gpio3 = - (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3 (); -struct s5p_gpio_bank *bank =NULL , *bank_ext =NULL ; -int i, start; +int i, start =0 , start_ext =0 ;switch (peripheral) {case PERIPH_ID_SDMMC0 : - bank = &gpio3->c0; - bank_ext = &gpio3->c3; - start =0 ; + start =EXYNOS5420_GPIO_C00 ; + start_ext =EXYNOS5420_GPIO_C30 ;break ;case PERIPH_ID_SDMMC1 : - bank = &gpio3->c1; - bank_ext = &gpio3->d1; - start =4 ; + start =EXYNOS5420_GPIO_C10 ; + start_ext =EXYNOS5420_GPIO_D14 ;break ;case PERIPH_ID_SDMMC2 : - bank = &gpio3->c2; - bank_ext =NULL ; - start =0 ; + start =EXYNOS5420_GPIO_C20 ; + start_ext =0 ;break ;default : start =0 ;
@@ -175,21 +150,21 @@ static int exynos5420_mmc_config(int peripheral, int flags)return -1 ; } -if ((flags &PINMUX_FLAG_8BIT_MODE ) && !bank_ext) { +if ((flags &PINMUX_FLAG_8BIT_MODE ) && !start_ext) {debug ("SDMMC device %d does not support 8bit mode" , peripheral);return -1 ; }if (flags &PINMUX_FLAG_8BIT_MODE ) { -for (i = start; i <= (start +3 ); i++) { -s5p_gpio_cfg_pin (bank_ext, i,GPIO_FUNC (0x2 )); -s5p_gpio_set_pull (bank_ext, i,GPIO_PULL_UP ); -s5p_gpio_set_drv (bank_ext, i,GPIO_DRV_4X ); +for (i = start_ext; i <= (start_ext +3 ); i++) { +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_UP ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); } } -for (i =0 ; i <3 ; i++) { +for (i = start; i < (start +3 ); i++) {/* * MMC0 is intended to be used for eMMC. The * card detect pin is used as a VDDEN signal to
@@ -197,19 +172,19 @@ static int exynos5420_mmc_config(int peripheral, int flags)* this same assumption. */ if ((peripheral ==PERIPH_ID_SDMMC0 ) && (i ==2 )) { -s5p_gpio_set_value (bank, i,1 ); -s5p_gpio_cfg_pin (bank, i,GPIO_OUTPUT ); +gpio_set_value (i,1 ); +gpio_cfg_pin (i,S5P_GPIO_OUTPUT ); }else { -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); } -s5p_gpio_set_pull (bank, i,GPIO_PULL_NONE ); -s5p_gpio_set_drv (bank, i,GPIO_DRV_4X ); +gpio_set_pull (i,S5P_GPIO_PULL_NONE ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); } -for (i =3 ; i <=6 ; i++) { -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); -s5p_gpio_set_pull (bank, i,GPIO_PULL_UP ); -s5p_gpio_set_drv (bank, i,GPIO_DRV_4X ); +for (i = (start +3 ); i <= (start +6 ); i++) { +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_UP ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); }return 0 ;
@@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags)static void exynos5_sromc_config (int flags) { -struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1 ();int i;/*
@@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags)* GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ -s5p_gpio_cfg_pin (&gpio1->y0, (flags &PINMUX_FLAG_BANK ), -GPIO_FUNC (2 )); -s5p_gpio_cfg_pin (&gpio1->y0,4 ,GPIO_FUNC (2 )); -s5p_gpio_cfg_pin (&gpio1->y0,5 ,GPIO_FUNC (2 )); +gpio_cfg_pin (EXYNOS5_GPIO_Y00 + (flags &PINMUX_FLAG_BANK ), +S5P_GPIO_FUNC (2 )); +gpio_cfg_pin (EXYNOS5_GPIO_Y04 ,S5P_GPIO_FUNC (2 )); +gpio_cfg_pin (EXYNOS5_GPIO_Y05 ,S5P_GPIO_FUNC (2 ));for (i =0 ; i <4 ; i++) -s5p_gpio_cfg_pin (&gpio1->y1, i,GPIO_FUNC (2 )); +gpio_cfg_pin (EXYNOS5_GPIO_Y10 + i,S5P_GPIO_FUNC (2 ));/* * EBI: 8 Addrss Lines
@@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags)* GPY6[7] EBI_DATA[15](2) */ for (i =0 ; i <8 ; i++) { -s5p_gpio_cfg_pin (&gpio1->y3, i,GPIO_FUNC (2 )); -s5p_gpio_set_pull (&gpio1->y3, i,GPIO_PULL_UP ); +gpio_cfg_pin (EXYNOS5_GPIO_Y30 + i,S5P_GPIO_FUNC (2 )); +gpio_set_pull (EXYNOS5_GPIO_Y30 + i,S5P_GPIO_PULL_UP ); -s5p_gpio_cfg_pin (&gpio1->y5, i,GPIO_FUNC (2 )); -s5p_gpio_set_pull (&gpio1->y5, i,GPIO_PULL_UP ); +gpio_cfg_pin (EXYNOS5_GPIO_Y50 + i,S5P_GPIO_FUNC (2 )); +gpio_set_pull (EXYNOS5_GPIO_Y50 + i,S5P_GPIO_PULL_UP ); -s5p_gpio_cfg_pin (&gpio1->y6, i,GPIO_FUNC (2 )); -s5p_gpio_set_pull (&gpio1->y6, i,GPIO_PULL_UP ); +gpio_cfg_pin (EXYNOS5_GPIO_Y60 + i,S5P_GPIO_FUNC (2 )); +gpio_set_pull (EXYNOS5_GPIO_Y60 + i,S5P_GPIO_PULL_UP ); } }static void exynos5_i2c_config (int peripheral,int flags) { - -struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1 (); -switch (peripheral) {case PERIPH_ID_I2C0 : -s5p_gpio_cfg_pin (&gpio1->b3,0 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->b3,1 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5_GPIO_B30 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5_GPIO_B31 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C1 : -s5p_gpio_cfg_pin (&gpio1->b3,2 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->b3,3 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5_GPIO_B32 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5_GPIO_B33 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C2 : -s5p_gpio_cfg_pin (&gpio1->a0,6 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a0,7 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A06 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A07 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C3 : -s5p_gpio_cfg_pin (&gpio1->a1,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a1,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A12 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A13 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C4 : -s5p_gpio_cfg_pin (&gpio1->a2,0 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a2,1 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A20 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A21 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C5 : -s5p_gpio_cfg_pin (&gpio1->a2,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a2,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A22 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_A23 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C6 : -s5p_gpio_cfg_pin (&gpio1->b1,3 ,GPIO_FUNC (0x4 )); -s5p_gpio_cfg_pin (&gpio1->b1,4 ,GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5_GPIO_B13 ,S5P_GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5_GPIO_B14 ,S5P_GPIO_FUNC (0x4 ));break ;case PERIPH_ID_I2C7 : -s5p_gpio_cfg_pin (&gpio1->b2,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->b2,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_B22 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5_GPIO_B23 ,S5P_GPIO_FUNC (0x3 ));break ; } }static void exynos5420_i2c_config (int peripheral) { -struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1 (); -switch (peripheral) {case PERIPH_ID_I2C0 : -s5p_gpio_cfg_pin (&gpio1->b3,0 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->b3,1 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B30 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B31 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C1 : -s5p_gpio_cfg_pin (&gpio1->b3,2 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->b3,3 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B32 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B33 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C2 : -s5p_gpio_cfg_pin (&gpio1->a0,6 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a0,7 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A06 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A07 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C3 : -s5p_gpio_cfg_pin (&gpio1->a1,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a1,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A12 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A13 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C4 : -s5p_gpio_cfg_pin (&gpio1->a2,0 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a2,1 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A20 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A21 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C5 : -s5p_gpio_cfg_pin (&gpio1->a2,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a2,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A22 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_A23 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C6 : -s5p_gpio_cfg_pin (&gpio1->b1,3 ,GPIO_FUNC (0x4 )); -s5p_gpio_cfg_pin (&gpio1->b1,4 ,GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B13 ,S5P_GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B14 ,S5P_GPIO_FUNC (0x4 ));break ;case PERIPH_ID_I2C7 : -s5p_gpio_cfg_pin (&gpio1->b2,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->b2,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B22 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B23 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C8 : -s5p_gpio_cfg_pin (&gpio1->b3,4 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->b3,5 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B34 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B35 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C9 : -s5p_gpio_cfg_pin (&gpio1->b3,6 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->b3,7 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B36 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B37 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C10 : -s5p_gpio_cfg_pin (&gpio1->b4,0 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->b4,1 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B40 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS5420_GPIO_B41 ,S5P_GPIO_FUNC (0x2 ));break ; } }
@@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral)static void exynos5_i2s_config (int peripheral) {int i; -struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1 (); -struct exynos5_gpio_part4 *gpio4 = - (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4 ();switch (peripheral) {case PERIPH_ID_I2S0 :for (i =0 ; i <5 ; i++) -s5p_gpio_cfg_pin (&gpio4->z, i,GPIO_FUNC (0x02 )); +gpio_cfg_pin (EXYNOS5_GPIO_Z0 +i,S5P_GPIO_FUNC (0x02 ));break ;case PERIPH_ID_I2S1 :for (i =0 ; i <5 ; i++) -s5p_gpio_cfg_pin (&gpio1->b0, i,GPIO_FUNC (0x02 )); +gpio_cfg_pin (EXYNOS5_GPIO_B00 +i,S5P_GPIO_FUNC (0x02 ));break ; } }
@@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral)void exynos5_spi_config (int peripheral) {int cfg =0 , pin =0 , i; -struct s5p_gpio_bank *bank =NULL ; -struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1 (); -struct exynos5_gpio_part2 *gpio2 = - (struct exynos5_gpio_part2 *)samsung_get_base_gpio_part2 ();switch (peripheral) {case PERIPH_ID_SPI0 : - bank = &gpio1->a2; - cfg =GPIO_FUNC (0x2 ); - pin =0 ; + cfg =S5P_GPIO_FUNC (0x2 ); + pin =EXYNOS5_GPIO_A20 ;break ;case PERIPH_ID_SPI1 : - bank = &gpio1->a2; - cfg =GPIO_FUNC (0x2 ); - pin =4 ; + cfg =S5P_GPIO_FUNC (0x2 ); + pin =EXYNOS5_GPIO_A24 ;break ;case PERIPH_ID_SPI2 : - bank = &gpio1->b1; - cfg =GPIO_FUNC (0x5 ); - pin =1 ; + cfg =S5P_GPIO_FUNC (0x5 ); + pin =EXYNOS5_GPIO_B11 ;break ;case PERIPH_ID_SPI3 : - bank = &gpio2->f1; - cfg =GPIO_FUNC (0x2 ); - pin =0 ; + cfg =S5P_GPIO_FUNC (0x2 ); + pin =EXYNOS5_GPIO_F10 ;break ;case PERIPH_ID_SPI4 :for (i =0 ; i <2 ; i++) { -s5p_gpio_cfg_pin (&gpio2->f0, i +2 ,GPIO_FUNC (0x4 )); -s5p_gpio_cfg_pin (&gpio2->e0, i +4 ,GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5_GPIO_F02 + i,S5P_GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5_GPIO_E04 + i,S5P_GPIO_FUNC (0x4 )); }break ; }if (peripheral !=PERIPH_ID_SPI4 ) {for (i = pin; i < pin +4 ; i++) -s5p_gpio_cfg_pin (bank, i, cfg); +gpio_cfg_pin (i, cfg); } }void exynos5420_spi_config (int peripheral) {int cfg, pin, i; -struct s5p_gpio_bank *bank =NULL ; -struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1 (); -struct exynos5420_gpio_part4 *gpio4 = - (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4 ();switch (peripheral) {case PERIPH_ID_SPI0 : - bank = &gpio1->a2; - cfg =GPIO_FUNC (0x2 ); - pin =0 ; + pin =EXYNOS5420_GPIO_A20 ; + cfg =S5P_GPIO_FUNC (0x2 );break ;case PERIPH_ID_SPI1 : - bank = &gpio1->a2; - cfg =GPIO_FUNC (0x2 ); - pin =4 ; + pin =EXYNOS5420_GPIO_A24 ; + cfg =S5P_GPIO_FUNC (0x2 );break ;case PERIPH_ID_SPI2 : - bank = &gpio1->b1; - cfg =GPIO_FUNC (0x5 ); - pin =1 ; + pin =EXYNOS5420_GPIO_B11 ; + cfg =S5P_GPIO_FUNC (0x5 );break ;case PERIPH_ID_SPI3 : - bank = &gpio4->f1; - cfg =GPIO_FUNC (0x2 ); - pin =0 ; + pin =EXYNOS5420_GPIO_F10 ; + cfg =S5P_GPIO_FUNC (0x2 );break ;case PERIPH_ID_SPI4 : cfg =0 ;
@@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral)if (peripheral !=PERIPH_ID_SPI4 ) {for (i = pin; i < pin +4 ; i++) -s5p_gpio_cfg_pin (bank, i, cfg); +gpio_cfg_pin (i, cfg); }else {for (i =0 ; i <2 ; i++) { -s5p_gpio_cfg_pin (&gpio4->f0, i +2 ,GPIO_FUNC (0x4 )); -s5p_gpio_cfg_pin (&gpio4->e0, i +4 ,GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5420_GPIO_F02 + i, +S5P_GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS5420_GPIO_E04 + i, +S5P_GPIO_FUNC (0x4 )); } } }
@@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags)static void exynos4_i2c_config (int peripheral,int flags) { -struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1 (); -switch (peripheral) {case PERIPH_ID_I2C0 : -s5p_gpio_cfg_pin (&gpio1->d1,0 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->d1,1 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS4_GPIO_D10 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS4_GPIO_D11 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C1 : -s5p_gpio_cfg_pin (&gpio1->d1,2 ,GPIO_FUNC (0x2 )); -s5p_gpio_cfg_pin (&gpio1->d1,3 ,GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS4_GPIO_D12 ,S5P_GPIO_FUNC (0x2 )); +gpio_cfg_pin (EXYNOS4_GPIO_D13 ,S5P_GPIO_FUNC (0x2 ));break ;case PERIPH_ID_I2C2 : -s5p_gpio_cfg_pin (&gpio1->a0,6 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a0,7 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_A06 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_A07 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C3 : -s5p_gpio_cfg_pin (&gpio1->a1,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->a1,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_A12 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_A13 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C4 : -s5p_gpio_cfg_pin (&gpio1->b,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->b,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_B2 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_B3 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C5 : -s5p_gpio_cfg_pin (&gpio1->b,6 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->b,7 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_B6 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_B7 ,S5P_GPIO_FUNC (0x3 ));break ;case PERIPH_ID_I2C6 : -s5p_gpio_cfg_pin (&gpio1->c1,3 ,GPIO_FUNC (0x4 )); -s5p_gpio_cfg_pin (&gpio1->c1,4 ,GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS4_GPIO_C13 ,S5P_GPIO_FUNC (0x4 )); +gpio_cfg_pin (EXYNOS4_GPIO_C14 ,S5P_GPIO_FUNC (0x4 ));break ;case PERIPH_ID_I2C7 : -s5p_gpio_cfg_pin (&gpio1->d0,2 ,GPIO_FUNC (0x3 )); -s5p_gpio_cfg_pin (&gpio1->d0,3 ,GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_D02 ,S5P_GPIO_FUNC (0x3 )); +gpio_cfg_pin (EXYNOS4_GPIO_D03 ,S5P_GPIO_FUNC (0x3 ));break ; } }static int exynos4_mmc_config (int peripheral,int flags) { -struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2 (); -struct s5p_gpio_bank *bank, *bank_ext; -int i; +int i, start =0 , start_ext =0 ;switch (peripheral) {case PERIPH_ID_SDMMC0 : - bank = &gpio2->k0; - bank_ext = &gpio2->k1; + start =EXYNOS4_GPIO_K00 ; + start_ext =EXYNOS4_GPIO_K13 ;break ;case PERIPH_ID_SDMMC2 : - bank = &gpio2->k2; - bank_ext = &gpio2->k3; + start =EXYNOS4_GPIO_K20 ; + start_ext =EXYNOS4_GPIO_K33 ;break ;default :return -1 ; } -for (i =0 ; i <7 ; i++) { +for (i = start; i < (start +7 ); i++) {if (i ==2 )continue ; -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); -s5p_gpio_set_pull (bank, i,GPIO_PULL_NONE ); -s5p_gpio_set_drv (bank, i,GPIO_DRV_4X ); +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_NONE ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); }if (flags &PINMUX_FLAG_8BIT_MODE ) { -for (i =3 ; i <7 ; i++) { -s5p_gpio_cfg_pin (bank_ext, i,GPIO_FUNC (0x3 )); -s5p_gpio_set_pull (bank_ext, i,GPIO_PULL_NONE ); -s5p_gpio_set_drv (bank_ext, i,GPIO_DRV_4X ); +for (i = start_ext; i < (start_ext +4 ); i++) { +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x3 )); +gpio_set_pull (i,S5P_GPIO_PULL_NONE ); +gpio_set_drv (i,S5P_GPIO_DRV_4X ); } }
@@ -666,30 +606,23 @@ static int exynos4_mmc_config(int peripheral, int flags)static void exynos4_uart_config (int peripheral) { -struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1 (); -struct s5p_gpio_bank *bank;int i, start, count;switch (peripheral) {case PERIPH_ID_UART0 : - bank = &gpio1->a0; - start =0 ; + start =EXYNOS4_GPIO_A00 ; count =4 ;break ;case PERIPH_ID_UART1 : - bank = &gpio1->a0; - start =4 ; + start =EXYNOS4_GPIO_A04 ; count =4 ;break ;case PERIPH_ID_UART2 : - bank = &gpio1->a1; - start =0 ; + start =EXYNOS4_GPIO_A10 ; count =4 ;break ;case PERIPH_ID_UART3 : - bank = &gpio1->a1; - start =4 ; + start =EXYNOS4_GPIO_A14 ; count =2 ;break ;default :
@@ -697,8 +630,8 @@ static void exynos4_uart_config(int peripheral)return ; }for (i = start; i < start + count; i++) { -s5p_gpio_set_pull (bank, i,GPIO_PULL_NONE ); -s5p_gpio_cfg_pin (bank, i,GPIO_FUNC (0x2 )); +gpio_set_pull (i,S5P_GPIO_PULL_NONE ); +gpio_cfg_pin (i,S5P_GPIO_FUNC (0x2 )); } }static int exynos4_pinmux_config (int peripheral,int flags)
arch/arm/include/asm/arch-exynos/cpu.h +11 -6
@@ -98,7 +98,7 @@#define EXYNOS5_I2C_SPACING 0x10000#define EXYNOS5_AUDIOSS_BASE 0x03810000 -#define EXYNOS5_GPIO_PART4_BASE 0x03860000 +#define EXYNOS5_GPIO_PART8_BASE 0x03860000#define EXYNOS5_PRO_ID 0x10000000#define EXYNOS5_CLOCK_BASE 0x10010000#define EXYNOS5_POWER_BASE 0x10040000
@@ -108,9 +108,13 @@#define EXYNOS5_WATCHDOG_BASE 0x101D0000#define EXYNOS5_ACE_SFR_BASE 0x10830000#define EXYNOS5_DMC_PHY_BASE 0x10C00000 -#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART5_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART6_BASE 0x10D10060 +#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000#define EXYNOS5_GPIO_PART1_BASE 0x11400000 +#define EXYNOS5_GPIO_PART2_BASE 0x114002E0 +#define EXYNOS5_GPIO_PART3_BASE 0x11400C00#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000#define EXYNOS5_USB3PHY_BASE 0x12100000
@@ -125,7 +129,7 @@#define EXYNOS5_I2S_BASE 0x12D60000#define EXYNOS5_PWMTIMER_BASE 0x12DD0000#define EXYNOS5_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5_GPIO_PART4_BASE 0x13400000#define EXYNOS5_FIMD_BASE 0x14400000#define EXYNOS5_DP_BASE 0x145B0000
@@ -135,7 +139,7 @@/* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 +#define EXYNOS5420_GPIO_PART6_BASE 0x03860000#define EXYNOS5420_PRO_ID 0x10000000#define EXYNOS5420_CLOCK_BASE 0x10010000#define EXYNOS5420_POWER_BASE 0x10040000
@@ -158,8 +162,9 @@#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000#define EXYNOS5420_SPI_ISP_BASE 0x131A0000#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART4_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 +#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART5_BASE 0x14000000#define EXYNOS5420_GPIO_PART1_BASE 0x14010000#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000#define EXYNOS5420_DP_BASE 0x145B0000
arch/arm/include/asm/arch-exynos/gpio.h +1509 -269
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arch/arm/include/asm/arch-s5pc1xx/gpio.h +815 -126
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board/samsung/trats2/trats2.c +30 -44
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board/samsung/universal_c210/universal.c +23 -28
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drivers/gpio/s5p_gpio.c +168 -26
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Signature · 1 line
1.8.3.2
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PATCH v8 1/2 S5P: Exynos: Add GPIO pin numbering and rename definitions
Hi, Akshay.
Did you test exynos4 board?
I have tested your patch-set with the exynos4 board(TRATS2). It didn't work.
Occurred DATA_ABORT.gpio_set_pull(EXYNOS4x12_GPIO_X15,...);
Add the comment at below.
Quoted 41 lines · Akshay Saraswat
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.* Rename GPIO definitions from
GPIO_... toS5P_GPIO_... These changes were done to enablecmd_gpiofor EXYNOS andcmd_gpiohasGPIO_INPUTsame ass5p_gpiodriver and hence getting a error during compilation.* Adds support for name to gpio conversion in
s5p_gpioto enable gpio command EXYNOS SoCs. Function has been added toasm/gpio.hto decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00Signed-off-by Leela Krishna Amudala <[email protected]>Signed-off-by Rajeshwari Shinde <[email protected]>Signed-off-by Akshay Saraswat <[email protected]>--- arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++---- arch/arm/include/asm/arch-exynos/cpu.h | 17 +- arch/arm/include/asm/arch-exynos/gpio.h | 1778 +++++++++++++++++++++++++----- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +++++++++++++--- board/samsung/arndale/arndale.c | 11 +- board/samsung/goni/goni.c | 26 +- board/samsung/smdk5250/exynos5-dt.c | 20 +- board/samsung/smdk5250/smdk5250.c | 19 +- board/samsung/smdk5420/smdk5420.c | 15 +- board/samsung/smdkc100/smdkc100.c | 5 +- board/samsung/smdkv310/smdkv310.c | 17 +- board/samsung/trats/trats.c | 39 +- board/samsung/trats2/trats2.c | 74 +- board/samsung/universal_c210/universal.c | 51 +- drivers/gpio/s5p_gpio.c | 194 +++- 15 files changed, 2779 insertions(+), 831 deletions(-)arch/arm/cpu/armv7/exynos/pinmux.c +0
-0@@ -13,30 +13,23 @@
[..snip..]
arch/arm/cpu/armv7/exynos/pinmux.c unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); · line 32
Quoted 10 lines
arch/arm/cpu/armv7/exynos/pinmux.c +2
-1- +#if 0 /* functions */ void s5p_gpio_cfg_pin (struct s5p_gpio_bank *bank,int gpio,int cfg);void s5p_gpio_direction_output (struct s5p_gpio_bank *bank,int gpio,int en);@@ -244,6 +29,7 @@ unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);void s5p_gpio_set_pull (struct s5p_gpio_bank *bank,int gpio,int mode);void s5p_gpio_set_drv (struct s5p_gpio_bank *bank,int gpio,int mode);void s5p_gpio_set_rate (struct s5p_gpio_bank *bank,int gpio,int mode); +#endif
Why did you use the "#if 0 ~ #endif".
If it didn't need to use, it can be removed, isn't?
Best Regards,
Jaehoon Chung
PATCH v8 1/2 S5P: Exynos: Add GPIO pin numbering and rename definitions
In reply to Akshay SaraswatHello Akshay,
Quoted 27 lines · Akshay Saraswat
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.* Rename GPIO definitions from
GPIO_... toS5P_GPIO_... These changes were done to enablecmd_gpiofor EXYNOS andcmd_gpiohasGPIO_INPUTsame ass5p_gpiodriver and hence getting a error during compilation.* Adds support for name to gpio conversion in
s5p_gpioto enable gpio command EXYNOS SoCs. Function has been added toasm/gpio.hto decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00Signed-off-by Leela Krishna Amudala <[email protected]>Signed-off-by Rajeshwari Shinde <[email protected]>Signed-off-by Akshay Saraswat <[email protected]>--- arch/arm/cpu/armv7/exynos/pinmux.c | 403 +++---- arch/arm/include/asm/arch-exynos/cpu.h | 17 +- arch/arm/include/asm/arch-exynos/gpio.h | 1778 +++++++++++++++++++++++++----- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 941 +++++++++++++--- board/samsung/arndale/arndale.c | 11 +- board/samsung/goni/goni.c | 26 +- board/samsung/smdk5250/exynos5-dt.c | 20 +- board/samsung/smdk5250/smdk5250.c | 19 +-
Quoted 10 lines
board/samsung/smdk5420/smdk5420.c | 15 +- board/samsung/smdkc100/smdkc100.c | 5 +- board/samsung/smdkv310/smdkv310.c | 17 +- board/samsung/trats/trats.c | 39 +- board/samsung/trats2/trats2.c | 74 +- board/samsung/universal_c210/universal.c | 51 +- drivers/gpio/s5p_gpio.c | 194 +++- 15 files changed, 2779 insertions(+), 831 deletions(-)
You introduced new method for gpio numbering and I don't know why are you using macro like this:
"exynos_gpio_get(2, EXYNOS4X12_GPIO_X33)"
and also new style like only "EXYNOS4X12_GPIO_X33".
Those are two different numbers and can't be given to s5p_gpio driver which interprets only new gpio numbering method.
This code can't work properly.
Please remove old macros and use only proper gpio enum in boards config files.
We don't need any "get" macro if all gpio numbers are defined explicitly.
You should also modify proper dts files in arch/arm/dts/* .
I tested your changes with enums only and after change proper dts file for trats2 there is still data abort.
So this means that probably enums are not mapped correctly to proper gpio bank addresses.
Do you have an documentation for Exynos4 socs?
I think that this should be checked again with documentation and compiled next to the current code which is simple and just works.
There are also some warnings when checking by checkpatch script.
Thanks
Signature · 4 lines
Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak at samsung.com
PATCH v8 2/2 S5P: Exynos: Config: Enable Generic GPIO and CMD configs
In reply to Akshay SaraswatEnabling configs for GPIO CMD and Generic GPIO in case of S5P and Exynos target boards.
Also, doing modifications in the config definitions wherever required due to change in gpio macros pin numbering enums.
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
--- include/configs/arndale.h | 1 + include/configs/exynos5-dt.h | 3 +++ include/configs/origen.h | 1 + include/configs/s5p_goni.h | 5 +++-- include/configs/s5pc210_universal.h | 17 +++++++++-------- include/configs/smdkc100.h | 1 + include/configs/smdkv310.h | 2 ++ include/configs/trats.h | 9 +++++---- include/configs/trats2.h | 5 +++-- 9 files changed, 28 insertions(+), 16 deletions(-)
include/configs/arndale.h +1 -0
@@ -249,4 +249,5 @@/* Enable Time Command */ #define CONFIG_CMD_TIME +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
include/configs/exynos5-dt.h +3 -0
@@ -288,4 +288,7 @@#define CONFIG_CMD_BOOTZ +#define HAVE_GENERIC_GPIO +#define CONFIG_CMD_GPIO +#endif /* __CONFIG_H */
include/configs/origen.h +1 -0
@@ -95,4 +95,5 @@#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
include/configs/s5p_goni.h +3 -2
@@ -214,8 +214,8 @@/* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL s5p_gpio_get(S5PC110_GPIO_J43) +#define CONFIG_SOFT_I2C_GPIO_SDA s5p_gpio_get(S5PC110_GPIO_J40)#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
@@ -227,4 +227,5 @@#define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
include/configs/s5pc210_universal.h +9 -8
@@ -170,8 +170,8 @@/* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos_gpio_get(1, EXYNOS4_GPIO_B7) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos_gpio_get(1, EXYNOS4_GPIO_B6)#define CONFIG_CMD_I2C
@@ -196,10 +196,10 @@*/ #define CONFIG_SOFT_SPI #define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3) +#define CONFIG_SOFT_SPI_GPIO_SCLK exynos_gpio_get(2, EXYNOS4_GPIO_Y31) +#define CONFIG_SOFT_SPI_GPIO_MOSI exynos_gpio_get(2, EXYNOS4_GPIO_Y33) +#define CONFIG_SOFT_SPI_GPIO_MISO exynos_gpio_get(2, EXYNOS4_GPIO_Y30) +#define CONFIG_SOFT_SPI_GPIO_CS exynos_gpio_get(2, EXYNOS4_GPIO_Y43)#define SPI_DELAY udelay(1)#undef SPI_INIT
@@ -231,8 +231,8 @@ int universal_spi_read(void);#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1#define KEY_PWR_INTERRUPT_MASK (1 << 7) -#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) -#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#define KEY_VOL_UP_GPIO exynos_gpio_get(2, EXYNOS4_GPIO_X20) +#define KEY_VOL_DOWN_GPIO exynos_gpio_get(2, EXYNOS4_GPIO_X21)#endif /* __ASSEMBLY__ */ /* LCD console */
@@ -253,4 +253,5 @@ int universal_spi_read(void);#define LCD_XRES 480#define LCD_YRES 800 +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
include/configs/smdkc100.h +1 -0
@@ -217,4 +217,5 @@#define CONFIG_ENV_SROM_BANK 3/* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */ +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
include/configs/smdkv310.h +2 -0
@@ -12,6 +12,7 @@/* High Level Configuration Options */ #define CONFIG_SAMSUNG 1/* in a SAMSUNG core */ #define CONFIG_S5P 1/* S5P Family */ +#define CONFIG_EXYNOS4 /* EXYNOS4 Family */ #define CONFIG_EXYNOS4210 1/* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1/* working with SMDKV310*/
@@ -148,4 +149,5 @@/* Enable devicetree support */ #define CONFIG_OF_LIBFDT +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
include/configs/trats.h +5 -4
@@ -207,8 +207,8 @@#define CONFIG_SYS_I2C_INIT_BOARD /* I2C FG */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos_gpio_get(2, EXYNOS4_GPIO_Y41) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos_gpio_get(2, EXYNOS4_GPIO_Y40)/* POWER */ #define CONFIG_POWER
@@ -245,8 +245,8 @@#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1#define KEY_PWR_INTERRUPT_MASK (1 << 0) -#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) -#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#define KEY_VOL_UP_GPIO exynos_gpio_get(2, EXYNOS4_GPIO_X20) +#define KEY_VOL_DOWN_GPIO exynos_gpio_get(2, EXYNOS4_GPIO_X21)#endif /* __ASSEMBLY__ */ /* LCD console */
@@ -267,4 +267,5 @@#define LCD_XRES 720#define LCD_YRES 1280 +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
include/configs/trats2.h +3 -2
@@ -227,8 +227,8 @@ int get_soft_i2c_sda_pin(void);#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1#define KEY_PWR_INTERRUPT_MASK (1 << 1) -#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) -#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) +#define KEY_VOL_UP_GPIO exynos_gpio_get(2, EXYNOS4X12_GPIO_X22) +#define KEY_VOL_DOWN_GPIO exynos_gpio_get(2, EXYNOS4X12_GPIO_X33)#endif /* __ASSEMBLY__ */ /* LCD console */
@@ -249,4 +249,5 @@ int get_soft_i2c_sda_pin(void);#define LCD_XRES 720#define LCD_YRES 1280 +#define HAVE_GENERIC_GPIO #endif /* __CONFIG_H */
Signature · 1 line
1.8.3.2