ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
Subsystems (6)
v8 cover ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzend?rfer and I have been working on.
The first 2 patches are depenencies which should go in through the clk tree, Mike can you pick these 2 up please ? :
"clk: sunxi: factors: automatic reparenting support"
Is uncontroversial and has been favorably reviewed by various people.
"clk: sunxi: Implement MMC phase control"
Is somewhat more controversial as there has been lots of discussion about adding a generic phase control method to the clk framework. The problem is that there has been a lot of talk about such a generic phase control method but not a single patch. Therefor I would like to move forwards with using a platform specific method for now. I hereby promise that once we've a generic method I'll write patches to convert the sunxi code to that method.
The third patch is the patch adding the actual mmc driver and should go in through the mmc tree.
All the other patches are devicetree patches hooking things up, and should go upstream through Maxime's sunxi-dt tree.
Changes since v1:
-Using mmc_of_parse instead of diy dt parsing -Adding nodes for all mmc controller to the dtsi files,
including sofar unused controllers
-Using generic GPIO slot library for WP/CD -Adding additional MMC device nodes into DTSI files
Changes since v2:
-Add missing Signed-off-by tags
-Stop using __raw_readl / __raw_writel so that barriers are properly used -Adding missing new lines
-Adding missing patch for automatic reparenting of clocks
Changes since v3:
-Move clk_enable / disable into host_init / exit (Hans) -Fix hang on boot caused by irq storm (Hans)
Changes since v4:
-moving sunxi-mci.{c/h} to sunxi-mmc.{c/h} -removing camel cases from the defines in sunxi-mmc.h -moving defines out of the struct definition
since this is bad coding style
-adding documentation for the device tree binding Changes since v5:
-adding host initialization for when the sdio irq is enabled
(just to make sure having a defined state at all time)
-add mmc support fixup: set pullup on cd pins -fixup: Don't set MMC_CAP_NEEDS_POLL / MMC_CAP_4_BIT_DATA
Changes since v6:
-fixing copyright info in sunxi-mmc.*
-s/__SUNXI_MCI_H__/__SUNXI_MMC_H__/g
-s/SDXC_RESPONSE_/SDXC_RESP_/g
-s/define/definitions <- Comment from Priit Laes
Changes since v7:
-Merge sunxi-mmc.h into sunxi-mmc.c
-Various style fixes / cleanups based on Maxime's review
-sun6i support
-Fix a race condition in interrupt / tasklet interaction
-Split the dts patches into 3 per platform:
1) Add mmc nodes to the dtsi
2) Add mmc pinmux to the dtsi
3) Add mmc nodes to the various board files
-Moved setting of bus-width and cd gpio polarity from .dtsi to the board-files -Added sun6i dts patches
Regards,
Hans
PATCH v8 1/17 clk: sunxi: factors: automatic reparenting support
From: Emilio L?pez <[email protected]>
This commit implements .determine_rate, so that our factor clocks can be reparented when needed.
--- drivers/clk/sunxi/clk-factors.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
drivers/clk/sunxi/clk-factors.c +36 -0
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,return rate; } +static long clk_factors_determine_rate (struct clk_hw *hw,unsigned long rate, +unsigned long *best_parent_rate, +struct clk **best_parent_p) +{ +struct clk *clk = hw->clk, *parent, *best_parent =NULL ; +int i, num_parents; +unsigned long parent_rate, best =0 , child_rate, best_child_rate =0 ; + +/* find the parent that can help provide the fastest rate <= rate */ + num_parents =__clk_get_num_parents (clk); +for (i =0 ; i < num_parents; i++) { + parent =clk_get_parent_by_index (clk, i); +if (!parent) +continue ; +if (__clk_get_flags (clk) &CLK_SET_RATE_PARENT ) + parent_rate =__clk_round_rate (parent, rate); +else + parent_rate =__clk_get_rate (parent); + + child_rate =clk_factors_round_rate (hw, rate, &parent_rate); + +if (child_rate <= rate && child_rate > best_child_rate) { + best_parent = parent; + best = parent_rate; + best_child_rate = child_rate; + } + } + +if (best_parent) + *best_parent_p = best_parent; + *best_parent_rate = best; + +return best_child_rate; +} +static int clk_factors_set_rate (struct clk_hw *hw,unsigned long rate,unsigned long parent_rate) {
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate, }const struct clk_ops clk_factors_ops = { + .determine_rate = clk_factors_determine_rate, .recalc_rate = clk_factors_recalc_rate, .round_rate = clk_factors_round_rate, .set_rate = clk_factors_set_rate,
Signature · 1 line
1.9.0
PATCH v8 2/17 clk: sunxi: Implement MMC phase control
In reply to Hans de GoedeFrom: Emilio L?pez <[email protected]>
HdG: add header exporting clk_sunxi_mmc_phase_control
--- drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++ include/linux/clk/sunxi.h | 22 ++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 include/linux/clk/sunxi.h
drivers/clk/sunxi/clk-sunxi.c +35 -0
@@ -507,6 +507,41 @@ CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",/** +* clk_sunxi_mmc_phase_control() - configures MMC clock phase control +*/ + +void clk_sunxi_mmc_phase_control (struct clk_hw *hw,u8 sample,u8 output) +{ +#define to_clk_composite (_hw) container_of(_hw, struct clk_composite, hw) +#define to_clk_factors (_hw) container_of(_hw, struct clk_factors, hw) + +struct clk_composite *composite =to_clk_composite (hw); +struct clk_hw *rate_hw = composite->rate_hw; +struct clk_factors *factors =to_clk_factors (rate_hw); +unsigned long flags =0 ; +u32 reg; + +if (factors->lock) +spin_lock_irqsave (factors->lock, flags); + + reg =readl (factors->reg); + +/* set sample clock phase control */ + reg &= ~(0x7 <<20 ); + reg |= ((sample &0x7 ) <<20 ); + +/* set output clock phase control */ + reg &= ~(0x7 <<8 ); + reg |= ((output &0x7 ) <<8 ); + +writel (reg, factors->reg); + +if (factors->lock) +spin_unlock_irqrestore (factors->lock, flags); +} + + +/** * sunxi_factors_clk_setup() - Setup function for factor clocks */
include/linux/clk/sunxi.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copyright 2013 - Hans de Goede <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __LINUX_CLK_SUNXI_H_ +#define __LINUX_CLK_SUNXI_H_ + +#include <linux/clk.h> + +void clk_sunxi_mmc_phase_control (struct clk_hw *hw,u8 sample,u8 output); + +#endif
Signature · 1 line
1.9.0
PATCH v8 3/17 ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
In reply to Hans de GoedeFrom: David Lanzend??rfer <[email protected]>
The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices.
HdG: Various cleanups and fixes.
--- .../devicetree/bindings/mmc/sunxi-mmc.txt | 43 + drivers/mmc/host/Kconfig | 7 + drivers/mmc/host/Makefile | 2 + drivers/mmc/host/sunxi-mmc.c | 1126 ++++++++++++++++++++ 4 files changed, 1178 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt create mode 100644 drivers/mmc/host/sunxi-mmc.c
Documentation/devicetree/bindings/mmc/sunxi-mmc.txt new file +43 -0
@@ -0,0 +1,43 @@ +* Allwinner sunxi MMC controller + +The highspeed MMC host controller on Allwinner SoCs provides an interface +for MMC, SD and SDIO types of memory cards. + +Supported maximum speeds are the ones of the eMMC standard 4.5 as well +as the speed of SD standard 3.0. +Absolute maximum transfer rate is 200MB/s + +Required properties: + - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc" + - reg : mmc controller base registers + - clocks : a list with 2 phandle + clock specifier pairs + - clock-names : must contain "ahb" and "mod" + - interrupts : mmc controller interrupt + +Optional properties: + - resets : phandle + reset specifier pair + - reset-names : must contain "ahb" + - for cd, bus-width and additional generic mmc parameters + please refer to mmc.txt within this directory + +Examples: + - Within .dtsi: + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <0 32 4>; + status = "disabled"; + }; + + - Within dts: + mmc0: mmc at 01c0f000 { + pinctrl-names = "default", "default"; + pinctrl-0 = <&mmc0_pins_a>; + pinctrl-1 = <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + };
drivers/mmc/host/Kconfig +7 -0
@@ -694,3 +694,10 @@ config MMC_REALTEK_PCI help Say Y here to include driver code to support SD/MMC card interface of Realtek PCI-E card reader + +config MMC_SUNXI + tristate "Allwinner sunxi SD/MMC Host Controller support" + depends on ARCH_SUNXI + help + This selects support for the SD/MMC Host Controller on + Allwinner sunxi SoCs.
drivers/mmc/host/Makefile +2 -0
@@ -53,6 +53,8 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o +obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o + obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
drivers/mmc/host/sunxi-mmc.c new file +1126 -0
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Signature · 1 line
1.9.0
PATCH v8 4/17 ARM: dts: sun4i: Add mmc controller nodes
In reply to Hans de GoedeFrom: David Lanzend?rfer <[email protected]>
Add nodes for the 4 mmc controllers found on A10 SoCs to arch/arm/boot/dts/sun4i-a10.dtsi.
--- arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
arch/arm/boot/dts/sun4i-a10.dtsi +36 -0
@@ -377,6 +377,42 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc at 01c10000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mod"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + interrupts = <34>; + status = "disabled"; + }; + + mmc3: mmc at 01c12000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mod"; + interrupts = <35>; + status = "disabled"; + }; + usbphy: phy at 01c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy";
Signature · 1 line
1.9.0
PATCH v8 5/17 ARM: dts: sun4i: Add pin-muxing info for the mmc0 controller
In reply to Hans de Goedemmc0 is the only controller actually being used on boards, so limit the pin-muxing options to that.
--- arch/arm/boot/dts/sun4i-a10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/sun4i-a10.dtsi +14 -0
@@ -565,6 +565,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0 at 0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_a: mmc0_cd_pin at 0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; }; timer at 01c20c00 {
Signature · 1 line
1.9.0
PATCH v8 6/17 ARM: dts: sun4i: Enable mmc controller on various A10 boards
In reply to Hans de GoedeTested on a subset of these boards, for the others boards the settings match the ones of the tested boards according to the original firmware fex files.
--- arch/arm/boot/dts/sun4i-a10-a1000.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-hackberry.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-pcduino.dts | 9 +++++++++ 7 files changed, 63 insertions(+)
arch/arm/boot/dts/sun4i-a10-a1000.dts +9 -0
@@ -36,6 +36,15 @@ }; }; + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
arch/arm/boot/dts/sun4i-a10-cubieboard.dts +9 -0
@@ -34,6 +34,15 @@ }; }; + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
arch/arm/boot/dts/sun4i-a10-hackberry.dts +9 -0
@@ -36,6 +36,15 @@ }; }; + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +9 -0
@@ -24,6 +24,15 @@ }; soc at 01c00000 { + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + uart0: serial at 01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>;
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +9 -0
@@ -20,6 +20,15 @@ compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; soc at 01c00000 { + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +9 -0
@@ -33,6 +33,15 @@ }; }; + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
arch/arm/boot/dts/sun4i-a10-pcduino.dts +9 -0
@@ -34,6 +34,15 @@ }; }; + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
Signature · 1 line
1.9.0
PATCH v8 7/17 ARM: dts: sun5i: Add mmc controller nodes
In reply to Hans de GoedeFrom: David Lanzend?rfer <[email protected]>
Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc controllers found on A13 SoCs.
--- arch/arm/boot/dts/sun5i-a10s.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 18 ++++++++++++++++++ 2 files changed, 45 insertions(+)
arch/arm/boot/dts/sun5i-a10s.dtsi +27 -0
@@ -338,6 +338,33 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc at 01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mod"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy at 01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy";
arch/arm/boot/dts/sun5i-a13.dtsi +18 -0
@@ -320,6 +320,24 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <32>; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy at 01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy";
Signature · 1 line
1.9.0
PATCH v8 7/17 ARM: dts: sun5i: Add mmc controller nodes
Quoted 66 lines · Hans de Goede
From: David Lanzend?rfer <[email protected]>
Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc controllers found on A13 SoCs.
Signed-off-by David Lanzend?rfer <[email protected]>Signed-off-by Hans de Goede <[email protected]>--- arch/arm/boot/dts/sun5i-a10s.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 18 ++++++++++++++++++ 2 files changed, 45 insertions(+)arch/arm/boot/dts/sun5i-a10s.dtsi +27
-0@@ -338,6 +338,33 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc at 01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mod"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy at 01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy";arch/arm/boot/dts/sun5i-a13.dtsi +8
-0@@ -320,6 +320,24 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <32>; + status = "disabled"; + };
arch/arm/boot/dts/sun5i-a13.dtsi line 340
Quoted 10 lines
arch/arm/boot/dts/sun5i-a13.dtsi +10
-0+ + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + interrupts = <34>; + status = "disabled"; + }; +
The A13 user manual reports that there is 3 of them in the A13, just like on the A10s. Have you forgotten one?
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140423/adabe2e0/attachment.sig>
[linux-sunxi] Re: [PATCH v8 07/17] ARM: dts: sun5i: Add mmc controller nodes
Hi,
Quoted 72 lines · Maxime Ripard
Quoted 71 lines · Hans de Goede
From: David Lanzend?rfer <[email protected]>
Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc controllers found on A13 SoCs.
Signed-off-by David Lanzend?rfer <[email protected]>Signed-off-by Hans de Goede <[email protected]>--- arch/arm/boot/dts/sun5i-a10s.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 18 ++++++++++++++++++ 2 files changed, 45 insertions(+)arch/arm/boot/dts/sun5i-a10s.dtsi +27
-0@@ -338,6 +338,33 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc at 01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mod"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy at 01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy";arch/arm/boot/dts/sun5i-a13.dtsi +13
-0@@ -320,6 +320,24 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <32>; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>;
Quoted 8 lines
arch/arm/boot/dts/sun5i-a13.dtsi line 340
Quoted 5 lines
arch/arm/boot/dts/sun5i-a13.dtsi +5
-0+ clock-names = "ahb", "mod"; + interrupts = <34>; + status = "disabled"; + }; +The A13 user manual reports that there is 3 of them in the A13, just like on the A10s. Have you forgotten one?
mmc1 is likely there, but it is not usable as it is not routed to the outside, so I've left it out deliberately.
Regards,
Hans
PATCH v8 8/17 ARM: dts: sun5i: Add pin-muxing info for the mmc controllers
In reply to Hans de GoedeThis adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards.
--- arch/arm/boot/dts/sun5i-a10s.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++ 2 files changed, 21 insertions(+)
arch/arm/boot/dts/sun5i-a10s.dtsi +14 -0
@@ -478,6 +478,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0 at 0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc1_pins_a: mmc1 at 0 { + allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; + allwinner,function = "mmc1"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer at 01c20c00 {
arch/arm/boot/dts/sun5i-a13.dtsi +7 -0
@@ -433,6 +433,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0 at 0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer at 01c20c00 {
Signature · 1 line
1.9.0
PATCH v8 9/17 ARM: dts: sun5i: Enable mmc controller on various A10s and A13 boards
In reply to Hans de GoedeThe cd pin settings have been taken from the original firmware fex files, and have been confirmed to work on the actual boards.
--- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 32 ++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 16 ++++++++++++ arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 16 ++++++++++++ 3 files changed, 64 insertions(+)
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +32 -0
@@ -35,6 +35,24 @@ }; }; + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; + bus-width = <4>; + cd-gpios = <&pio 6 1 0>; /* PG1 */ + cd-inverted; + status = "okay"; + }; + + mmc1: mmc at 01c10000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; + bus-width = <4>; + cd-gpios = <&pio 6 13 0>; /* PG13 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay";
@@ -49,6 +67,20 @@ }; pinctrl at 01c20800 { + mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin at 0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin at 0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins at 0 { allwinner,pins = "PE3"; allwinner,function = "gpio_out";
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +16 -0
@@ -21,6 +21,15 @@ compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; soc at 01c00000 { + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay";
@@ -35,6 +44,13 @@ }; pinctrl at 01c20800 { + mmc0_cd_pin_olinuxinom: mmc0_cd_pin at 0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxinom: led_pins at 0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out";
arch/arm/boot/dts/sun5i-a13-olinuxino.dts +16 -0
@@ -20,6 +20,15 @@ compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; soc at 01c00000 { + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay";
@@ -34,6 +43,13 @@ }; pinctrl at 01c20800 { + mmc0_cd_pin_olinuxino: mmc0_cd_pin at 0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins at 0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out";
Signature · 1 line
1.9.0
PATCH v8 10/17 ARM: dts: sun6i: Add mmc clocks
In reply to Hans de GoedeAdd clk-nodes for the mmc clocks.
--- arch/arm/boot/dts/sun6i-a31.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +32 -0
@@ -198,6 +198,38 @@ "apb2_uart4", "apb2_uart5"; }; + mmc0_clk: clk at 01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk at 01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk at 01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk at 01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc3"; + }; + spi0_clk: clk at 01c200a0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk";
Signature · 1 line
1.9.0
PATCH v8 10/17 ARM: dts: sun6i: Add mmc clocks
Quoted 12 lines · Hans de Goede
Add clk-nodes for the mmc clocks.
Signed-off-by Hans de Goede <[email protected]>--- arch/arm/boot/dts/sun6i-a31.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)arch/arm/boot/dts/sun6i-a31.dtsi +0
-0
arch/arm/boot/dts/sun6i-a31.dtsi line 203
Quoted 6 lines
arch/arm/boot/dts/sun6i-a31.dtsi +3
-0@@ -198,6 +198,38 @@ "apb2_uart4", "apb2_uart5"; }; + mmc0_clk: clk at 01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk";
This is simply not true.
module0 clocks don't have any kind of phase control, while we do here.
You should introduce a new compatible.
(and change the clock-names content accordingly)
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140423/b770600c/attachment.sig>
[linux-sunxi] Re: [PATCH v8 10/17] ARM: dts: sun6i: Add mmc clocks
Hi,
Quoted 16 lines · Maxime Ripard
Quoted 15 lines · Hans de Goede
Add clk-nodes for the mmc clocks.
Signed-off-by Hans de Goede <[email protected]>--- arch/arm/boot/dts/sun6i-a31.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)arch/arm/boot/dts/sun6i-a31.dtsi +0
-0@@ -198,6 +198,38 @@ "apb2_uart4", "apb2_uart5"; };
Quoted 7 lines
arch/arm/boot/dts/sun6i-a31.dtsi line 203
Quoted 3 lines
arch/arm/boot/dts/sun6i-a31.dtsi +3
-0+ mmc0_clk: clk at 01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk";This is simply not true.
module0 clocks don't have any kind of phase control, while we do here.
We've the exact same situation for all of sun4i, sun5i and sun7i. IMHO it would be much simpler to keep things uns sync everywhere, until we actually know how we want to deal with the phase control stuff, and then change the compatible, etc. everywhere at once.
Regards,
Hans
PATCH v8 11/17 ARM: dts: sun6i: Add mmc controller nodes
In reply to Hans de GoedeAdd nodes for the 4 mmc controllers found on A31 SoCs to arch/arm/boot/dts/sun6i-a31.dtsi.
--- arch/arm/boot/dts/sun6i-a31.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +52 -0
@@ -269,6 +269,58 @@ #size-cells = <1>; ranges; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + bus-width = <4>; + cd-inverted; + status = "disabled"; + }; + + mmc1: mmc at 01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 9>; + reset-names = "reset"; + interrupts = <0 61 4>; + bus-width = <4>; + cd-inverted; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 10>; + reset-names = "reset"; + interrupts = <0 62 4>; + bus-width = <4>; + cd-inverted; + status = "disabled"; + }; + + mmc3: mmc at 01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb1_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 11>; + reset-names = "reset"; + interrupts = <0 63 4>; + bus-width = <4>; + cd-inverted; + status = "disabled"; + }; + nmi_intc: interrupt-controller at 01f00c0c { compatible = "allwinner,sun6i-a31-sc-nmi"; interrupt-controller;
Signature · 1 line
1.9.0
PATCH v8 11/17 ARM: dts: sun6i: Add mmc controller nodes
Quoted 16 lines · Hans de Goede
Add nodes for the 4 mmc controllers found on A31 SoCs to
arch/arm/boot/dts/sun6i-a31.dtsi.Signed-off-by Hans de Goede <[email protected]>--- arch/arm/boot/dts/sun6i-a31.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)arch/arm/boot/dts/sun6i-a31.dtsi +0
-0@@ -269,6 +269,58 @@ #size-cells = <1>; ranges;
arch/arm/boot/dts/sun6i-a31.dtsi line 281
Quoted 10 lines
arch/arm/boot/dts/sun6i-a31.dtsi +10
-0+ mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + bus-width = <4>; + cd-inverted;
The two last items should be in the DTS.
Looks good otherwise.
Thanks!
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140423/1e9fa971/attachment.sig>
PATCH v8 11/17 ARM: dts: sun6i: Add mmc controller nodes
Hi,
Quoted 17 lines · Maxime Ripard
Quoted 16 lines · Hans de Goede
Add nodes for the 4 mmc controllers found on A31 SoCs to
arch/arm/boot/dts/sun6i-a31.dtsi.Signed-off-by Hans de Goede <[email protected]>--- arch/arm/boot/dts/sun6i-a31.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)arch/arm/boot/dts/sun6i-a31.dtsi +0
-0@@ -269,6 +269,58 @@ #size-cells = <1>; ranges;
Quoted 12 lines
arch/arm/boot/dts/sun6i-a31.dtsi line 281
Quoted 10 lines
arch/arm/boot/dts/sun6i-a31.dtsi +10
-0+ mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + bus-width = <4>; + cd-inverted;The two last items should be in the DTS.
Ah, I had fixed sun4i / sun5i & sun7i but forgot about this one, fixed in my local tree now. I've also squashed the m9 mmc enablement patch into the m9 addition patch as you've requested.
Regards,
Hans
PATCH v8 12/17 ARM: dts: sun6i: Add pin-muxing info for the mmc controllers
In reply to Hans de GoedeThis adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards.
--- arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +7 -0
@@ -370,6 +370,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0 at 0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset at 01c202c0 {
Signature · 1 line
1.9.0
PATCH v8 13/17 ARM: dts: sun6i: Add new sun6i-a31-m9 dts file for Mele M9
In reply to Hans de GoedeAdd a new sun6i-a31-m9 dts file for the Mele M9 / Mele A1000G Quad. These HTPCs use the same board in a different case, for more details see:
http://linux-sunxi.org/Mele_M9
--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun6i-a31-m9.dts | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31-m9.dts
arch/arm/boot/dts/Makefile +1 -0
@@ -351,6 +351,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun6i-a31-colombus.dtb \ + sun6i-a31-m9.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ sun7i-a20-olinuxino-micro.dtb
arch/arm/boot/dts/sun6i-a31-m9.dts new file +30 -0
@@ -0,0 +1,30 @@ +/* + * Copyright 2014 Hans de Goede <[email protected]> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" + +/ { + model = "Mele M9 / A1000G Quad top set box"; + compatible = "mele,m9", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc at 01c00000 { + uart0: serial at 01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; +};
Signature · 1 line
1.9.0
PATCH v8 14/17 ARM: dts: sun6i: Enable the mmc controller on the m9
In reply to Hans de GoedeTested on a Mele A1000G Quad.
--- arch/arm/boot/dts/sun6i-a31-m9.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm/boot/dts/sun6i-a31-m9.dts +16 -0
@@ -21,6 +21,22 @@ }; soc at 01c00000 { + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + cd-gpios = <&pio 7 22 0>; /* PH22 */ + status = "okay"; + }; + + pio: pinctrl at 01c20800 { + mmc0_cd_pin_m9: mmc0_cd_pin at 0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + uart0: serial at 01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>;
Signature · 1 line
1.9.0
PATCH v8 14/17 ARM: dts: sun6i: Enable the mmc controller on the m9
Quoted 3 lines · Hans de Goede
Tested on a Mele A1000G Quad.
Signed-off-by Hans de Goede <[email protected]>
This patch can be merged with the previous one.
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140423/a48c52ee/attachment.sig>
PATCH v8 15/17 ARM: dts: sun7i: Add mmc controller nodes
In reply to Hans de GoedeAdd nodes for the 4 mmc controllers found on A20 SoCs to arch/arm/boot/dts/sun7i-a20.dtsi.
--- arch/arm/boot/dts/sun7i-a20.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
arch/arm/boot/dts/sun7i-a20.dtsi +36 -0
@@ -447,6 +447,42 @@ #size-cells = <0>; }; + mmc0: mmc at 01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mod"; + interrupts = <0 32 4>; + status = "disabled"; + }; + + mmc1: mmc at 01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mod"; + interrupts = <0 33 4>; + status = "disabled"; + }; + + mmc2: mmc at 01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mod"; + interrupts = <0 34 4>; + status = "disabled"; + }; + + mmc3: mmc at 01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mod"; + interrupts = <0 35 4>; + status = "disabled"; + }; + usbphy: phy at 01c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy";
Signature · 1 line
1.9.0
PATCH v8 16/17 ARM: dts: sun7i: Add pin-muxing info for the mmc controllers
In reply to Hans de GoedeThis adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards.
--- arch/arm/boot/dts/sun7i-a20.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
arch/arm/boot/dts/sun7i-a20.dtsi +21 -0
@@ -689,6 +689,27 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0 at 0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_a: mmc0_cd_pin at 0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc3_pins_a: mmc3 at 0 { + allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; + allwinner,function = "mmc3"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer at 01c20c00 {
Signature · 1 line
1.9.0
PATCH v8 17/17 ARM: dts: sun7i: Enable mmc controller on various A20 boards
In reply to Hans de GoedeThe cd pin settings have been taken from the original firmware fex files, and have been confirmed to work on the actual boards.
--- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 9 +++++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 9 +++++++++ arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 25 +++++++++++++++++++++++++ 3 files changed, 43 insertions(+)
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +9 -0
@@ -20,6 +20,15 @@ compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; soc at 01c00000 { + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
arch/arm/boot/dts/sun7i-a20-cubietruck.dts +9 -0
@@ -20,6 +20,15 @@ compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; soc at 01c00000 { + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +25 -0
@@ -31,6 +31,24 @@ status = "okay"; }; + mmc0: mmc at 01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc at 01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; + bus-width = <4>; + cd-gpios = <&pio 7 11 0>; /* PH11 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy at 01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>;
@@ -65,6 +83,13 @@ }; pinctrl at 01c20800 { + mmc3_cd_pin_olinuxinom: mmc3_cd_pin at 0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins at 0 { allwinner,pins = "PH2"; allwinner,function = "gpio_out";
Signature · 1 line
1.9.0
Emilio López
maintainerv8 cover ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
In reply to Hans de GoedeHi Hans,
El 22/04/14 08:01, Hans de Goede escribi?:
Quoted 10 lines
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzend?rfer and I have been working on.
The first 2 patches are depenencies which should go in through the clk tree, Mike can you pick these 2 up please ? :
"clk: sunxi: factors: automatic reparenting support"
Is uncontroversial and has been favorably reviewed by various people.
I'll pick this one up for 3.16 if you're ok with that. Mike, let me know if you have any objection to the patch, but I'm pretty sure you (informally?) acked it in the past.
Quoted 7 lines
"clk: sunxi: Implement MMC phase control"
Is somewhat more controversial as there has been lots of discussion about adding a generic phase control method to the clk framework. The problem is that there has been a lot of talk about such a generic phase control method but not a single patch. Therefor I would like to move forwards with using a platform specific method for now. I hereby promise that once we've a generic method I'll write patches to convert the sunxi code to that method.
Mike proposed a RFC for handling this better, and there were talks with Allwinner people to see what did these phase controls actually mean. We should be able to get a proper solution for it during this cycle. I'd prefer to work towards that instead of merging this, as we have more than a month to get it ready still.
Cheers,
Emilio
v8 cover ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
Hi,
Quoted 24 lines · Emilio L?pez
Hi Hans,
El 22/04/14 08:01, Hans de Goede escribi?:
Quoted 10 lines
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzend?rfer and I have been working on.
The first 2 patches are depenencies which should go in through the clk tree, Mike can you pick these 2 up please ? :
"clk: sunxi: factors: automatic reparenting support"
Is uncontroversial and has been favorably reviewed by various people.I'll pick this one up for 3.16 if you're ok with that. Mike, let me know if you have any objection to the patch, but I'm pretty sure you (informally?) acked it in the past.
Quoted 7 lines
"clk: sunxi: Implement MMC phase control"
Is somewhat more controversial as there has been lots of discussion about adding a generic phase control method to the clk framework. The problem is that there has been a lot of talk about such a generic phase control method but not a single patch. Therefor I would like to move forwards with using a platform specific method for now. I hereby promise that once we've a generic method I'll write patches to convert the sunxi code to that method.
Quoted 1 line
Mike proposed a RFC for handling this better, and there were talks with Allwinner people to see what did these phase controls actually mean. We should be able to get a proper solution for it during this cycle. I'd prefer to work towards that instead of merging this, as we have more than a month to get it ready still.
A month will be gone before you know it, and merging sunxi mmc support really is long overdue, and is the last thing keeping distros from shipping with sunxi support ootb. So I would really prefer to just get this merged as is for now, changing it later should be easy, and merging an interim solution will make some more time for doing the generic clk phase control method properly.
Regards,
Hans
v8 cover ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
Quoted 35 lines · Hans de Goede
Hi,
Quoted 26 lines · Emilio L?pez
Hi Hans,
El 22/04/14 08:01, Hans de Goede escribi?:
Quoted 10 lines
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzend?rfer and I have been working on.
The first 2 patches are depenencies which should go in through the clk tree, Mike can you pick these 2 up please ? :
"clk: sunxi: factors: automatic reparenting support"
Is uncontroversial and has been favorably reviewed by various people.I'll pick this one up for 3.16 if you're ok with that. Mike, let me know if you have any objection to the patch, but I'm pretty sure you (informally?) acked it in the past.
Quoted 7 lines
"clk: sunxi: Implement MMC phase control"
Is somewhat more controversial as there has been lots of discussion about adding a generic phase control method to the clk framework. The problem is that there has been a lot of talk about such a generic phase control method but not a single patch. Therefor I would like to move forwards with using a platform specific method for now. I hereby promise that once we've a generic method I'll write patches to convert the sunxi code to that method.Quoted 5 lines
Mike proposed a RFC for handling this better, and there were talks with Allwinner people to see what did these phase controls actually mean. We should be able to get a proper solution for it during this cycle. I'd prefer to work towards that instead of merging this, as we have more than a month to get it ready still.
Quoted 5 lines
A month will be gone before you know it, and merging sunxi mmc support really is long overdue, and is the last thing keeping distros from shipping with sunxi support ootb. So I would really prefer to just get this merged as is for now, changing it later should be easy, and merging an interim solution will make some more time for doing the generic clk phase control method properly.
While I'd be inclined to agree, it will be up to Mike.
Mike?
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140423/56d549db/attachment.sig>
v8 cover ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
In reply to Hans de GoedeHi Hans,
Quoted 19 lines · Hans de Goede
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzend?rfer and I have been working on.
The first 2 patches are depenencies which should go in through the clk tree, Mike can you pick these 2 up please ? :
"clk: sunxi: factors: automatic reparenting support"
Is uncontroversial and has been favorably reviewed by various people."clk: sunxi: Implement MMC phase control"
Is somewhat more controversial as there has been lots of discussion about adding a generic phase control method to the clk framework. The problem is that there has been a lot of talk about such a generic phase control method but not a single patch. Therefor I would like to move forwards with using a platform specific method for now. I hereby promise that once we've a generic method I'll write patches to convert the sunxi code to that method.
Quoted 5 lines
The third patch is the patch adding the actual mmc driver and should go in through the mmc tree.
All the other patches are devicetree patches hooking things up, and should go upstream through Maxime's sunxi-dt tree.
Apart from the ever-controversial phase control thing, and the minor comments I had here and there, this looks good, thanks!
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140423/ffae2471/attachment.sig>