board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
PATCH v2 1/1 board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs.
So Slow MDC clock to comply IEEE specs
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Update commit message
board/freescale/b4860qds/b4_pbi.cfg | 3 +++ 1 file changed, 3 insertions(+)
board/freescale/b4860qds/b4_pbi.cfg +3 -0
@@ -22,6 +22,9 @@ 09110024 00100008 09110028 00100008 0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 #Flush PBL data 09138000 00000000 091380c0 00000000
Signature · 1 line
1.7.9.5
PATCH v2 1/1 board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
Quoted 8 lines · Prabhakar Kushwaha
The MDC generate by default value of
MDIO_CLK_DIVis too high i.e. higher than 2.5 MHZ. It violates the IEEE specs.So Slow MDC clock to comply IEEE specs
Signed-off-by Prabhakar Kushwaha <[email protected]>---
Changes for v2: Update commit message
Applied to u-boot-mpc85xx/master, thanks.
York