driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3

MDIO clock needs to be initialized in u-boot code for SoCs having FMAN-v3(v3H or v3L) controller due to below reasons

-On SoCs that have FMAN-v3H like B4860, default value of MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates mdio clock too high (much higher than 2.5MHz), violating the IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.

So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to be properly initialized.
Also this type of initialization is generally done in PBI(pre-bootloader) phase using rcw.But for chips like T1040 which support deep-sleep, such type of initialization cannot be done in PBI phase due to the limitation that during deep-sleep resume, FMAN (MDIO) registers are not accessible in PBI phase. So, mdio clock initailization must be done as part of u-boot.

This initialization code is implemented in memac_phy.c which gets compiled only for SoCs having FMANv3, so no extra compilation flag is required.

---
Changes for v2: Corrected Signed-off footer

 drivers/net/fm/memac_phy.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

index 140e59b..2f4bc11 100644
@@ -133,5 +133,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
 
 	bus->priv = info->regs;
 
+	/*
+	 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+	 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+	 * (much higher than 2.5MHz), violating the IEEE specs.
+	 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+	 * is zero, so MDIO clock is disabled.
+	 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+	 * be properly initialized.
+	 */
+	setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
+		     MDIO_STAT_CLKDIV(258));
+
 	return mdio_register(bus);
 }

1.7.4.1

Applied to u-boot-mpc85xx/master, thanks.

York