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board/t208xqds: Add support of 2-stage NAND/SPI/SD boot

PATCH New Shengzhou Liu 2 participants 6 messages Apr 18, 2014 – Apr 23, 2014

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Shengzhou Liu

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#0 lore raw

PATCH v2 1/3 board/t208xqds: Add support of 2-stage NAND/SPI/SD boot

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot.

Signed-off-by Shengzhou Liu <[email protected]>

---
v2: updated to adapt to new SPL.

 board/freescale/t208xqds/Makefile |   5 ++
 board/freescale/t208xqds/ddr.c    |   7 +-
 board/freescale/t208xqds/spl.c    | 137 ++++++++++++++++++++++++++++++++++++++
 board/freescale/t208xqds/tlb.c    |   7 ++
 boards.cfg                        |  12 ++--
 include/configs/T208xQDS.h        | 113 +++++++++++++++++++++++++------
 6 files changed, 253 insertions(+), 28 deletions(-)
 create mode 100644 board/freescale/t208xqds/spl.c
board/freescale/t208xqds/Makefile +5 -0
index 947b7f7..6cb72c9 100644
@@ -4,11 +4,16 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T2080QDS) += t208xqds.o
 obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
 obj-$(CONFIG_T2081QDS) += t208xqds.o
 obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
 obj-$(CONFIG_PCI)      += pci.o
+endif
+
 obj-y   += ddr.o
 obj-y   += law.o
 obj-y   += tlb.o
board/freescale/t208xqds/ddr.c +5 -2
index ed1334d..3348971 100644
@@ -107,13 +107,16 @@ phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
 
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
 
-	puts("    DDR: ");
 	return dram_size;
 }
board/freescale/t208xqds/spl.c new file +137 -0

137 lines not on this page · raw message

board/freescale/t208xqds/tlb.c +7 -0
index 62cd110..8d60298 100644
@@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCIe 1, 0x80000000 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

@@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

@@ -141,6 +143,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
 
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
boards.cfg +6 -6
index ff385b9..2be3d42 100644
@@ -959,14 +959,14 @@ Active  powerpc     mpc85xx        -           freescale       t104xrdb
 Active  powerpc     mpc85xx        -           freescale       t104xrdb            T1042RDB_PI_SPIFLASH                 T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH                                                                     Priyanka Jain  <[email protected]>
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS                             T208xQDS:PPC_T2080                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SECURE_BOOT                 T208xQDS:PPC_T2080,SECURE_BOOT                                                                                                    Aneesh Bansal <[email protected]>
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_NAND                        T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SDCARD                      T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SPIFLASH                    T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_NAND                        T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SDCARD                      T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SPIFLASH                    T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2080QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS                             T208xQDS:PPC_T2081                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_NAND                        T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SDCARD                      T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_NAND                        T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SDCARD                      T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB                             T208xRDB:PPC_T2080                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
include/configs/T208xQDS.h +93 -20

174 lines not on this page · raw message

Signature · 1 line
1.8.0
author
#1 lore raw

PATCH v2 2/3 board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot.

Signed-off-by Shengzhou Liu <[email protected]>

---
v2: updated to adapt to new SPL.

 board/freescale/t208xrdb/Makefile |   5 ++
 board/freescale/t208xrdb/README   |  80 +++++++++++++++++++++++-----
 board/freescale/t208xrdb/ddr.c    |   8 +--
 board/freescale/t208xrdb/spl.c    | 107 +++++++++++++++++++++++++++++++++++++
 board/freescale/t208xrdb/tlb.c    |   4 +-
 boards.cfg                        |   6 +--
 include/configs/T208xRDB.h        | 108 ++++++++++++++++++++++++++++++++------
 7 files changed, 282 insertions(+), 36 deletions(-)
 create mode 100644 board/freescale/t208xrdb/spl.c
board/freescale/t208xrdb/Makefile +5 -0
index 092c9ff..9605f8b 100644
@@ -4,10 +4,15 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T2080RDB) += t208xrdb.o
 obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
 obj-$(CONFIG_T2080RDB) += cpld.o
 obj-$(CONFIG_PCI)      += pci.o
+endif
+
 obj-y   += ddr.o
 obj-y   += law.o
 obj-y   += tlb.o
board/freescale/t208xrdb/README +68 -12

113 lines not on this page · raw message

board/freescale/t208xrdb/ddr.c +5 -3
index 01e9173..8a26276 100644
@@ -100,13 +100,15 @@ phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
 
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
-
-	puts("    DDR: ");
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size = fsl_ddr_sdram_size();
+#endif
 	return dram_size;
 }
board/freescale/t208xrdb/spl.c new file +107 -0

107 lines not on this page · raw message

board/freescale/t208xrdb/tlb.c +3 -1
index 085d9f5..2ebea36 100644
@@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCIe 1, 0x80000000 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

@@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

@@ -140,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
boards.cfg +3 -3
index 2be3d42..d6ad103 100644
@@ -969,9 +969,9 @@ Active  powerpc     mpc85xx        -           freescale       t208xqds
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB                             T208xRDB:PPC_T2080                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD                      T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH                    T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD                      T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH                    T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SRIO_PCIE_BOOT              T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SECURE_BOOT                 T4240QDS:PPC_T4160,SECURE_BOOT                                                                                                    Aneesh Bansal <[email protected]>
include/configs/T208xRDB.h +91 -17

156 lines not on this page · raw message

Signature · 1 line
1.8.0
#2 lore raw

PATCH v2 2/3 board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot

Quoted 9 lines · Shengzhou Liu

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot.

Signed-off-by Shengzhou Liu <[email protected]>

---
v2: updated to adapt to new SPL.

Applied to u-boot-mpc85xx/master, thanks.

York

author
#3 lore raw

PATCH v2 3/3 board/t2080rdb: some update for t2080rdb

In reply to Shengzhou Liu

- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

Signed-off-by Shengzhou Liu <[email protected]>

---
v2: add eeprom update.

 board/freescale/t208xrdb/README     |  6 +++---
 board/freescale/t208xrdb/cpld.h     |  4 ++--
 board/freescale/t208xrdb/t208xrdb.c |  2 +-
 include/configs/T208xRDB.h          | 13 +++++++++----
 4 files changed, 15 insertions(+), 10 deletions(-)
board/freescale/t208xrdb/README +3 -3
index fe26de5..24484cd 100644
@@ -67,7 +67,7 @@ T2080PCIe-RDB board Overview
      - One PCIe x2 end-point device (C293 Crypto co-processor)
  - IFC/Local Bus
      - NOR:  128MB 16-bit NOR Flash
-     - NAND: 512MB 8-bit NAND flash
+     - NAND: 1GB 8-bit NAND flash
      - CPLD: for system controlling with programable header on-board
  - SATA
      - Two SATA 2.0 onnectors on-board

@@ -156,11 +156,11 @@ Software configurations and board settings
    Switching between default bank and alternate bank on NOR flash
    To change boot source to vbank4:
 	via software:   run command 'cpld reset altbank' in u-boot.
-	via DIP-switch: set SW3[5:7] = '011'
+	via DIP-switch: set SW3[5:7] = '100'
 
    To change boot source to vbank0:
 	via software:   run command 'cpld reset' in u-boot.
-	via DIP-Switch: set SW3[5:7] = '111'
+	via DIP-Switch: set SW3[5:7] = '000'
 
 2. NAND Boot:
    a. build PBL image for NAND boot
board/freescale/t208xrdb/cpld.h +2 -2
index 4cee4e5..3f15338 100644
@@ -35,8 +35,8 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_LBMAP_MASK		0x3F
 #define CPLD_BANK_SEL_MASK	0x07
 #define CPLD_BANK_OVERRIDE	0x40
-#define CPLD_LBMAP_ALTBANK	0x43 /* BANK OR | BANK 4 */
-#define CPLD_LBMAP_DFLTBANK	0x47 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_ALTBANK	0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK	0x40 /* BANK OR | BANK 0 */
 #define CPLD_LBMAP_RESET	0xFF
 #define CPLD_LBMAP_SHIFT	0x03
 #define CPLD_BOOT_SEL		0x80
board/freescale/t208xrdb/t208xrdb.c +1 -1
index f3fec2a..265c1f9 100644
@@ -44,7 +44,7 @@ int checkboard(void)
 		puts("NAND\n");
 	} else {
 		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
-		printf("NOR vBank%d\n", ~reg & 0x7);
+		printf("NOR vBank%d\n", reg);
 	}
 #endif
include/configs/T208xRDB.h +9 -4
index 4ef1167..73d82ed 100644
@@ -208,7 +208,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM	0
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
 
 /*
  * DDR Setup

@@ -584,7 +584,8 @@ unsigned long get_board_ddr_clk(void);
  * env, so we got 0x110000.
  */
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x110000
 #define CONFIG_CORTINA_FW_ADDR		0x120000
 
 #elif defined(CONFIG_SDCARD)

@@ -594,11 +595,13 @@ unsigned long get_board_ddr_clk(void);
  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_CORTINA_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
 #define CONFIG_CORTINA_FW_ADDR		(512 * 0x8a0)
 
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_CORTINA_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_CORTINA_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)

@@ -610,11 +613,13 @@ unsigned long get_board_ddr_clk(void);
  * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
-#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR		0xFFE00000
 #define CONFIG_CORTINA_FW_ADDR		0xFFE10000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
 #define CONFIG_CORTINA_FW_ADDR		0xEFE00000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
Signature · 1 line
1.8.0
#4 lore raw

PATCH v2 3/3 board/t2080rdb: some update for t2080rdb

Quoted 11 lines · Shengzhou Liu

- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

Signed-off-by Shengzhou Liu <[email protected]>

---
v2: add eeprom update.

Applied to u-boot-mpc85xx/master, thanks.

York

#5 lore raw

PATCH v2 1/3 board/t208xqds: Add support of 2-stage NAND/SPI/SD boot

In reply to Shengzhou Liu
Quoted 10 lines · Shengzhou Liu

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot.

Signed-off-by Shengzhou Liu <[email protected]>

---
v2: updated to adapt to new SPL.

Applied to u-boot-mpc85xx/master, thanks.

York