arm: dts: am43x-clock: add tbclk data for ehrpwm.
Subsystems (3)
PATCH 1/1 arm: dts: am43x-clock: add tbclk data for ehrpwm.
We need "tblclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file.
Signed-off-by Sourav Poddar <[email protected]>
--- arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clk-43xx.c | 6 +++ 2 files changed, 90 insertions(+)
arch/arm/boot/dts/am43xx-clocks.dtsi +84 -0
@@ -87,6 +87,90 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm0_gate_tbclk>; + }; + + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm1_gate_tbclk>; + }; + + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm2_gate_tbclk>; + }; + + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm3_gate_tbclk>; + }; + + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm4_gate_tbclk>; + }; + + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm5_gate_tbclk>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck {
drivers/clk/ti/clk-43xx.c +6 -0
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {DT_CLK (NULL ,"func_12m_clk" ,"func_12m_clk" ),DT_CLK (NULL ,"vtp_clk_div" ,"vtp_clk_div" ),DT_CLK (NULL ,"usbphy_32khz_clkmux" ,"usbphy_32khz_clkmux" ), +DT_CLK ("48300200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48302200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("48304200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), +DT_CLK ("48306200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48308200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("4830a200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), { .node_name = NULL }, };
Signature · 1 line
1.7.9.5
PATCH 1/1 arm: dts: am43x-clock: add tbclk data for ehrpwm.
Quoted 22 lines · Sourav Poddar
We need "tblclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file.
Signed-off-by Sourav Poddar <[email protected]>--- arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clk-43xx.c | 6 +++ 2 files changed, 90 insertions(+)arch/arm/boot/dts/am43xx-clocks.dtsi +4
-0@@ -87,6 +87,90 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock";
arch/arm/boot/dts/am43xx-clocks.dtsi line 103
Quoted 10 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +10
-0+ clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm0_gate_tbclk>; + };
Why do you use composite-clock type here? I see only add one sub-clock to the composite, thus the composite part is unused. How about using a gate-clock type only? Same question applies for the rest of the patch also.
-Tero
Quoted 91 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +70
-0+ + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm1_gate_tbclk>; + }; + + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm2_gate_tbclk>; + }; + + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm3_gate_tbclk>; + }; + + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm4_gate_tbclk>; + }; + + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm5_gate_tbclk>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck {drivers/clk/ti/clk-43xx.c +6
-0@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {DT_CLK (NULL ,"func_12m_clk" ,"func_12m_clk" ),DT_CLK (NULL ,"vtp_clk_div" ,"vtp_clk_div" ),DT_CLK (NULL ,"usbphy_32khz_clkmux" ,"usbphy_32khz_clkmux" ), +DT_CLK ("48300200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48302200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("48304200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), +DT_CLK ("48306200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48308200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("4830a200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), { .node_name = NULL }, };
PATCH 1/1 arm: dts: am43x-clock: add tbclk data for ehrpwm.
Hi Tero,
Quoted 32 lines · Tero Kristo
Quoted 31 lines · Sourav Poddar
We need "tblclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file.
Signed-off-by Sourav Poddar <[email protected]>--- arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clk-43xx.c | 6 +++ 2 files changed, 90 insertions(+)arch/arm/boot/dts/am43xx-clocks.dtsi +11
-0@@ -87,6 +87,90 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>;
Quoted 9 lines
arch/arm/boot/dts/am43xx-clocks.dtsi line 103
Quoted 3 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +3
-0+ compatible = "ti,composite-clock"; + clocks = <&ehrpwm0_gate_tbclk>; + };Why do you use composite-clock type here? I see only add one sub-clock to the composite, thus the composite part is unused. How about using a gate-clock type only? Same question applies for the rest of the patch also.
Yes, I though of doing so and I think it should be fine to use gate-clock only. I did this following the ehrpwm clock data in "am33xx-clock.dtsi" file, where we use composite clock for ehrpwm. I think it needs to be changed there also.?
-Sourav
Quoted 94 lines
-Tero
Quoted 91 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +70
-0+ + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm1_gate_tbclk>; + }; + + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm2_gate_tbclk>; + }; + + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm3_gate_tbclk>; + }; + + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm4_gate_tbclk>; + }; + + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm5_gate_tbclk>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck {drivers/clk/ti/clk-43xx.c +6
-0@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {DT_CLK (NULL ,"func_12m_clk" ,"func_12m_clk" ),DT_CLK (NULL ,"vtp_clk_div" ,"vtp_clk_div" ),DT_CLK (NULL ,"usbphy_32khz_clkmux" ,"usbphy_32khz_clkmux" ), +DT_CLK ("48300200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48302200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("48304200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), +DT_CLK ("48306200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48308200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("4830a200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), { .node_name = NULL }, };
PATCH 1/1 arm: dts: am43x-clock: add tbclk data for ehrpwm.
Quoted 45 lines · sourav
Hi Tero,
Quoted 32 lines · Tero Kristo
Quoted 31 lines · Sourav Poddar
We need "tblclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file.
Signed-off-by Sourav Poddar <[email protected]>--- arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clk-43xx.c | 6 +++ 2 files changed, 90 insertions(+)arch/arm/boot/dts/am43xx-clocks.dtsi +11
-0@@ -87,6 +87,90 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>;Quoted 9 lines
arch/arm/boot/dts/am43xx-clocks.dtsi line 103
Quoted 3 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +3
-0+ compatible = "ti,composite-clock"; + clocks = <&ehrpwm0_gate_tbclk>; + };Why do you use composite-clock type here? I see only add one sub-clock to the composite, thus the composite part is unused. How about using a gate-clock type only? Same question applies for the rest of the patch also.
Quoted 4 lines
Yes, I though of doing so and I think it should be fine to use gate-clock only. I did this following the ehrpwm clock data in "
am33xx-clock.dtsi" file, where we use composite clock for ehrpwm. I think it needs to be changed there also.?
Yeah, that seems to be a quirk that was generated by the automatic conversion script, there is no reason for these being composite clocks either.
-Tero
Quoted 97 lines
-Sourav
Quoted 94 lines
-Tero
Quoted 91 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +70
-0+ + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm1_gate_tbclk>; + }; + + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm2_gate_tbclk>; + }; + + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm3_gate_tbclk>; + }; + + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm4_gate_tbclk>; + }; + + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm5_gate_tbclk>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck {drivers/clk/ti/clk-43xx.c +6
-0@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {DT_CLK (NULL ,"func_12m_clk" ,"func_12m_clk" ),DT_CLK (NULL ,"vtp_clk_div" ,"vtp_clk_div" ),DT_CLK (NULL ,"usbphy_32khz_clkmux" ,"usbphy_32khz_clkmux" ), +DT_CLK ("48300200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48302200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("48304200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), +DT_CLK ("48306200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48308200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("4830a200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), { .node_name = NULL }, };
PATCH 1/1 arm: dts: am43x-clock: add tbclk data for ehrpwm.
Quoted 46 lines · Tero Kristo
Quoted 45 lines · sourav
Hi Tero,
Quoted 41 lines · Tero Kristo
Quoted 24 lines · Sourav Poddar
We need "tblclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file.
Signed-off-by Sourav Poddar <[email protected]>--- arch/arm/boot/dts/am43xx-clocks.dtsi | 84 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clk-43xx.c | 6 +++ 2 files changed, 90 insertions(+)arch/arm/boot/dts/am43xx-clocks.dtsi +4
-0@@ -87,6 +87,90 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock";arch/arm/boot/dts/am43xx-clocks.dtsi line 103
Quoted 10 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +10
-0+ clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm0_gate_tbclk>; + };Why do you use composite-clock type here? I see only add one sub-clock to the composite, thus the composite part is unused. How about using a gate-clock type only? Same question applies for the rest of the patch also.
Quoted 8 lines
Quoted 4 lines
Yes, I though of doing so and I think it should be fine to use gate-clock only. I did this following the ehrpwm clock data in "
am33xx-clock.dtsi" file, where we use composite clock for ehrpwm. I think it needs to be changed there also.?Yeah, that seems to be a quirk that was generated by the automatic conversion script, there is no reason for these being composite clocks either.
OK, I will send the updated patch for both am33xx and am43xx devices.
Thanks,
Sourav
Quoted 101 lines
-Tero
Quoted 97 lines
-Sourav
Quoted 94 lines
-Tero
Quoted 91 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +70
-0+ + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm1_gate_tbclk>; + }; + + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm2_gate_tbclk>; + }; + + ehrpwm3_gate_tbclk: ehrpwm3_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm3_gate_tbclk>; + }; + + ehrpwm4_gate_tbclk: ehrpwm4_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm4_gate_tbclk>; + }; + + ehrpwm5_gate_tbclk: ehrpwm5_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm5_gate_tbclk>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck {drivers/clk/ti/clk-43xx.c +6
-0@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {DT_CLK (NULL ,"func_12m_clk" ,"func_12m_clk" ),DT_CLK (NULL ,"vtp_clk_div" ,"vtp_clk_div" ),DT_CLK (NULL ,"usbphy_32khz_clkmux" ,"usbphy_32khz_clkmux" ), +DT_CLK ("48300200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48302200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("48304200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), +DT_CLK ("48306200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48308200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("4830a200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), { .node_name = NULL }, };