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arm: dts: am33xx-clock: Fix ehrpwm tbclk data.

PATCH Superseded Sourav Poddar 2 participants 2 messages Apr 25, 2014 Device tree bindings

v1 of 2 Superseded Latest is v2 →

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Sourav Poddar

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#0 lore raw

PATCH 1/1 arm: dts: am33xx-clock: Fix ehrpwm tbclk data.

tbclk does not need to be a composite clock, we can simply use gate clock for this purpose.

Signed-off-by Sourav Poddar <[email protected]>
---
 arch/arm/boot/dts/am33xx-clocks.dtsi |   42 ++++++++++------------------------
 1 file changed, 12 insertions(+), 30 deletions(-)
arch/arm/boot/dts/am33xx-clocks.dtsi +12 -30
index 9ccfe50..a45d27f 100644
@@ -96,46 +96,28 @@
 		clock-div = <1>;
 	};
 
-	ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+	ehrpwm0_tbclk: ehrpwm0_tbclk at 44e10664 {
 		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
+		compatible = "gate-clock";
 		clocks = <&dpll_per_m2_ck>;
-		ti,bit-shift = <0>;
-		reg = <0x0664>;
+		bit-shift = <0>;
+		reg = <0x44e10664 0x4>;
 	};
 
-	ehrpwm0_tbclk: ehrpwm0_tbclk {
+	ehrpwm1_tbclk: ehrpwm1_tbclk at 44e10664 {
 		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&ehrpwm0_gate_tbclk>;
-	};
-
-	ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
+		compatible = "gate-clock";
 		clocks = <&dpll_per_m2_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x0664>;
-	};
-
-	ehrpwm1_tbclk: ehrpwm1_tbclk {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&ehrpwm1_gate_tbclk>;
+		bit-shift = <1>;
+		reg = <0x44e10664 0x4>;
 	};
 
-	ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+	ehrpwm2_tbclk: ehrpwm2_tbclk at 44e10664 {
 		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
+		compatible = "gate-clock";
 		clocks = <&dpll_per_m2_ck>;
-		ti,bit-shift = <2>;
-		reg = <0x0664>;
-	};
-
-	ehrpwm2_tbclk: ehrpwm2_tbclk {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&ehrpwm2_gate_tbclk>;
+		bit-shift = <2>;
+		reg = <0x44e10664 0x4>;
 	};
 };
 &prcm_clocks {
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 arm: dts: am33xx-clock: Fix ehrpwm tbclk data.

Quoted 13 lines · Sourav Poddar

tbclk does not need to be a composite clock, we can simply use gate clock for this purpose.

Signed-off-by Sourav Poddar <[email protected]>
---
  arch/arm/boot/dts/am33xx-clocks.dtsi |   42 ++++++++++------------------------
  1 file changed, 12 insertions(+), 30 deletions(-)
arch/arm/boot/dts/am33xx-clocks.dtsi +0 -0
index 9ccfe50..a45d27f 100644

arch/arm/boot/dts/am33xx-clocks.dtsi line 101

Quoted 8 lines
arch/arm/boot/dts/am33xx-clocks.dtsi +2 -2
@@ -96,46 +96,28 @@
  		clock-div = <1>;
  	};
 
-	ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+	ehrpwm0_tbclk: ehrpwm0_tbclk at 44e10664 {
  		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
+		compatible = "gate-clock";

ti,gate-clock? Simple "gate-clock" is not supported.

arch/arm/boot/dts/am33xx-clocks.dtsi line 103

Quoted 4 lines
arch/arm/boot/dts/am33xx-clocks.dtsi +1 -2
  		clocks = <&dpll_per_m2_ck>;
-		ti,bit-shift = <0>;
-		reg = <0x0664>;
+		bit-shift = <0>;

Should be ti,bit-shift as above.

arch/arm/boot/dts/am33xx-clocks.dtsi line 104

Quoted 1 line
arch/arm/boot/dts/am33xx-clocks.dtsi +1 -0
+		reg = <0x44e10664 0x4>;

You are using an obsolete register format here, the one you removed from above was correct.

Same comment applies for the rest of this patch.

-Tero

Quoted 46 lines
arch/arm/boot/dts/am33xx-clocks.dtsi +8 -26
  	};
 
-	ehrpwm0_tbclk: ehrpwm0_tbclk {
+	ehrpwm1_tbclk: ehrpwm1_tbclk at 44e10664 {
  		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&ehrpwm0_gate_tbclk>;
-	};
-
-	ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
+		compatible = "gate-clock";
  		clocks = <&dpll_per_m2_ck>;
-		ti,bit-shift = <1>;
-		reg = <0x0664>;
-	};
-
-	ehrpwm1_tbclk: ehrpwm1_tbclk {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&ehrpwm1_gate_tbclk>;
+		bit-shift = <1>;
+		reg = <0x44e10664 0x4>;
  	};
 
-	ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+	ehrpwm2_tbclk: ehrpwm2_tbclk at 44e10664 {
  		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
+		compatible = "gate-clock";
  		clocks = <&dpll_per_m2_ck>;
-		ti,bit-shift = <2>;
-		reg = <0x0664>;
-	};
-
-	ehrpwm2_tbclk: ehrpwm2_tbclk {
-		#clock-cells = <0>;
-		compatible = "ti,composite-clock";
-		clocks = <&ehrpwm2_gate_tbclk>;
+		bit-shift = <2>;
+		reg = <0x44e10664 0x4>;
  	};
  };
  &prcm_clocks {