arm: dts: am43x-clock: add tbclk data for ehrpwm.
Subsystems (3)
PATCH 1/1 arm: dts: am43x-clock: add tbclk data for ehrpwm.
We need "tbclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file.
Signed-off-by Sourav Poddar <[email protected]>
--- arch/arm/boot/dts/am43xx-clocks.dtsi | 48 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clk-43xx.c | 6 +++++ 2 files changed, 54 insertions(+)
arch/arm/boot/dts/am43xx-clocks.dtsi +48 -0
@@ -87,6 +87,54 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_tbclk: ehrpwm0_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <0>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <1>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <2>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <3>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <4>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <5>; + reg = <0x44e10664 0x4>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck {
drivers/clk/ti/clk-43xx.c +6 -0
@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {DT_CLK (NULL ,"func_12m_clk" ,"func_12m_clk" ),DT_CLK (NULL ,"vtp_clk_div" ,"vtp_clk_div" ),DT_CLK (NULL ,"usbphy_32khz_clkmux" ,"usbphy_32khz_clkmux" ), +DT_CLK ("48300200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48302200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("48304200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), +DT_CLK ("48306200.ehrpwm" ,"tbclk" ,"ehrpwm3_tbclk" ), +DT_CLK ("48308200.ehrpwm" ,"tbclk" ,"ehrpwm4_tbclk" ), +DT_CLK ("4830a200.ehrpwm" ,"tbclk" ,"ehrpwm5_tbclk" ), { .node_name = NULL }, };
Signature · 1 line
1.7.9.5
PATCH 1/1 arm: dts: am43x-clock: add tbclk data for ehrpwm.
Quoted 15 lines · Sourav Poddar
We need "tbclk" clock data for the functioning of ehrpwm module. Hence, populating the required clock information in clock dts file.
Signed-off-by Sourav Poddar <[email protected]>--- arch/arm/boot/dts/am43xx-clocks.dtsi | 48 ++++++++++++++++++++++++++++++++++ drivers/clk/ti/clk-43xx.c | 6 +++++ 2 files changed, 54 insertions(+)arch/arm/boot/dts/am43xx-clocks.dtsi +0
-0
arch/arm/boot/dts/am43xx-clocks.dtsi line 93
Quoted 7 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +4
-0@@ -87,6 +87,54 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_tbclk: ehrpwm0_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock";
Should be ti,gate-clock.
arch/arm/boot/dts/am43xx-clocks.dtsi line 95
Quoted 2 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +2
-0+ clocks = <&dpll_per_m2_ck>; + bit-shift = <0>;
Should be ti,bit-shift.
arch/arm/boot/dts/am43xx-clocks.dtsi line 96
Quoted 1 line
arch/arm/boot/dts/am43xx-clocks.dtsi +1
-0+ reg = <0x44e10664 0x4>;
Should be reg = <0x664>. Mainline kernel uses offsets for clock data, not absolute register addresses.
Similar comments for the rest of the patch.
-Tero
Quoted 62 lines
arch/arm/boot/dts/am43xx-clocks.dtsi +41
-0+ }; + + ehrpwm1_tbclk: ehrpwm1_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <1>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <2>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <3>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <4>; + reg = <0x44e10664 0x4>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk at 44e10664 { + #clock-cells = <0>; + compatible = "gate-clock"; + clocks = <&dpll_per_m2_ck>; + bit-shift = <5>; + reg = <0x44e10664 0x4>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck {drivers/clk/ti/clk-43xx.c +6
-0@@ -105,6 +105,12 @@ static struct ti_dt_clk am43xx_clks[] = {DT_CLK (NULL ,"func_12m_clk" ,"func_12m_clk" ),DT_CLK (NULL ,"vtp_clk_div" ,"vtp_clk_div" ),DT_CLK (NULL ,"usbphy_32khz_clkmux" ,"usbphy_32khz_clkmux" ), +DT_CLK ("48300200.ehrpwm" ,"tbclk" ,"ehrpwm0_tbclk" ), +DT_CLK ("48302200.ehrpwm" ,"tbclk" ,"ehrpwm1_tbclk" ), +DT_CLK ("48304200.ehrpwm" ,"tbclk" ,"ehrpwm2_tbclk" ), +DT_CLK ("48306200.ehrpwm" ,"tbclk" ,"ehrpwm3_tbclk" ), +DT_CLK ("48308200.ehrpwm" ,"tbclk" ,"ehrpwm4_tbclk" ), +DT_CLK ("4830a200.ehrpwm" ,"tbclk" ,"ehrpwm5_tbclk" ), { .node_name = NULL }, };