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ARM: dts: imx27-phytec-phycore-rdk: Remove duplicate entries for USB PHY

PATCH New Alexander Shiyan 4 participants 17 messages Apr 26, 2014 – Apr 29, 2014

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Alexander Shiyan

author
#0 lore raw

PATCH 1/8 ARM: dts: imx27-phytec-phycore-rdk: Remove duplicate entries for USB PHY

"compatible", "#address-cells" and "#size-cells" for USB PHY are already described in the SOM DTS. Remove these duplicate entries.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 4 ----
 1 file changed, 4 deletions(-)
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +0 -4
index 0875327..ac18ccf 100644
@@ -39,10 +39,6 @@
 	};
 
 	usbphy {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		usbphy2: usbphy at 2 {
 			compatible = "usb-nop-xceiv";
 			reg = <0>;
Signature · 1 line
1.8.3.2
author
#1 lore raw

PATCH 2/8 ARM: dts: imx27-phytec-phycore-som: Fix active level for FEC reset

FEC reset GPIO is active low. Fix this typo.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +1 -1
index 32cc7dac9a..93482e9 100644
@@ -182,7 +182,7 @@
 
 &fec {
 	phy-mode = "mii";
-	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
 	phy-supply = <&reg_3v3>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
Signature · 1 line
1.8.3.2
author
#2 lore raw

PATCH 3/8 ARM: dts: imx27-phytec-phycore-som: Disable PM pins for USB OTG

In reply to Alexander Shiyan

USB PWR and OC pins are used as GPIOs for different purposes, so add "disable-over-current" property for OTG node to indicate this.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +1 -0
index 93482e9..b81796c 100644
@@ -323,6 +323,7 @@
 	phy_type = "ulpi";
 	fsl,usbphy = <&usbphy0>;
 	vbus-supply = <&sw3_reg>;
+	disable-over-current;
 	status = "okay";
 };
Signature · 1 line
1.8.3.2
author
#3 lore raw

PATCH 4/8 ARM: dts: imx: Remove excess entries for PMIC

In reply to Alexander Shiyan

This patch removes excess "#address-cells" and "#size-cells" entries for PMIC, since these entries is not used.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-pdk.dts                 | 2 --
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 2 --
 arch/arm/boot/dts/imx51-babbage.dts             | 2 --
 3 files changed, 6 deletions(-)
arch/arm/boot/dts/imx27-pdk.dts +0 -2
index 764cf79..4c31771 100644
@@ -42,8 +42,6 @@
 	status = "okay";
 
 	pmic: mc13783 at 0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
 		compatible = "fsl,mc13783";
 		reg = <0>;
 		spi-cs-high;
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +0 -2
index b81796c..31e9f70 100644
@@ -80,8 +80,6 @@
 	status = "okay";
 
 	pmic: mc13783 at 0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
 		compatible = "fsl,mc13783";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
arch/arm/boot/dts/imx51-babbage.dts +0 -2
index e9ce0c0..89470bf 100644
@@ -191,8 +191,6 @@
 	status = "okay";
 
 	pmic: mc13892 at 0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
 		compatible = "fsl,mc13892";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
Signature · 1 line
1.8.3.2
author
#4 lore raw

PATCH 5/8 ARM: dts: imx27-phytec-phycore-rdk: Add CSI enable switch

In reply to Alexander Shiyan

This patch adds a GPIO fixed regulator which used on RDK to enable CSI bus.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +20 -0
index ac18ccf..72c773e 100644
@@ -38,6 +38,20 @@
 		};
 	};
 
+	regulators {
+		regulator at 2 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_csien>;
+			reg = <2>;
+			regulator-name = "CSI_EN";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+			regulator-always-on;
+		};
+	};
+
 	usbphy {
 		usbphy2: usbphy at 2 {
 			compatible = "usb-nop-xceiv";

@@ -83,6 +97,12 @@
 
 &iomuxc {
 	imx27_phycore_rdk {
+		pinctrl_csien: csiengrp {
+			fsl,pins = <
+				MX27_PAD_USB_OC_B__GPIO2_24 0x0
+			>;
+		};
+
 		pinctrl_cspi1cs1: cspi1cs1grp {
 			fsl,pins = <
 				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
Signature · 1 line
1.8.3.2
author
#5 lore raw

PATCH 6/8 ARM: dts: imx27-phytec-phycore-rdk: Fix "reg" property for USBH2 PHY

In reply to Alexander Shiyan
Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +1 -1
index 72c773e..d0b693f 100644
@@ -55,7 +55,7 @@
 	usbphy {
 		usbphy2: usbphy at 2 {
 			compatible = "usb-nop-xceiv";
-			reg = <0>;
+			reg = <2>;
 			vcc-supply = <&reg_5v0>;
 			clocks = <&clks 0>;
 			clock-names = "main_clk";
Signature · 1 line
1.8.3.2
author
#6 lore raw

PATCH 7/8 ARM: dts: imx27: Trim node name for FEC

In reply to Alexander Shiyan

This patch reduce node name for FEC. Otherwise, the name for PHY is composed incorrectly.

Before:
fec 1002b000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.etherne:00, irq=-1)

After:
fec 1002b000.fec eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.fec-1:00, irq=-1)

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx27.dtsi +1 -1
index a75555c..377339e 100644
@@ -497,7 +497,7 @@
 				clocks = <&clks 38>;
 			};
 
-			fec: ethernet at 1002b000 {
+			fec: fec at 1002b000 {
 				compatible = "fsl,imx27-fec";
 				reg = <0x1002b000 0x4000>;
 				interrupts = <50>;
Signature · 1 line
1.8.3.2
#7 lore raw

PATCH 7/8 ARM: dts: imx27: Trim node name for FEC

Hello.

Quoted 19 lines · Alexander Shiyan

This patch reduce node name for FEC. Otherwise, the name for PHY is composed incorrectly.

Before:
fec 1002b000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.etherne:00, irq=-1)

After:
fec 1002b000.fec eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.fec-1:00, irq=-1)

Signed-off-by Alexander Shiyan <[email protected]>
---
  arch/arm/boot/dts/imx27.dtsi | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx27.dtsi +0 -0
index a75555c..377339e 100644

arch/arm/boot/dts/imx27.dtsi line 500

Quoted 5 lines
arch/arm/boot/dts/imx27.dtsi +1 -1
@@ -497,7 +497,7 @@
  				clocks = <&clks 38>;
  			};
 
-			fec: ethernet at 1002b000 {
+			fec: fec at 1002b000 {

The "ethernet" name complies to the ePAPR standard. Don't change it, please.

WBR, Sergei

author
#8 lore raw

Re: [PATCH 7/8] ARM: dts: imx27: Trim node name for FEC

Sat, 26 Apr 2014 20:32:18 +0400 ?? Sergei Shtylyov <[email protected]>:

Quoted 26 lines

Hello.

Quoted 22 lines · Alexander Shiyan

This patch reduce node name for FEC. Otherwise, the name for PHY is composed incorrectly.

Before:
fec 1002b000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.etherne:00, irq=-1)

After:
fec 1002b000.fec eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.fec-1:00, irq=-1)

Signed-off-by Alexander Shiyan <[email protected]>
---
  arch/arm/boot/dts/imx27.dtsi | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx27.dtsi +0 -0
index a75555c..377339e 100644
@@ -497,7 +497,7 @@
  				clocks = <&clks 38>;
  			};
Quoted 4 lines

arch/arm/boot/dts/imx27.dtsi line 500

Quoted 2 lines
arch/arm/boot/dts/imx27.dtsi +1 -1
-			fec: ethernet at 1002b000 {
+			fec: fec at 1002b000 {

The "ethernet" name complies to the ePAPR standard. Don't change it, please.

So this is ok?
mii_bus:phy_addr=1002b000.etherne:00

---

#9 lore raw

PATCH 7/8 ARM: dts: imx27: Trim node name for FEC

Hello.

Quoted 22 lines · Alexander Shiyan
Quoted 22 lines
Quoted 22 lines

This patch reduce node name for FEC. Otherwise, the name for PHY is composed incorrectly.

Before:
fec 1002b000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.etherne:00, irq=-1)

After:
fec 1002b000.fec eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.fec-1:00, irq=-1)

Signed-off-by Alexander Shiyan <[email protected]>
---
   arch/arm/boot/dts/imx27.dtsi | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx27.dtsi +0 -0
index a75555c..377339e 100644
@@ -497,7 +497,7 @@
   				clocks = <&clks 38>;
   			};
Quoted 7 lines
Quoted 4 lines

arch/arm/boot/dts/imx27.dtsi line 500

Quoted 2 lines
arch/arm/boot/dts/imx27.dtsi +1 -1
-			fec: ethernet at 1002b000 {
+			fec: fec at 1002b000 {

The "ethernet" name complies to the ePAPR standard. Don't change it, please.

So this is ok?
mii_bus:phy_addr=1002b000.etherne:00

    Why not? :-)

WBR, Sergei

author
#10 lore raw

Re: [PATCH 7/8] ARM: dts: imx27: Trim node name for FEC

Sat, 26 Apr 2014 20:54:11 +0400 ?? Sergei Shtylyov <[email protected]>:

Quoted 31 lines

Hello.

Quoted 26 lines · Alexander Shiyan
Quoted 26 lines
Quoted 19 lines

This patch reduce node name for FEC. Otherwise, the name for PHY is composed incorrectly.

Before:
fec 1002b000.ethernet eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.etherne:00, irq=-1)

After:
fec 1002b000.fec eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1002b000.fec-1:00, irq=-1)

Signed-off-by Alexander Shiyan <[email protected]>
---
   arch/arm/boot/dts/imx27.dtsi | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/imx27.dtsi +0 -0
index a75555c..377339e 100644

arch/arm/boot/dts/imx27.dtsi line 500

Quoted 5 lines
arch/arm/boot/dts/imx27.dtsi +1 -1
@@ -497,7 +497,7 @@
   				clocks = <&clks 38>;
   			};
 
-			fec: ethernet at 1002b000 {
+			fec: fec at 1002b000 {

The "ethernet" name complies to the ePAPR standard. Don't change it, please.

Quoted 4 lines
Quoted 2 lines

So this is ok?
mii_bus:phy_addr=1002b000.etherne:00

    Why not? :-)

OK if so. Shawn, please skip this one patch if all other looks OK.

---

author
#11 lore raw

PATCH 8/8 ARM: dts: imx27-phytec-phycore-*: Move "iomux" node to the bottom of file

In reply to Alexander Shiyan

This patch moves "iomux" node to the bottom of file. No functional changes.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts  | 234 ++++++++++++------------
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 176 +++++++++---------
 2 files changed, 205 insertions(+), 205 deletions(-)
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +117 -117
index d0b693f..07de457 100644
@@ -95,123 +95,6 @@
 	};
 };
 
-&iomuxc {
-	imx27_phycore_rdk {
-		pinctrl_csien: csiengrp {
-			fsl,pins = <
-				MX27_PAD_USB_OC_B__GPIO2_24 0x0
-			>;
-		};
-
-		pinctrl_cspi1cs1: cspi1cs1grp {
-			fsl,pins = <
-				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
-			>;
-		};
-
-		pinctrl_imxfb1: imxfbgrp {
-			fsl,pins = <
-				MX27_PAD_LD0__LD0 0x0
-				MX27_PAD_LD1__LD1 0x0
-				MX27_PAD_LD2__LD2 0x0
-				MX27_PAD_LD3__LD3 0x0
-				MX27_PAD_LD4__LD4 0x0
-				MX27_PAD_LD5__LD5 0x0
-				MX27_PAD_LD6__LD6 0x0
-				MX27_PAD_LD7__LD7 0x0
-				MX27_PAD_LD8__LD8 0x0
-				MX27_PAD_LD9__LD9 0x0
-				MX27_PAD_LD10__LD10 0x0
-				MX27_PAD_LD11__LD11 0x0
-				MX27_PAD_LD12__LD12 0x0
-				MX27_PAD_LD13__LD13 0x0
-				MX27_PAD_LD14__LD14 0x0
-				MX27_PAD_LD15__LD15 0x0
-				MX27_PAD_LD16__LD16 0x0
-				MX27_PAD_LD17__LD17 0x0
-				MX27_PAD_CLS__CLS 0x0
-				MX27_PAD_CONTRAST__CONTRAST 0x0
-				MX27_PAD_LSCLK__LSCLK 0x0
-				MX27_PAD_OE_ACD__OE_ACD 0x0
-				MX27_PAD_PS__PS 0x0
-				MX27_PAD_REV__REV 0x0
-				MX27_PAD_SPL_SPR__SPL_SPR 0x0
-				MX27_PAD_HSYNC__HSYNC 0x0
-				MX27_PAD_VSYNC__VSYNC 0x0
-			>;
-		};
-
-		pinctrl_i2c1: i2c1grp {
-			/* Add pullup to DATA line */
-			fsl,pins = <
-				MX27_PAD_I2C_DATA__I2C_DATA	0x1
-				MX27_PAD_I2C_CLK__I2C_CLK	0x0
-			>;
-		};
-
-		pinctrl_owire1: owire1grp {
-			fsl,pins = <
-				MX27_PAD_RTCK__OWIRE 0x0
-			>;
-		};
-
-		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <
-				MX27_PAD_SD2_CLK__SD2_CLK 0x0
-				MX27_PAD_SD2_CMD__SD2_CMD 0x0
-				MX27_PAD_SD2_D0__SD2_D0 0x0
-				MX27_PAD_SD2_D1__SD2_D1 0x0
-				MX27_PAD_SD2_D2__SD2_D2 0x0
-				MX27_PAD_SD2_D3__SD2_D3 0x0
-				MX27_PAD_SSI3_FS__GPIO3_28	0x0 /* WP */
-				MX27_PAD_SSI3_RXDAT__GPIO3_29	0x0 /* CD */
-			>;
-		};
-
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX27_PAD_UART1_TXD__UART1_TXD 0x0
-				MX27_PAD_UART1_RXD__UART1_RXD 0x0
-				MX27_PAD_UART1_CTS__UART1_CTS 0x0
-				MX27_PAD_UART1_RTS__UART1_RTS 0x0
-			>;
-		};
-
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX27_PAD_UART2_TXD__UART2_TXD 0x0
-				MX27_PAD_UART2_RXD__UART2_RXD 0x0
-				MX27_PAD_UART2_CTS__UART2_CTS 0x0
-				MX27_PAD_UART2_RTS__UART2_RTS 0x0
-			>;
-		};
-
-		pinctrl_usbh2: usbh2grp {
-			fsl,pins = <
-				MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
-				MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
-				MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
-				MX27_PAD_USBH2_STP__USBH2_STP 0x0
-				MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
-				MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
-				MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
-				MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
-				MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
-				MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
-				MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
-				MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
-			>;
-		};
-
-		pinctrl_weim: weimgrp {
-			fsl,pins = <
-				MX27_PAD_CS4_B__CS4_B		0x0 /* CS4 */
-				MX27_PAD_SD1_D1__GPIO5_19	0x0 /* CAN IRQ */
-			>;
-		};
-	};
-};
-
 &owire {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_owire1>;

@@ -318,3 +201,120 @@
 		fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
 	};
 };
+
+&iomuxc {
+	imx27_phycore_rdk {
+		pinctrl_csien: csiengrp {
+			fsl,pins = <
+				MX27_PAD_USB_OC_B__GPIO2_24		0x0
+			>;
+		};
+
+		pinctrl_cspi1cs1: cspi1cs1grp {
+			fsl,pins = <
+				MX27_PAD_CSPI1_SS1__GPIO4_27		0x0
+			>;
+		};
+
+		pinctrl_imxfb1: imxfbgrp {
+			fsl,pins = <
+				MX27_PAD_LD0__LD0			0x0
+				MX27_PAD_LD1__LD1			0x0
+				MX27_PAD_LD2__LD2			0x0
+				MX27_PAD_LD3__LD3			0x0
+				MX27_PAD_LD4__LD4			0x0
+				MX27_PAD_LD5__LD5			0x0
+				MX27_PAD_LD6__LD6			0x0
+				MX27_PAD_LD7__LD7			0x0
+				MX27_PAD_LD8__LD8			0x0
+				MX27_PAD_LD9__LD9			0x0
+				MX27_PAD_LD10__LD10			0x0
+				MX27_PAD_LD11__LD11			0x0
+				MX27_PAD_LD12__LD12			0x0
+				MX27_PAD_LD13__LD13			0x0
+				MX27_PAD_LD14__LD14			0x0
+				MX27_PAD_LD15__LD15			0x0
+				MX27_PAD_LD16__LD16			0x0
+				MX27_PAD_LD17__LD17			0x0
+				MX27_PAD_CLS__CLS			0x0
+				MX27_PAD_CONTRAST__CONTRAST		0x0
+				MX27_PAD_LSCLK__LSCLK			0x0
+				MX27_PAD_OE_ACD__OE_ACD			0x0
+				MX27_PAD_PS__PS				0x0
+				MX27_PAD_REV__REV			0x0
+				MX27_PAD_SPL_SPR__SPL_SPR		0x0
+				MX27_PAD_HSYNC__HSYNC			0x0
+				MX27_PAD_VSYNC__VSYNC			0x0
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			/* Use pullup for DATA line */
+			fsl,pins = <
+				MX27_PAD_I2C_DATA__I2C_DATA		0x1
+				MX27_PAD_I2C_CLK__I2C_CLK		0x0
+			>;
+		};
+
+		pinctrl_owire1: owire1grp {
+			fsl,pins = <
+				MX27_PAD_RTCK__OWIRE			0x0
+			>;
+		};
+
+		pinctrl_sdhc2: sdhc2grp {
+			fsl,pins = <
+				MX27_PAD_SD2_CLK__SD2_CLK		0x0
+				MX27_PAD_SD2_CMD__SD2_CMD		0x0
+				MX27_PAD_SD2_D0__SD2_D0			0x0
+				MX27_PAD_SD2_D1__SD2_D1			0x0
+				MX27_PAD_SD2_D2__SD2_D2			0x0
+				MX27_PAD_SD2_D3__SD2_D3			0x0
+				MX27_PAD_SSI3_FS__GPIO3_28		0x0 /* WP */
+				MX27_PAD_SSI3_RXDAT__GPIO3_29		0x0 /* CD */
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX27_PAD_UART1_TXD__UART1_TXD		0x0
+				MX27_PAD_UART1_RXD__UART1_RXD		0x0
+				MX27_PAD_UART1_CTS__UART1_CTS		0x0
+				MX27_PAD_UART1_RTS__UART1_RTS		0x0
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX27_PAD_UART2_TXD__UART2_TXD		0x0
+				MX27_PAD_UART2_RXD__UART2_RXD		0x0
+				MX27_PAD_UART2_CTS__UART2_CTS		0x0
+				MX27_PAD_UART2_RTS__UART2_RTS		0x0
+			>;
+		};
+
+		pinctrl_usbh2: usbh2grp {
+			fsl,pins = <
+				MX27_PAD_USBH2_CLK__USBH2_CLK		0x0
+				MX27_PAD_USBH2_DIR__USBH2_DIR		0x0
+				MX27_PAD_USBH2_NXT__USBH2_NXT		0x0
+				MX27_PAD_USBH2_STP__USBH2_STP		0x0
+				MX27_PAD_CSPI2_SCLK__USBH2_DATA0	0x0
+				MX27_PAD_CSPI2_MOSI__USBH2_DATA1	0x0
+				MX27_PAD_CSPI2_MISO__USBH2_DATA2	0x0
+				MX27_PAD_CSPI2_SS1__USBH2_DATA3		0x0
+				MX27_PAD_CSPI2_SS2__USBH2_DATA4		0x0
+				MX27_PAD_CSPI1_SS2__USBH2_DATA5		0x0
+				MX27_PAD_CSPI2_SS0__USBH2_DATA6		0x0
+				MX27_PAD_USBH2_DATA7__USBH2_DATA7	0x0
+			>;
+		};
+
+		pinctrl_weim: weimgrp {
+			fsl,pins = <
+				MX27_PAD_CS4_B__CS4_B			0x0 /* CS4 */
+				MX27_PAD_SD1_D1__GPIO5_19		0x0 /* CAN IRQ */
+			>;
+		};
+	};
+};
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +88 -88

185 lines not on this page · raw message

Signature · 1 line
1.8.3.2
maintainer
#12 lore raw

PATCH 8/8 ARM: dts: imx27-phytec-phycore-*: Move "iomux" node to the bottom of file

Quoted 2 lines · Alexander Shiyan

This patch moves "iomux" node to the bottom of file. No functional changes.

Why? The nodes are (at least should be) sorted alphabetically.

Sascha

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
author
#13 lore raw

Re: [PATCH 8/8] ARM: dts: imx27-phytec-phycore-*: Move "iomux" node to the bottom of file

Sat, 26 Apr 2014 21:09:35 +0200 ?? Sascha Hauer <[email protected]>:

Quoted 5 lines · Alexander Shiyan
Quoted 2 lines

This patch moves "iomux" node to the bottom of file. No functional changes.

Why? The nodes are (at least should be) sorted alphabetically.

Pin definitions look better in one place, at the bottom. As far as I know, Shawn supported this position.

---

maintainer
#14 lore raw

PATCH 8/8 ARM: dts: imx27-phytec-phycore-*: Move "iomux" node to the bottom of file

Quoted 9 lines · Alexander Shiyan

Sat, 26 Apr 2014 21:09:35 +0200 ?? Sascha Hauer <[email protected]>:

Quoted 5 lines · Alexander Shiyan
Quoted 2 lines

This patch moves "iomux" node to the bottom of file. No functional changes.

Why? The nodes are (at least should be) sorted alphabetically.

Pin definitions look better in one place, at the bottom. As far as I know, Shawn supported this position.

If that's the way we want to go then ok. I wasn't aware of this.

Sascha

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
#15 lore raw

PATCH 8/8 ARM: dts: imx27-phytec-phycore-*: Move "iomux" node to the bottom of file

In reply to Alexander Shiyan
Quoted 1 line · Alexander Shiyan

This patch moves "iomux" node to the bottom of file.

Let's only do this for new files, and save the churn on the existing files.

Shawn

Quoted 7 lines

No functional changes.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts  | 234 ++++++++++++------------
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 176 +++++++++---------
 2 files changed, 205 insertions(+), 205 deletions(-)