MCPM backend for Exynos5420

Add machine-dependent MCPM call-backs for Exynos5420. These are used to power up/down the secondary CPUs during boot, shutdown, s2r and switching.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

---
 arch/arm/mach-exynos/Kconfig       |   8 +
 arch/arm/mach-exynos/Makefile      |   2 +
 arch/arm/mach-exynos/mcpm-exynos.c | 321 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h    |   3 +
 4 files changed, 334 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

arch/arm/mach-exynos/Kconfig +8 -0

index fc8bf18..1602abc 100644
@@ -110,4 +110,12 @@ config SOC_EXYNOS5440
 
 endmenu
 
+config EXYNOS5420_MCPM
+       bool "Exynos5420 Multi-Cluster PM support"
+       depends on MCPM && SOC_EXYNOS5420
+       select ARM_CCI
+       help
+         This is needed to provide CPU and cluster power management
+         on Exynos5420 implementing big.LITTLE.
+
 endif

arch/arm/mach-exynos/Makefile +2 -0

index a656dbe..01bc9b9 100644
@@ -29,3 +29,5 @@ obj-$(CONFIG_ARCH_EXYNOS)     += firmware.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o            :=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_EXYNOS5420_MCPM)  += mcpm-exynos.o

arch/arm/mach-exynos/mcpm-exynos.c new file +11 -0

new file mode 100644
index 0000000..f9977bf
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * arch/arm/mach-exynos/mcpm-exynos.c
+ *
+ * Based on arch/arm/mach-vexpress/dcscb.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.

arch/arm/mach-exynos/mcpm-exynos.c new file +35 -0

+
+#include <asm/mcpm.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+#include <plat/cpu.h>
+
+#include "regs-pmu.h"
+#include "common.h"
+
+#define EXYNOS5420_CPUS_PER_CLUSTER    4
+#define EXYNOS5420_NR_CLUSTERS         2
+
+/* Secondary CPU entry point */
+#define REG_ENTRY_ADDR         (S5P_VA_SYSRAM_NS + 0x1C)
+
+/*
+ * The common v7_exit_coherency_flush API could not be used because of the
+ * Erratum 799270 workaround. This macro is the same as the common one (in
+ * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
+ */
+#define exynos_v7_exit_coherency_flush(level) \
+       asm volatile( \
+       "stmfd  sp!, {fp, ip}\n\t"\
+       "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR\n\t" \
+       "bic    r0, r0, #"__stringify(CR_C)"\n\t" \
+       "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
+       "isb\n\t"\
+       "bl     v7_flush_dcache_"__stringify(level)"\n\t" \
+       "clrex\n\t"\
+       "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
+       "bic    r0, r0, #(1 << 6)       @ disable local coherency\n\t" \
+       /* Dummy Load of a device register to avoid Erratum 799270 */ \
+       "ldr    r4, [%0]\n\t" \
+       "and    r4, r4, #0\n\t" \

arch/arm/mach-exynos/mcpm-exynos.c new file +15 -0

+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+       unsigned int tries = 100;
+       unsigned int val = 0;
+

arch/arm/mach-exynos/mcpm-exynos.c new file +32 -0

+                       return 0;
+
+               cpu_relax();
+       }
+       pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
+               enable ? "on" : "off");
+
+       return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+       unsigned int err;
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+               cluster >= EXYNOS5420_NR_CLUSTERS)
+               return -EINVAL;
+
+       /*
+        * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+        * variant exists, we need to disable IRQs manually here.
+        */
+       local_irq_disable();
+       arch_spin_lock(&exynos_mcpm_lock);
+
+       cpu_use_count[cpu][cluster]++;
+       if (cpu_use_count[cpu][cluster] == 1) {
+               bool was_cluster_down =
+                       __mcpm_cluster_state(cluster) == CLUSTER_DOWN;
+

arch/arm/mach-exynos/mcpm-exynos.c new file +36 -0

+       } else if (cpu_use_count[cpu][cluster] != 2) {
+               /*
+                * The only possible values are:
+                * 0 = CPU down
+                * 1 = CPU (still) up
+                * 2 = CPU requested to be up before it had a chance
+                *     to actually make itself down.
+                * Any other value is a bug.
+                */
+               BUG();
+       }
+
+       arch_spin_unlock(&exynos_mcpm_lock);
+       local_irq_enable();
+
+       return 0;
+}
+
+static void exynos_power_down(void)
+{
+       unsigned int mpidr, cpu, cluster;
+       bool last_man = false, skip_wfi = false;
+       unsigned int cpunr;
+
+       mpidr = read_cpuid_mpidr();
+       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+       cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       __mcpm_cpu_going_down(cpu, cluster);
+
+       arch_spin_lock(&exynos_mcpm_lock);

arch/arm/mach-exynos/mcpm-exynos.c new file +85 -0

+       } else if (cpu_use_count[cpu][cluster] == 1) {
+               /*
+                * A power_up request went ahead of us.
+                * Even if we do not want to shut this CPU down,
+                * the caller expects a certain state as if the WFI
+                * was aborted.  So let's continue with cache cleaning.
+                */
+               skip_wfi = true;
+       } else {
+               BUG();
+       }
+
+       if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+               arch_spin_unlock(&exynos_mcpm_lock);
+
+               /* Flush all cache levels for this cluster. */
+               exynos_v7_exit_coherency_flush(all);
+
+               /*
+                * Disable cluster-level coherency by masking
+                * incoming snoops and DVM messages:
+                */
+               cci_disable_port_by_cpu(mpidr);
+
+               __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+       } else {
+               arch_spin_unlock(&exynos_mcpm_lock);
+
+               /* Disable and flush the local CPU cache. */
+               exynos_v7_exit_coherency_flush(louis);
+       }
+
+       __mcpm_cpu_down(cpu, cluster);
+
+       /* Now we are prepared for power-down, do it: */
+       if (!skip_wfi)
+               wfi();
+
+       /* Not dead at this point?  Let our caller cope. */
+}
+
+static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+       unsigned int tries = 100;
+       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       /* Wait for the core state to be OFF */
+       while (tries--) {
+               if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+                       if ((exynos_cpu_power_state(cpunr) == 0))
+                               return 0; /* success: the CPU is halted */
+               }
+
+               /* Otherwise, wait and retry: */
+               msleep(1);
+       }
+
+       return -ETIMEDOUT; /* timeout */
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+       .power_up               = exynos_power_up,
+       .power_down             = exynos_power_down,
+       .power_down_finish      = exynos_power_down_finish,
+};
+
+static void __init exynos_mcpm_usage_count_init(void)
+{
+       unsigned int mpidr, cpu, cluster;
+
+       mpidr = read_cpuid_mpidr();
+       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       cpu_use_count[cpu][cluster] = 1;
+}
+

arch/arm/mach-exynos/mcpm-exynos.c line 21

Quoted 8 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +8 -0

+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/arm-cci.h>

Alphabetical order please.

Quoted 19 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +19 -0

+#define exynos_v7_exit_coherency_flush(level) \
+       asm volatile( \
+       "stmfd  sp!, {fp, ip}\n\t"\
+       "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR\n\t" \
+       "bic    r0, r0, #"__stringify(CR_C)"\n\t" \
+       "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
+       "isb\n\t"\
+       "bl     v7_flush_dcache_"__stringify(level)"\n\t" \
+       "clrex\n\t"\
+       "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
+       "bic    r0, r0, #(1 << 6)       @ disable local coherency\n\t" \
+       /* Dummy Load of a device register to avoid Erratum 799270 */ \
+       "ldr    r4, [%0]\n\t" \
+       "and    r4, r4, #0\n\t" \
+       "orr    r0, r0, r4\n\t" \
+       "mcr    p15, 0, r0, c1, c0, 1   @ set ACTLR\n\t" \
+       "isb\n\t" \
+       "dsb\n\t" \
+       "ldmfd  sp!, {fp, ip}" \

arch/arm/mach-exynos/mcpm-exynos.c line 66

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+       : \
+       : "Ir" (S5P_INFORM0) \
+       : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+         "r9", "r10", "lr", "memory")
+

Still investigating to see if can work around errata 799270 in a different fashion, will keep you posted.

Quoted 20 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +19 -0

+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+       unsigned int tries = 100;
+       unsigned int val = 0;
+
+       if (enable) {
+               exynos_cluster_powerup(cluster);
+               val = S5P_CORE_LOCAL_PWR_EN;
+       } else {

arch/arm/mach-exynos/mcpm-exynos.c line 91

Quoted 6 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +6 -0

+               exynos_cluster_powerdown(cluster);
+       }
+
+       /* Wait until cluster power control is applied */
+       while (tries--) {
+               if (exynos_cluster_power_state(cluster) == val)

Do you really need val ?

Quoted 37 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +36 -0

+                       return 0;
+
+               cpu_relax();
+       }
+       pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
+               enable ? "on" : "off");
+
+       return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+       unsigned int err;
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+               cluster >= EXYNOS5420_NR_CLUSTERS)
+               return -EINVAL;
+
+       /*
+        * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+        * variant exists, we need to disable IRQs manually here.
+        */
+       local_irq_disable();
+       arch_spin_lock(&exynos_mcpm_lock);
+
+       cpu_use_count[cpu][cluster]++;
+       if (cpu_use_count[cpu][cluster] == 1) {
+               bool was_cluster_down =
+                       __mcpm_cluster_state(cluster) == CLUSTER_DOWN;
+
+               /*
+                * Turn on the cluster (L2/COMMON) and then power on the cores.
+                * TODO: Turn off the clusters when all cores in the cluster
+                * are down to achieve significant power savings.

arch/arm/mach-exynos/mcpm-exynos.c line 133

Quoted 6 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +6 -0

+                */
+               if (was_cluster_down) {
+                       err = exynos_cluster_power_control(cluster, 1);
+                       if (err) {
+                               exynos_cluster_power_control(cluster, 0);
+                               return err;

You must not return without undoing what you should (irqs and locking).

arch/arm/mach-exynos/mcpm-exynos.c line 140

Quoted 8 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +7 -0

+                       }
+               }
+
+               exynos_cpu_powerup(cpunr);
+
+               /* CPU should be powered up there */
+               /* Also setup Cluster Power Sequence here */

Stale comment ?

Quoted 37 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +36 -0

+       } else if (cpu_use_count[cpu][cluster] != 2) {
+               /*
+                * The only possible values are:
+                * 0 = CPU down
+                * 1 = CPU (still) up
+                * 2 = CPU requested to be up before it had a chance
+                *     to actually make itself down.
+                * Any other value is a bug.
+                */
+               BUG();
+       }
+
+       arch_spin_unlock(&exynos_mcpm_lock);
+       local_irq_enable();
+
+       return 0;
+}
+
+static void exynos_power_down(void)
+{
+       unsigned int mpidr, cpu, cluster;
+       bool last_man = false, skip_wfi = false;
+       unsigned int cpunr;
+
+       mpidr = read_cpuid_mpidr();
+       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+       cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       __mcpm_cpu_going_down(cpu, cluster);
+
+       arch_spin_lock(&exynos_mcpm_lock);

arch/arm/mach-exynos/mcpm-exynos.c line 186

Quoted 10 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +10 -0

+       BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+       cpu_use_count[cpu][cluster]--;
+       if (cpu_use_count[cpu][cluster] == 0) {
+               int cnt = 0, i;
+
+               exynos_cpu_powerdown(cpunr);
+               for (i = 0; i < EXYNOS5420_CPUS_PER_CLUSTER; i++)
+                       cnt += cpu_use_count[i][cluster];
+               if (cnt == 0)
+                       last_man = true;

                for (i = 0; i < EXYNOS5420_CPUS_PER_CLUSTER; i++)
                        if (cpu_use_count[i][cluster])
                                break;
                last_man = i == EXYNOS5420_CPUS_PER_CLUSTER;

and get rid of cnt.

Quoted 91 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +90 -0

+       } else if (cpu_use_count[cpu][cluster] == 1) {
+               /*
+                * A power_up request went ahead of us.
+                * Even if we do not want to shut this CPU down,
+                * the caller expects a certain state as if the WFI
+                * was aborted.  So let's continue with cache cleaning.
+                */
+               skip_wfi = true;
+       } else {
+               BUG();
+       }
+
+       if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+               arch_spin_unlock(&exynos_mcpm_lock);
+
+               /* Flush all cache levels for this cluster. */
+               exynos_v7_exit_coherency_flush(all);
+
+               /*
+                * Disable cluster-level coherency by masking
+                * incoming snoops and DVM messages:
+                */
+               cci_disable_port_by_cpu(mpidr);
+
+               __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+       } else {
+               arch_spin_unlock(&exynos_mcpm_lock);
+
+               /* Disable and flush the local CPU cache. */
+               exynos_v7_exit_coherency_flush(louis);
+       }
+
+       __mcpm_cpu_down(cpu, cluster);
+
+       /* Now we are prepared for power-down, do it: */
+       if (!skip_wfi)
+               wfi();
+
+       /* Not dead at this point?  Let our caller cope. */
+}
+
+static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+       unsigned int tries = 100;
+       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       /* Wait for the core state to be OFF */
+       while (tries--) {
+               if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+                       if ((exynos_cpu_power_state(cpunr) == 0))
+                               return 0; /* success: the CPU is halted */
+               }
+
+               /* Otherwise, wait and retry: */
+               msleep(1);
+       }
+
+       return -ETIMEDOUT; /* timeout */
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+       .power_up               = exynos_power_up,
+       .power_down             = exynos_power_down,
+       .power_down_finish      = exynos_power_down_finish,
+};
+
+static void __init exynos_mcpm_usage_count_init(void)
+{
+       unsigned int mpidr, cpu, cluster;
+
+       mpidr = read_cpuid_mpidr();
+       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       cpu_use_count[cpu][cluster] = 1;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{

arch/arm/mach-exynos/mcpm-exynos.c line 281

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+       asm volatile ("\n"
+       "cmp    r0, #1\n"
+       "bxne   lr\n"
+       "b      cci_enable_port_for_self");
+}

How many times are we going to duplicate this function before we decide to move it to a common header ?

arch/arm/mach-exynos/mcpm-exynos.c line 288

Quoted 7 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +6 -0

+static int __init exynos_mcpm_init(void)
+{
+       int ret = 0;
+
+       if (!soc_is_exynos5420())
+               return -ENODEV;

I do not particularly like these soc_is* stubs, but it is just a matter of taste.

Thanks,
Lorenzo

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{

Quoted 8 lines

arch/arm/mach-exynos/mcpm-exynos.c line 281

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+       asm volatile ("\n"
+       "cmp    r0, #1\n"
+       "bxne   lr\n"
+       "b      cci_enable_port_for_self");
+}

How many times are we going to duplicate this function before we decide to move it to a common header ?

I see this being used in arch/arm/mach-vexpress/tc2_pm.c (where I copied it from for exynos) and arch/arm/mach-vexpress/dcscb.c. A common function named "mcpm_default_power_up_setup" in the mcpm header would be acceptable ?

Quoted 13 lines · Abhilash Kesavan

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{

Quoted 8 lines

arch/arm/mach-exynos/mcpm-exynos.c line 281

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+       asm volatile ("\n"
+       "cmp    r0, #1\n"
+       "bxne   lr\n"
+       "b      cci_enable_port_for_self");
+}

How many times are we going to duplicate this function before we decide to move it to a common header ?

Quoted 4 lines

I see this being used in arch/arm/mach-vexpress/tc2_pm.c (where I copied it from for exynos) and arch/arm/mach-vexpress/dcscb.c. A common function named "mcpm_default_power_up_setup" in the mcpm header would be acceptable ?

Not necessarily.

First of all, this can't be a static inline as we need a pointer to it. And moving this to a header would create multiple instances of the same function in a multiplatform build for example.

Furthermore, this can't be called "default_power_up_setup" as this is specific to systems with a CCI.

It is true that the code in dcscb_setup.S does the same thing as this 3-line inline assembly, but the former is heavily commented and may serve as an example template for platforms that may require something more sophisticated here.

There are other patterns that seem to emerge as more MCPM backends are being submitted. I'm making a list of them and I intend to address such duplications after those backends do hit mainline.

Nicolas

Hi Nicolas,

Quoted 28 lines · Nicolas Pitre

Quoted 13 lines · Abhilash Kesavan

Quoted 5 lines

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{

Quoted 8 lines

arch/arm/mach-exynos/mcpm-exynos.c line 281

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+       asm volatile ("\n"
+       "cmp    r0, #1\n"
+       "bxne   lr\n"
+       "b      cci_enable_port_for_self");
+}

How many times are we going to duplicate this function before we decide to move it to a common header ?

Quoted 4 lines

I see this being used in arch/arm/mach-vexpress/tc2_pm.c (where I copied it from for exynos) and arch/arm/mach-vexpress/dcscb.c. A common function named "mcpm_default_power_up_setup" in the mcpm header would be acceptable ?

Not necessarily.

First of all, this can't be a static inline as we need a pointer to it. And moving this to a header would create multiple instances of the same function in a multiplatform build for example.

Furthermore, this can't be called "default_power_up_setup" as this is specific to systems with a CCI.

Add machine-dependent MCPM call-backs for Exynos5420. These are used to power up/down the secondary CPUs during boot, shutdown, s2r and switching.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

arch/arm/mach-exynos/mcpm-exynos.c new file +32 -0

+	}
+
+	/* Wait until cluster power control is applied */
+	while (tries--) {
+		if (exynos_cluster_power_state(cluster) == val)
+			return 0;
+
+		cpu_relax();
+	}
+	pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
+		enable ? "on" : "off");
+
+	return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+	unsigned int err;
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+		cluster >= EXYNOS5420_NR_CLUSTERS)
+		return -EINVAL;
+
+	/*
+	 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+	 * variant exists, we need to disable IRQs manually here.
+	 */
+	local_irq_disable();
+	arch_spin_lock(&exynos_mcpm_lock);
+

arch/arm/mach-exynos/mcpm-exynos.c new file +36 -0

+	} else if (cpu_use_count[cpu][cluster] != 2) {
+		/*
+		 * The only possible values are:
+		 * 0 = CPU down
+		 * 1 = CPU (still) up
+		 * 2 = CPU requested to be up before it had a chance
+		 *     to actually make itself down.
+		 * Any other value is a bug.
+		 */
+		BUG();
+	}
+
+	arch_spin_unlock(&exynos_mcpm_lock);
+	local_irq_enable();
+
+	return 0;
+}
+
+static void exynos_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool last_man = false, skip_wfi = false;
+	unsigned int cpunr;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+	cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	arch_spin_lock(&exynos_mcpm_lock);

Quoted 8 lines · Abhilash Kesavan

Add machine-dependent MCPM call-backs for Exynos5420. These are used to power up/down the secondary CPUs during boot, shutdown, s2r and switching.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

Small comments below.

arch/arm/mach-exynos/mcpm-exynos.c line 86

Quoted 10 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +10 -0

+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+     unsigned int tries = 100;
+     unsigned int val = 0;
+
+     if (enable) {
+             exynos_cluster_powerup(cluster);
+             val = S5P_CORE_LOCAL_PWR_EN;
+     } else {
+             exynos_cluster_powerdown(cluster);

It would be clearer if you have "val = 0" here instead so it looks symetric.

Quoted 38 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +37 -0

+     }
+
+     /* Wait until cluster power control is applied */
+     while (tries--) {
+             if (exynos_cluster_power_state(cluster) == val)
+                     return 0;
+
+             cpu_relax();
+     }
+     pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
+             enable ? "on" : "off");
+
+     return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+     unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+     unsigned int err;
+
+     pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+     if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+             cluster >= EXYNOS5420_NR_CLUSTERS)
+             return -EINVAL;
+
+     /*
+      * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+      * variant exists, we need to disable IRQs manually here.
+      */
+     local_irq_disable();
+     arch_spin_lock(&exynos_mcpm_lock);
+
+     cpu_use_count[cpu][cluster]++;
+     if (cpu_use_count[cpu][cluster] == 1) {
+             bool was_cluster_down =
+                     __mcpm_cluster_state(cluster) == CLUSTER_DOWN;
+

arch/arm/mach-exynos/mcpm-exynos.c line 128

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+             /*
+              * Turn on the cluster (L2/COMMON) and then power on the cores.
+              * TODO: Turn off the clusters when all cores in the cluster
+              * are down to achieve significant power savings.
+              */

This TODO comment should be moved in exynos_power_down() were last_man is determined to be true.

arch/arm/mach-exynos/mcpm-exynos.c line 133

Quoted 6 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+             if (was_cluster_down) {
+                     err = exynos_cluster_power_control(cluster, 1);
+                     if (err) {
+                             exynos_cluster_power_control(cluster, 0);
+                             return err;

The lock is still held.

To make the code clearer, you should do:

                        if (!err)
                                exynos_cpu_powerup(cpunr);

and return err at the end.

arch/arm/mach-exynos/mcpm-exynos.c line 140

Quoted 8 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +7 -0

+                     }
+             }
+
+             exynos_cpu_powerup(cpunr);
+
+             /* CPU should be powered up there */
+             /* Also setup Cluster Power Sequence here */

Both comments are wrong. The CPU is not necessarily powered up yet at this point, and "Cluster Power Sequence" (whatever that is) should not happen here but in the callback provided to mcpm_sync_init().

Quoted 37 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +36 -0

+     } else if (cpu_use_count[cpu][cluster] != 2) {
+             /*
+              * The only possible values are:
+              * 0 = CPU down
+              * 1 = CPU (still) up
+              * 2 = CPU requested to be up before it had a chance
+              *     to actually make itself down.
+              * Any other value is a bug.
+              */
+             BUG();
+     }
+
+     arch_spin_unlock(&exynos_mcpm_lock);
+     local_irq_enable();
+
+     return 0;
+}
+
+static void exynos_power_down(void)
+{
+     unsigned int mpidr, cpu, cluster;
+     bool last_man = false, skip_wfi = false;
+     unsigned int cpunr;
+
+     mpidr = read_cpuid_mpidr();
+     cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+     cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+     cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+     pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+     BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                     cluster >= EXYNOS5420_NR_CLUSTERS);
+
+     __mcpm_cpu_going_down(cpu, cluster);
+
+     arch_spin_lock(&exynos_mcpm_lock);

arch/arm/mach-exynos/mcpm-exynos.c line 186

Quoted 10 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +10 -0

+     BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+     cpu_use_count[cpu][cluster]--;
+     if (cpu_use_count[cpu][cluster] == 0) {
+             int cnt = 0, i;
+
+             exynos_cpu_powerdown(cpunr);
+             for (i = 0; i < EXYNOS5420_CPUS_PER_CLUSTER; i++)
+                     cnt += cpu_use_count[i][cluster];
+             if (cnt == 0)
+                     last_man = true;

I think Lorenzo commented on this code block already.

Otherwise it is almost there.

Nicolas

arch/arm/mach-exynos/mcpm-exynos.c new file +120 -0

+               /* Flush all cache levels for this cluster. */
+               exynos_v7_exit_coherency_flush(all);
+
+               /*
+                * Disable cluster-level coherency by masking
+                * incoming snoops and DVM messages:
+                */
+               cci_disable_port_by_cpu(mpidr);
+
+               __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+       } else {
+               arch_spin_unlock(&exynos_mcpm_lock);
+
+               /* Disable and flush the local CPU cache. */
+               exynos_v7_exit_coherency_flush(louis);
+       }
+
+       __mcpm_cpu_down(cpu, cluster);
+
+       /* Now we are prepared for power-down, do it: */
+       if (!skip_wfi)
+               wfi();
+
+       /* Not dead at this point?  Let our caller cope. */
+}
+
+static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+       unsigned int tries = 100;
+       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       /* Wait for the core state to be OFF */
+       while (tries--) {
+               if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+                       if ((exynos_cpu_power_state(cpunr) == 0))
+                               return 0; /* success: the CPU is halted */
+               }
+
+               /* Otherwise, wait and retry: */
+               msleep(1);
+       }
+
+       return -ETIMEDOUT; /* timeout */
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+       .power_up               = exynos_power_up,
+       .power_down             = exynos_power_down,
+       .power_down_finish      = exynos_power_down_finish,
+};
+
+static void __init exynos_mcpm_usage_count_init(void)
+{
+       unsigned int mpidr, cpu, cluster;
+
+       mpidr = read_cpuid_mpidr();
+       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       cpu_use_count[cpu][cluster] = 1;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{
+       asm volatile ("\n"
+       "cmp    r0, #1\n"
+       "bxne   lr\n"
+       "b      cci_enable_port_for_self");
+}
+
+static int __init exynos_mcpm_init(void)
+{
+       int ret = 0;
+
+       if (!soc_is_exynos5420())
+               return -ENODEV;
+
+       if (!cci_probed())
+               return -ENODEV;
+
+       /*
+        * To increase the stability of KFC reset we need to program
+        * the PMU SPARE3 register
+        */
+       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+
+       exynos_mcpm_usage_count_init();
+
+       ret = mcpm_platform_register(&exynos_power_ops);
+       if (!ret)
+               ret = mcpm_sync_init(exynos_pm_power_up_setup);
+       if (ret)
+               return ret;
+
+       mcpm_smp_set_ops();
+
+       pr_info("Exynos MCPM support installed\n");
+
+       /*
+        * Future entries into the kernel can now go
+        * through the cluster entry vectors.
+        */
+       __raw_writel(virt_to_phys(mcpm_entry_point),
+               REG_ENTRY_ADDR);
+
+       return ret;
+}
+
+early_initcall(exynos_mcpm_init);

arch/arm/mach-exynos/regs-pmu.h +3 -1

index 6685ebf..f44d318 100644
@@ -38,6 +38,7 @@
 #define S5P_INFORM5                            S5P_PMUREG(0x0814)
 #define S5P_INFORM6                            S5P_PMUREG(0x0818)
 #define S5P_INFORM7                            S5P_PMUREG(0x081C)
+#define S5P_PMU_SPARE3                         S5P_PMUREG(0x090C)
 
 #define S5P_ARM_CORE0_LOWPWR                   S5P_PMUREG(0x1000)
 #define S5P_DIS_IRQ_CORE0                      S5P_PMUREG(0x1004)

@@ -325,4 +326,6 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION                           (1 << 4)
 
+#define EXYNOS5420_SWRESET_KFC_SEL                             0x3
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
--

1.8.3.2

On Sat, Apr 26, 2014 at 05:05:47PM +0100, Abhilash Kesavan wrote:

[...]

arch/arm/mach-exynos/mcpm-exynos.c line 201

Quoted 3 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +3 -0

+       if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+               arch_spin_unlock(&exynos_mcpm_lock);
+

I missed it on first review, but you do need to disable L2 prefetching on A15 here as we do in TC2 (tc2_pm.c), this power down procedure is not compliant otherwise.

Thanks,
Lorenzo

Quoted 143 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +120 -0

+               /* Flush all cache levels for this cluster. */
+               exynos_v7_exit_coherency_flush(all);
+
+               /*
+                * Disable cluster-level coherency by masking
+                * incoming snoops and DVM messages:
+                */
+               cci_disable_port_by_cpu(mpidr);
+
+               __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+       } else {
+               arch_spin_unlock(&exynos_mcpm_lock);
+
+               /* Disable and flush the local CPU cache. */
+               exynos_v7_exit_coherency_flush(louis);
+       }
+
+       __mcpm_cpu_down(cpu, cluster);
+
+       /* Now we are prepared for power-down, do it: */
+       if (!skip_wfi)
+               wfi();
+
+       /* Not dead at this point?  Let our caller cope. */
+}
+
+static int exynos_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+       unsigned int tries = 100;
+       unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       /* Wait for the core state to be OFF */
+       while (tries--) {
+               if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+                       if ((exynos_cpu_power_state(cpunr) == 0))
+                               return 0; /* success: the CPU is halted */
+               }
+
+               /* Otherwise, wait and retry: */
+               msleep(1);
+       }
+
+       return -ETIMEDOUT; /* timeout */
+}
+
+static const struct mcpm_platform_ops exynos_power_ops = {
+       .power_up               = exynos_power_up,
+       .power_down             = exynos_power_down,
+       .power_down_finish      = exynos_power_down_finish,
+};
+
+static void __init exynos_mcpm_usage_count_init(void)
+{
+       unsigned int mpidr, cpu, cluster;
+
+       mpidr = read_cpuid_mpidr();
+       cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+       cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+       pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+       BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+                       cluster >= EXYNOS5420_NR_CLUSTERS);
+
+       cpu_use_count[cpu][cluster] = 1;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{
+       asm volatile ("\n"
+       "cmp    r0, #1\n"
+       "bxne   lr\n"
+       "b      cci_enable_port_for_self");
+}
+
+static int __init exynos_mcpm_init(void)
+{
+       int ret = 0;
+
+       if (!soc_is_exynos5420())
+               return -ENODEV;
+
+       if (!cci_probed())
+               return -ENODEV;
+
+       /*
+        * To increase the stability of KFC reset we need to program
+        * the PMU SPARE3 register
+        */
+       __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+
+       exynos_mcpm_usage_count_init();
+
+       ret = mcpm_platform_register(&exynos_power_ops);
+       if (!ret)
+               ret = mcpm_sync_init(exynos_pm_power_up_setup);
+       if (ret)
+               return ret;
+
+       mcpm_smp_set_ops();
+
+       pr_info("Exynos MCPM support installed\n");
+
+       /*
+        * Future entries into the kernel can now go
+        * through the cluster entry vectors.
+        */
+       __raw_writel(virt_to_phys(mcpm_entry_point),
+               REG_ENTRY_ADDR);
+
+       return ret;
+}
+
+early_initcall(exynos_mcpm_init);

arch/arm/mach-exynos/regs-pmu.h +3 -1

index 6685ebf..f44d318 100644
@@ -38,6 +38,7 @@
 #define S5P_INFORM5                            S5P_PMUREG(0x0814)
 #define S5P_INFORM6                            S5P_PMUREG(0x0818)
 #define S5P_INFORM7                            S5P_PMUREG(0x081C)
+#define S5P_PMU_SPARE3                         S5P_PMUREG(0x090C)
 
 #define S5P_ARM_CORE0_LOWPWR                   S5P_PMUREG(0x1000)
 #define S5P_DIS_IRQ_CORE0                      S5P_PMUREG(0x1004)

@@ -325,4 +326,6 @@
 
 #define EXYNOS5_OPTION_USE_RETENTION                           (1 << 4)
 
+#define EXYNOS5420_SWRESET_KFC_SEL                             0x3
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
--

1.8.3.2

Add machine-dependent MCPM call-backs for Exynos5420. These are used to power up/down the secondary CPUs during boot, shutdown, s2r and switching.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

---
 arch/arm/mach-exynos/Kconfig       |    8 +
 arch/arm/mach-exynos/Makefile      |    2 +
 arch/arm/mach-exynos/mcpm-exynos.c |  345 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h    |    3 +
 4 files changed, 358 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

arch/arm/mach-exynos/Kconfig +8 -0

index 5c34dc2..138070e 100644
@@ -73,4 +73,12 @@ config SOC_EXYNOS5440
 
 endmenu
 
+config EXYNOS5420_MCPM
+	bool "Exynos5420 Multi-Cluster PM support"
+	depends on MCPM && SOC_EXYNOS5420
+	select ARM_CCI
+	help
+	  This is needed to provide CPU and cluster power management
+	  on Exynos5420 implementing big.LITTLE.
+
 endif

arch/arm/mach-exynos/Makefile +2 -0

index a656dbe..01bc9b9 100644
@@ -29,3 +29,5 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= firmware.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_EXYNOS5420_MCPM)	+= mcpm-exynos.o

arch/arm/mach-exynos/mcpm-exynos.c new file +113 -0

new file mode 100644
index 0000000..d0f7461
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * arch/arm/mach-exynos/mcpm-exynos.c
+ *
+ * Based on arch/arm/mach-vexpress/dcscb.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "regs-pmu.h"
+#include "common.h"
+
+#define EXYNOS5420_CPUS_PER_CLUSTER	4
+#define EXYNOS5420_NR_CLUSTERS		2
+
+/* Non-secure iRAM base address */
+static void __iomem *ns_sram_base_addr;
+
+/*
+ * The common v7_exit_coherency_flush API could not be used because of the
+ * Erratum 799270 workaround. This macro is the same as the common one (in
+ * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
+ */
+#define exynos_v7_exit_coherency_flush(level) \
+	asm volatile( \
+	"stmfd	sp!, {fp, ip}\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 0	@ get SCTLR\n\t" \
+	"bic	r0, r0, #"__stringify(CR_C)"\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 0	@ set SCTLR\n\t" \
+	"isb\n\t"\
+	"bl	v7_flush_dcache_"__stringify(level)"\n\t" \
+	"clrex\n\t"\
+	"mrc	p15, 0, r0, c1, c0, 1	@ get ACTLR\n\t" \
+	"bic	r0, r0, #(1 << 6)	@ disable local coherency\n\t" \
+	/* Dummy Load of a device register to avoid Erratum 799270 */ \
+	"ldr	r4, [%0]\n\t" \
+	"and	r4, r4, #0\n\t" \
+	"orr	r0, r0, r4\n\t" \
+	"mcr	p15, 0, r0, c1, c0, 1	@ set ACTLR\n\t" \
+	"isb\n\t" \
+	"dsb\n\t" \
+	"ldmfd	sp!, {fp, ip}" \
+	: \
+	: "Ir" (S5P_INFORM0) \
+	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+	  "r9", "r10", "lr", "memory")
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+
+#define exynos_cluster_unused(cluster) \
+	(!cpu_use_count[0][cluster] && \
+	 !cpu_use_count[1][cluster] && \
+	 !cpu_use_count[2][cluster] && \
+	 !cpu_use_count[3][cluster])
+
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+	unsigned int tries = 100;
+	unsigned int val;
+
+	if (enable) {
+		exynos_cluster_powerup(cluster);
+		val = S5P_CORE_LOCAL_PWR_EN;
+	} else {
+		exynos_cluster_powerdown(cluster);
+		val = 0;
+	}
+
+	/* Wait until cluster power control is applied */
+	while (tries--) {
+		if (exynos_cluster_power_state(cluster) == val)
+			return 0;
+
+		cpu_relax();
+	}
+	pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
+		enable ? "on" : "off");
+
+	return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+	int err = 0;
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+		cluster >= EXYNOS5420_NR_CLUSTERS)
+		return -EINVAL;
+
+	/*

arch/arm/mach-exynos/mcpm-exynos.c new file +61 -0

+
+		/*
+		 * Turn on the cluster (L2/COMMON) and then power on the
+		 * cores.
+		 */
+		if (was_cluster_down)
+			err = exynos_cluster_power_control(cluster, 1);
+
+		if (!err)
+			exynos_cpu_powerup(cpunr);
+		else
+			exynos_cluster_power_control(cluster, 0);
+	} else if (cpu_use_count[cpu][cluster] != 2) {
+		/*
+		 * The only possible values are:
+		 * 0 = CPU down
+		 * 1 = CPU (still) up
+		 * 2 = CPU requested to be up before it had a chance
+		 *     to actually make itself down.
+		 * Any other value is a bug.
+		 */
+		BUG();
+	}
+
+	arch_spin_unlock(&exynos_mcpm_lock);
+	local_irq_enable();
+
+	return err;
+}
+
+static void exynos_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	bool last_man = false, skip_wfi = false;
+	unsigned int cpunr;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+	cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+	BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+			cluster >= EXYNOS5420_NR_CLUSTERS);
+
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	arch_spin_lock(&exynos_mcpm_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	cpu_use_count[cpu][cluster]--;
+	if (cpu_use_count[cpu][cluster] == 0) {
+		exynos_cpu_powerdown(cpunr);
+
+		if (exynos_cluster_unused(cluster))
+			last_man = true;
+	} else if (cpu_use_count[cpu][cluster] == 1) {
+		/*
+		 * A power_up request went ahead of us.
+		 * Even if we do not want to shut this CPU down,
+		 * the caller expects a certain state as if the WFI
+		 * was aborted.  So let's continue with cache cleaning.

arch/arm/mach-exynos/mcpm-exynos.c new file +17 -0

+	if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		/* Flush all cache levels for this cluster. */
+		exynos_v7_exit_coherency_flush(all);
+
+		/*
+		 * Disable cluster-level coherency by masking
+		 * incoming snoops and DVM messages:
+		 */
+		cci_disable_port_by_cpu(mpidr);
+
+		__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+	} else {
+		arch_spin_unlock(&exynos_mcpm_lock);
+
+		if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {

arch/arm/mach-exynos/mcpm-exynos.c line 194

Quoted 4 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +4 -0

+     /*
+      * TODO: Turn off the clusters when all cores in the cluster
+      * are down to achieve significant power savings.
+      */

This comment should actually be located right after the
"if (exynos_cluster_unused(cluster))" above. That is where the cluster control should be applied, assuming it'll be effective only when WFI is executed.

Quoted 9 lines

arch/arm/mach-exynos/mcpm-exynos.c line 194

Quoted 4 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +4 -0

+     /*
+      * TODO: Turn off the clusters when all cores in the cluster
+      * are down to achieve significant power savings.
+      */

This comment should actually be located right after the
"if (exynos_cluster_unused(cluster))" above. That is where the cluster control should be applied, assuming it'll be effective only when WFI is executed.

Correct me if I'm wrong Samsung folks, but I thought it was not possible to apply cluster power control from a CPU within the cluster being powered down, i.e. a CPU in the other cluster must be the one to apply the cluster power control to power down the outbound cluster.

Quoted 9 lines

arch/arm/mach-exynos/mcpm-exynos.c line 194

Quoted 4 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +4 -0

+     /*
+      * TODO: Turn off the clusters when all cores in the cluster
+      * are down to achieve significant power savings.
+      */

This comment should actually be located right after the
"if (exynos_cluster_unused(cluster))" above. That is where the cluster control should be applied, assuming it'll be effective only when WFI is executed.

Correct me if I'm wrong Samsung folks, but I thought it was not possible to apply cluster power control from a CPU within the cluster being powered down, i.e. a CPU in the other cluster must be the one to apply the cluster power control to power down the outbound cluster.

-Andrew

Quoted 8 lines · Abhilash Kesavan

Add machine-dependent MCPM call-backs for Exynos5420. These are used to power up/down the secondary CPUs during boot, shutdown, s2r and switching.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

OK.... There is still a detail wrong. At least we are converging.

Quoted 154 lines

---
 arch/arm/mach-exynos/Kconfig       |    8 +
 arch/arm/mach-exynos/Makefile      |    2 +
 arch/arm/mach-exynos/mcpm-exynos.c |  345 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h    |    3 +
 4 files changed, 358 insertions(+)
 create mode 100644 arch/arm/mach-exynos/mcpm-exynos.c

arch/arm/mach-exynos/Kconfig +8 -0

index 5c34dc2..138070e 100644
@@ -73,4 +73,12 @@ config SOC_EXYNOS5440
 
 endmenu
 
+config EXYNOS5420_MCPM
+     bool "Exynos5420 Multi-Cluster PM support"
+     depends on MCPM && SOC_EXYNOS5420
+     select ARM_CCI
+     help
+       This is needed to provide CPU and cluster power management
+       on Exynos5420 implementing big.LITTLE.
+
 endif

arch/arm/mach-exynos/Makefile +2 -0

index a656dbe..01bc9b9 100644
@@ -29,3 +29,5 @@ obj-$(CONFIG_ARCH_EXYNOS)   += firmware.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o          :=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_EXYNOS5420_MCPM)        += mcpm-exynos.o

arch/arm/mach-exynos/mcpm-exynos.c new file +113 -0

new file mode 100644
index 0000000..d0f7461
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *           http://www.samsung.com
+ *
+ * arch/arm/mach-exynos/mcpm-exynos.c
+ *
+ * Based on arch/arm/mach-vexpress/dcscb.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+
+#include "regs-pmu.h"
+#include "common.h"
+
+#define EXYNOS5420_CPUS_PER_CLUSTER  4
+#define EXYNOS5420_NR_CLUSTERS               2
+
+/* Non-secure iRAM base address */
+static void __iomem *ns_sram_base_addr;
+
+/*
+ * The common v7_exit_coherency_flush API could not be used because of the
+ * Erratum 799270 workaround. This macro is the same as the common one (in
+ * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
+ */
+#define exynos_v7_exit_coherency_flush(level) \
+     asm volatile( \
+     "stmfd  sp!, {fp, ip}\n\t"\
+     "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR\n\t" \
+     "bic    r0, r0, #"__stringify(CR_C)"\n\t" \
+     "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
+     "isb\n\t"\
+     "bl     v7_flush_dcache_"__stringify(level)"\n\t" \
+     "clrex\n\t"\
+     "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
+     "bic    r0, r0, #(1 << 6)       @ disable local coherency\n\t" \
+     /* Dummy Load of a device register to avoid Erratum 799270 */ \
+     "ldr    r4, [%0]\n\t" \
+     "and    r4, r4, #0\n\t" \
+     "orr    r0, r0, r4\n\t" \
+     "mcr    p15, 0, r0, c1, c0, 1   @ set ACTLR\n\t" \
+     "isb\n\t" \
+     "dsb\n\t" \
+     "ldmfd  sp!, {fp, ip}" \
+     : \
+     : "Ir" (S5P_INFORM0) \
+     : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+       "r9", "r10", "lr", "memory")
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+
+#define exynos_cluster_unused(cluster) \
+     (!cpu_use_count[0][cluster] && \
+      !cpu_use_count[1][cluster] && \
+      !cpu_use_count[2][cluster] && \
+      !cpu_use_count[3][cluster])
+
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+     unsigned int tries = 100;
+     unsigned int val;
+
+     if (enable) {
+             exynos_cluster_powerup(cluster);
+             val = S5P_CORE_LOCAL_PWR_EN;
+     } else {
+             exynos_cluster_powerdown(cluster);
+             val = 0;
+     }
+
+     /* Wait until cluster power control is applied */
+     while (tries--) {
+             if (exynos_cluster_power_state(cluster) == val)
+                     return 0;
+
+             cpu_relax();
+     }
+     pr_warn("timed out waiting for cluster %u to power %s\n", cluster,
+             enable ? "on" : "off");
+
+     return -ETIMEDOUT;
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+     unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+     int err = 0;
+
+     pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+     if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+             cluster >= EXYNOS5420_NR_CLUSTERS)
+             return -EINVAL;
+
+     /*

arch/arm/mach-exynos/mcpm-exynos.c line 123

Quoted 10 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +10 -0

+      * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+      * variant exists, we need to disable IRQs manually here.
+      */
+     local_irq_disable();
+     arch_spin_lock(&exynos_mcpm_lock);
+
+     cpu_use_count[cpu][cluster]++;
+     if (cpu_use_count[cpu][cluster] == 1) {
+             bool was_cluster_down =
+                     __mcpm_cluster_state(cluster) == CLUSTER_DOWN;

This is racy. I probably made this comment already. The MCPM cluster state may change in mcpm-head.S where concurrency protection is achieved with a different mechanism.

What you should do instead is to redefine exynos_cluster_unused() into exynos_cluster_usecnt() and simply add all counts together. You could even have:

#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)

Yet, here you should use:

        bool was_cluster_down = (exynos_cluster_usecnt(cluster) == 1);

Quoted 69 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +68 -0

+
+             /*
+              * Turn on the cluster (L2/COMMON) and then power on the
+              * cores.
+              */
+             if (was_cluster_down)
+                     err = exynos_cluster_power_control(cluster, 1);
+
+             if (!err)
+                     exynos_cpu_powerup(cpunr);
+             else
+                     exynos_cluster_power_control(cluster, 0);
+     } else if (cpu_use_count[cpu][cluster] != 2) {
+             /*
+              * The only possible values are:
+              * 0 = CPU down
+              * 1 = CPU (still) up
+              * 2 = CPU requested to be up before it had a chance
+              *     to actually make itself down.
+              * Any other value is a bug.
+              */
+             BUG();
+     }
+
+     arch_spin_unlock(&exynos_mcpm_lock);
+     local_irq_enable();
+
+     return err;
+}
+
+static void exynos_power_down(void)
+{
+     unsigned int mpidr, cpu, cluster;
+     bool last_man = false, skip_wfi = false;
+     unsigned int cpunr;
+
+     mpidr = read_cpuid_mpidr();
+     cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+     cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+     cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+
+     pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+     BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                     cluster >= EXYNOS5420_NR_CLUSTERS);
+
+     __mcpm_cpu_going_down(cpu, cluster);
+
+     arch_spin_lock(&exynos_mcpm_lock);
+     BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+     cpu_use_count[cpu][cluster]--;
+     if (cpu_use_count[cpu][cluster] == 0) {
+             exynos_cpu_powerdown(cpunr);
+
+             if (exynos_cluster_unused(cluster))
+                     last_man = true;
+     } else if (cpu_use_count[cpu][cluster] == 1) {
+             /*
+              * A power_up request went ahead of us.
+              * Even if we do not want to shut this CPU down,
+              * the caller expects a certain state as if the WFI
+              * was aborted.  So let's continue with cache cleaning.
+              */
+             skip_wfi = true;
+     } else {
+             BUG();
+     }
+
+     /*

arch/arm/mach-exynos/mcpm-exynos.c line 194

Quoted 3 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +3 -0

+      * TODO: Turn off the clusters when all cores in the cluster
+      * are down to achieve significant power savings.
+      */

This comment should actually be located right after the
"if (exynos_cluster_unused(cluster))" above. That is where the cluster control should be applied, assuming it'll be effective only when WFI is executed.

Quoted 24 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +22 -0

+     if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+             arch_spin_unlock(&exynos_mcpm_lock);
+
+             /* Flush all cache levels for this cluster. */
+             exynos_v7_exit_coherency_flush(all);
+
+             /*
+              * Disable cluster-level coherency by masking
+              * incoming snoops and DVM messages:
+              */
+             cci_disable_port_by_cpu(mpidr);
+
+             __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+     } else {
+             arch_spin_unlock(&exynos_mcpm_lock);
+
+             if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+                     /*
+                      * On the Cortex-A15 we need to disable
+                      * L2 prefetching before flushing the cache.
+                      */
+                     asm volatile(

arch/arm/mach-exynos/mcpm-exynos.c line 221

Quoted 5 lines

arch/arm/mach-exynos/mcpm-exynos.c new file +5 -0

+                     "mcr    p15, 1, %0, c15, c0, 3\n\t"
+                     "isb\n\t"
+                     "dsb"
+                     : : "r" (0x400));
+             }

This doesn't belong here. That is for the last_man only to do, right before the "Flush all cache levels for this cluster" comment.

The rest looks fine to me.

Nicolas

Add a user interface to check the core and cluster status on Exynos5420. This can be utilized while debugging mcpm issues. cat /dev/bL_status will show the current power status of all the 8 cores along with the cluster.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

---

  arch/arm/mach-exynos/mcpm-exynos.c | 64 ++++++++++++++++++++++++++++++++++++++
  1 file changed, 64 insertions(+)

arch/arm/mach-exynos/mcpm-exynos.c +64 -0

index f9977bf..83428b0 100644
@@ -269,6 +269,53 @@ static void __init exynos_mcpm_usage_count_init(void)
  	cpu_use_count[cpu][cluster] = 1;
  }
 
+static size_t bL_check_status(char *info)
+{
+	size_t len = 0;
+	int i;
+
+	len += sprintf(&info[len], "\t0 1 2 3 L2\n");
+	len += sprintf(&info[len], "[A15]   ");
+	for (i = 0; i < 4; i++) {
+		len += sprintf(&info[len], "%d ",
+			(readl(EXYNOS_ARM_CORE_STATUS(i)) & 0x3) == 3 ? 1 : 0);
+	}
+	len += sprintf(&info[len], "%d\n",
+			(readl(EXYNOS_COMMON_STATUS(0)) & 0x3) == 3 ? 1 : 0);
+
+	len += sprintf(&info[len], "[A7]    ");
+	for (i = 4; i < 8; i++)
+		len += sprintf(&info[len], "%d ",
+			(readl(EXYNOS_ARM_CORE_STATUS(i)) & 0x3) == 3 ? 1 : 0);
+	len += sprintf(&info[len], "%d\n\n",
+			(readl(EXYNOS_COMMON_STATUS(1)) & 0x3) == 3 ? 1 : 0);
+
+	return len;
+}
+
+static ssize_t bL_status_read(struct file *file, char __user *buf,
+			size_t len, loff_t *pos)
+{
+	size_t count = 0;
+	char info[100];
+
+	count = bL_check_status(info);
+	if (count < 0)
+		return -EINVAL;
+
+	return simple_read_from_buffer(buf, len, pos, info, count);
+}
+
+static const struct file_operations bL_status_fops = {
+	.read		= bL_status_read,
+};
+
+static struct miscdevice bL_status_device = {
+	MISC_DYNAMIC_MINOR,
+	"bL_status",
+	&bL_status_fops
+};
+
  /*
   * Enable cluster-level coherency, in preparation for turning on the MMU.
   */

@@ -319,3 +366,20 @@ static int __init exynos_mcpm_init(void)
  }
 
  early_initcall(exynos_mcpm_init);
+
+static int __init exynos_bl_status_init(void)
+{
+	int ret;
+
+	if (!soc_is_exynos5420())
+		return -ENODEV;
+
+	ret = misc_register(&bL_status_device);
+	if (ret) {
+		pr_info("bl_status not available\n");
+		return ret;
+	}
+	return 0;
+}
+
+late_initcall(exynos_bl_status_init);

Quoted 6 lines · Abhilash Kesavan

Add a user interface to check the core and cluster status on Exynos5420. This can be utilized while debugging mcpm issues. cat /dev/bL_status will show the current power status of all the 8 cores along with the cluster.

Quoted 5 lines

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

---

Hi Abhilash,

I don't think you should add this file.

1. big Little is not exynos specific

2. /dev is not for the purpose of your patch

So I would recommend:

1. create a generic infra-structure for all the big.Little
2. and/or use debugfs

Furthermore, how is it usable ? Will you read the file every 2ms to check the cluster status, knowing it will be woken up by the read operation ?

Frankly speaking, it would make sense to add traces in mcpm.c (if they aren't already there - did not check).

Quoted 82 lines

  arch/arm/mach-exynos/mcpm-exynos.c | 64
++++++++++++++++++++++++++++++++++++++
  1 file changed, 64 insertions(+)

arch/arm/mach-exynos/mcpm-exynos.c +20 -0

index f9977bf..83428b0 100644
@@ -269,6 +269,53 @@ static void __init exynos_mcpm_usage_count_init(void)
        cpu_use_count[cpu][cluster] = 1;
  }
 
+static size_t bL_check_status(char *info)
+{
+       size_t len = 0;
+       int i;
+
+       len += sprintf(&info[len], "\t0 1 2 3 L2\n");
+       len += sprintf(&info[len], "[A15]   ");
+       for (i = 0; i < 4; i++) {
+               len += sprintf(&info[len], "%d ",
+                       (readl(EXYNOS_ARM_CORE_STATUS(i)) & 0x3) == 3 ? 1
 : 0);
+       }
+       len += sprintf(&info[len], "%d\n",
+                       (readl(EXYNOS_COMMON_STATUS(0)) & 0x3) == 3 ? 1 :
 0);
+
+       len += sprintf(&info[len], "[A7]    ");
+       for (i = 4; i < 8; i++)
+               len += sprintf(&info[len], "%d ",
+                       (readl(EXYNOS_ARM_CORE_STATUS(i)) & 0x3) == 3 ? 1
 : 0);
+       len += sprintf(&info[len], "%d\n\n",
+                       (readl(EXYNOS_COMMON_STATUS(1)) & 0x3) == 3 ? 1 :

0);

arch/arm/mach-exynos/mcpm-exynos.c +27 -0

+
+       return len;
+}
+
+static ssize_t bL_status_read(struct file *file, char __user *buf,
+                       size_t len, loff_t *pos)
+{
+       size_t count = 0;
+       char info[100];
+
+       count = bL_check_status(info);
+       if (count < 0)
+               return -EINVAL;
+
+       return simple_read_from_buffer(buf, len, pos, info, count);
+}
+
+static const struct file_operations bL_status_fops = {
+       .read           = bL_status_read,
+};
+
+static struct miscdevice bL_status_device = {
+       MISC_DYNAMIC_MINOR,
+       "bL_status",
+       &bL_status_fops
+};
+
  /*
   * Enable cluster-level coherency, in preparation for turning on the

MMU.
*/

arch/arm/mach-exynos/mcpm-exynos.c +7 -0

@@ -319,3 +366,20 @@ static int __init exynos_mcpm_init(void)
  }
 
  early_initcall(exynos_mcpm_init);
+
+static int __init exynos_bl_status_init(void)
+{
+       int ret;
+
+       if (!soc_is_exynos5420())
+               return -ENODEV;

arch/arm/mach-exynos/mcpm-exynos.c static int __init exynos_mcpm_init(void) · line 385

Quoted 10 lines

arch/arm/mach-exynos/mcpm-exynos.c +10 -0

+
+       ret = misc_register(&bL_status_device);
+       if (ret) {
+               pr_info("bl_status not available\n");
+               return ret;
+       }
+       return 0;
+}
+
+late_initcall(exynos_bl_status_init);

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Quoted 7 lines · Daniel Lezcano

Quoted 6 lines · Abhilash Kesavan

Add a user interface to check the core and cluster status on Exynos5420. This can be utilized while debugging mcpm issues. cat /dev/bL_status will show the current power status of all the 8 cores along with the cluster.

Quoted 8 lines

Quoted 5 lines

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

---

Hi Abhilash,

Hi Daniel,

Quoted 4 lines

I don't think you should add this file.

1. big Little is not exynos specific

But the core control/status bits that I am accessing are exynos specific and currently it is being enabled only on 5420.

Quoted 20 lines · Abhilash Kesavan

Quoted 7 lines · Daniel Lezcano

Quoted 6 lines · Abhilash Kesavan

Add a user interface to check the core and cluster status on Exynos5420. This can be utilized while debugging mcpm issues. cat /dev/bL_status will show the current power status of all the 8 cores along with the cluster.

Quoted 8 lines

Quoted 5 lines

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Inderpal Singh <[email protected]>

Signed-off-by Andrew Bresticker <[email protected]>

Signed-off-by Abhilash Kesavan <[email protected]>

---

Hi Abhilash,

Hi Daniel,

Quoted 1 line

Quoted 5 lines

Quoted 3 lines

I don't think you should add this file.

1. big Little is not exynos specific

But the core control/status bits that I am accessing are exynos specific and currently it is being enabled only on 5420.

Maybe yt is not worth pushing this patch upstream? Once basic debugging is over, you shouldn't have to use this code anymore.

Nicolas