exynos5420: clock file cleanup
v3 cover exynos5420: clock file cleanup
Many changes/fixes have been identified for clock file for exynos5420. These include correct parents, bit fields, new clocks etc. Existing files needs some correction in terms of names of the clock and indentation. These issues are addressed in this patch series. It also replaces the usage of enums with macro as clock ids.
This patch series is rebased on,git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git:master
This patch is also dependent on the following patch.
ARM: dts: add dt node for sss module for exynos5250/5420
Changes since v2:
-----------------
1] Addressed review comments from Gerhard Sittig and Tomasz Figa.
Changes since v1:
-----------------
1] Addressed review comments from Tomasz Figa.
http://www.spinics.net/lists/devicetree/msg16759.html http://www.spinics.net/lists/devicetree/msg16760.html
Shaik Ameer Basha (16):
clk: exynos5420: rename parent clocks
clk: exynos5420: add clocks for ISP block
clk: exynos5420: update clocks for GSCL and MSCL blocks
clk: exynos5420: correct clock parents for mscl sysmmu
clk: exynos5420: update clocks for G2D block
clk: exynos5420: update clocks for DISP1 block
clk: exynos5420: update clocks for PERIC block
clk: exynos5420: update clocks for PERIS and GEN blocks
clk: exynos5420: update clocks for WCORE block
clk: exynos5420: update clocks for FSYS and FSYS2 blocks
clk: exynos5420: correct sysmmu-mfc parent clocks
clk: exynos5420: fix register offset for sclk_bpll
clk: exynos5420: cleanup core and misc clocks
clk: exynos5420: correct g3d parent clock
clk: exynos5420: create clock ID for mout_sclk_vpll
clk: exynos5420: add more registers to restore list
arch/arm/boot/dts/exynos5420.dtsi | 14 +- drivers/clk/samsung/clk-exynos5420.c | 808 ++++++++++++++++++++------------ include/dt-bindings/clock/exynos5420.h | 33 +- 3 files changed, 550 insertions(+), 305 deletions(-) mode change 100644 => 100755 drivers/clk/samsung/clk-exynos5420.c mode change 100644 => 100755 include/dt-bindings/clock/exynos5420.h
Signature · 1 line
1.7.9.5
PATCH v3 1/16 clk: exynos5420: rename parent clocks
This patch modifies the defined parent clock names as per the exynos5420 datasheet.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 359 ++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 172 deletions(-) mode change 100644 => 100755 drivers/clk/samsung/clk-exynos5420.c
drivers/clk/samsung/clk-exynos5420.c +187 -172
@@ -217,85 +217,92 @@ static void exynos5420_clk_sleep_init(void) {}#endif /* list of all parent clocks */ -PNAME (mspll_cpu_p) = {"sclk_cpll" ,"sclk_dpll" , -"sclk_mpll" ,"sclk_spll" }; -PNAME (cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; -PNAME (kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; -PNAME (apll_p) = {"fin_pll" ,"fout_apll" , }; -PNAME (bpll_p) = {"fin_pll" ,"fout_bpll" , }; -PNAME (cpll_p) = {"fin_pll" ,"fout_cpll" , }; -PNAME (dpll_p) = {"fin_pll" ,"fout_dpll" , }; -PNAME (epll_p) = {"fin_pll" ,"fout_epll" , }; -PNAME (ipll_p) = {"fin_pll" ,"fout_ipll" , }; -PNAME (kpll_p) = {"fin_pll" ,"fout_kpll" , }; -PNAME (mpll_p) = {"fin_pll" ,"fout_mpll" , }; -PNAME (rpll_p) = {"fin_pll" ,"fout_rpll" , }; -PNAME (spll_p) = {"fin_pll" ,"fout_spll" , }; -PNAME (vpll_p) = {"fin_pll" ,"fout_vpll" , }; - -PNAME (group1_p) = {"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group2_p) = {"fin_pll" ,"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (group3_p) = {"sclk_rpll" ,"sclk_spll" }; -PNAME (group4_p) = {"sclk_ipll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group5_p) = {"sclk_vpll" ,"sclk_dpll" }; - -PNAME (sw_aclk66_p) = {"dout_aclk66" ,"sclk_spll" }; -PNAME (aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; - -PNAME (sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"sclk_spll" }; -PNAME (user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; - -PNAME (sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"sclk_spll" }; -PNAME (user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; - -PNAME (sw_aclk200_p) = {"dout_aclk200" ,"sclk_spll" }; -PNAME (aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; - -PNAME (sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"sclk_spll" }; -PNAME (user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; - -PNAME (sw_aclk333_p) = {"dout_aclk333" ,"sclk_spll" }; -PNAME (user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; - -PNAME (sw_aclk166_p) = {"dout_aclk166" ,"sclk_spll" }; -PNAME (user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; - -PNAME (sw_aclk266_p) = {"dout_aclk266" ,"sclk_spll" }; -PNAME (user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; - -PNAME (sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"sclk_spll" }; -PNAME (user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; - -PNAME (sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"sclk_spll" }; -PNAME (user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; - -PNAME (sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"sclk_spll" }; -PNAME (user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; - -PNAME (sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"sclk_spll" }; -PNAME (user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; - -PNAME (sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"sclk_spll" }; -PNAME (user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; - -PNAME (sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"sclk_spll" }; -PNAME (user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; - -PNAME (sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"sclk_spll" }; -PNAME (user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; - -PNAME (audio0_p) = {"fin_pll" ,"cdclk0" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio1_p) = {"fin_pll" ,"cdclk1" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio2_p) = {"fin_pll" ,"cdclk2" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" ,"dout_audio2" , -"spdif_extclk" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; -PNAME (maudio0_p) = {"fin_pll" ,"maudio_clk" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; +PNAME (mout_mspll_cpu_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" }; +PNAME (mout_cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; +PNAME (mout_kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; +PNAME (mout_apll_p) = {"fin_pll" ,"fout_apll" }; +PNAME (mout_bpll_p) = {"fin_pll" ,"fout_bpll" }; +PNAME (mout_cpll_p) = {"fin_pll" ,"fout_cpll" }; +PNAME (mout_dpll_p) = {"fin_pll" ,"fout_dpll" }; +PNAME (mout_epll_p) = {"fin_pll" ,"fout_epll" }; +PNAME (mout_ipll_p) = {"fin_pll" ,"fout_ipll" }; +PNAME (mout_kpll_p) = {"fin_pll" ,"fout_kpll" }; +PNAME (mout_mpll_p) = {"fin_pll" ,"fout_mpll" }; +PNAME (mout_rpll_p) = {"fin_pll" ,"fout_rpll" }; +PNAME (mout_spll_p) = {"fin_pll" ,"fout_spll" }; +PNAME (mout_vpll_p) = {"fin_pll" ,"fout_vpll" }; + +PNAME (mout_group1_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" }; +PNAME (mout_group2_p) = {"fin_pll" ,"mout_sclk_cpll" , +"mout_sclk_dpll" ,"mout_sclk_mpll" ,"mout_sclk_spll" , +"mout_sclk_ipll" ,"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_group3_p) = {"mout_sclk_rpll" ,"mout_sclk_spll" }; +PNAME (mout_group4_p) = {"mout_sclk_ipll" ,"mout_sclk_dpll" ,"mout_sclk_mpll" }; +PNAME (mout_group5_p) = {"mout_sclk_vpll" ,"mout_sclk_dpll" }; + +PNAME (mout_sw_aclk66_p) = {"dout_aclk66" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; + +PNAME (mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; + +PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; + +PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" }; +PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; + +PNAME (mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; + +PNAME (mout_sw_aclk333_p) = {"dout_aclk333" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; + +PNAME (mout_sw_aclk166_p) = {"dout_aclk166" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; + +PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; + +PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; + +PNAME (mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; + +PNAME (mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; + +PNAME (mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; + +PNAME (mout_sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; + +PNAME (mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; + +PNAME (mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; + +PNAME (mout_audio0_p) = {"fin_pll" ,"cdclk0" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_audio1_p) = {"fin_pll" ,"cdclk1" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_audio2_p) = {"fin_pll" ,"cdclk2" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" , +"dout_audio2" ,"spdif_extclk" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; +PNAME (mout_maudio0_p) = {"fin_pll" ,"maudio_clk" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[]__initdata = {
@@ -316,123 +323,131 @@ static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initda };static struct samsung_mux_clock exynos5420_mux_clks[]__initdata = { -MUX (0 ,"mout_mspll_kfc" , mspll_cpu_p,SRC_TOP7 ,8 ,2 ), -MUX (0 ,"mout_mspll_cpu" , mspll_cpu_p,SRC_TOP7 ,12 ,2 ), -MUX (0 ,"mout_apll" , apll_p,SRC_CPU ,0 ,1 ), -MUX (0 ,"mout_cpu" , cpu_p,SRC_CPU ,16 ,1 ), -MUX (0 ,"mout_kpll" , kpll_p,SRC_KFC ,0 ,1 ), -MUX (0 ,"mout_cpu_kfc" , kfc_p,SRC_KFC ,16 ,1 ), +MUX (0 ,"mout_mspll_kfc" , mout_mspll_cpu_p,SRC_TOP7 ,8 ,2 ), +MUX (0 ,"mout_mspll_cpu" , mout_mspll_cpu_p,SRC_TOP7 ,12 ,2 ), +MUX (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ), +MUX (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ), +MUX (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 ), +MUX (0 ,"mout_kfc" , mout_kfc_p,SRC_KFC ,16 ,1 ), -MUX (0 ,"sclk_bpll" , bpll_p,SRC_CDREX ,0 ,1 ), +MUX (0 ,"sclk_bpll" , mout_bpll_p,SRC_CDREX ,0 ,1 ), -MUX_A (0 ,"mout_aclk400_mscl" , group1_p, +MUX_A (0 ,"mout_aclk400_mscl" , mout_group1_p,SRC_TOP0 ,4 ,2 ,"aclk400_mscl" ), -MUX (0 ,"mout_aclk200" , group1_p,SRC_TOP0 ,8 ,2 ), -MUX (0 ,"mout_aclk200_fsys2" , group1_p,SRC_TOP0 ,12 ,2 ), -MUX (0 ,"mout_aclk200_fsys" , group1_p,SRC_TOP0 ,28 ,2 ), - -MUX (0 ,"mout_aclk333_432_gscl" , group4_p,SRC_TOP1 ,0 ,2 ), -MUX (0 ,"mout_aclk66" , group1_p,SRC_TOP1 ,8 ,2 ), -MUX (0 ,"mout_aclk266" , group1_p,SRC_TOP1 ,20 ,2 ), -MUX (0 ,"mout_aclk166" , group1_p,SRC_TOP1 ,24 ,2 ), -MUX (0 ,"mout_aclk333" , group1_p,SRC_TOP1 ,28 ,2 ), - -MUX (0 ,"mout_aclk333_g2d" , group1_p,SRC_TOP2 ,8 ,2 ), -MUX (0 ,"mout_aclk266_g2d" , group1_p,SRC_TOP2 ,12 ,2 ), -MUX (0 ,"mout_aclk_g3d" , group5_p,SRC_TOP2 ,16 ,1 ), -MUX (0 ,"mout_aclk300_jpeg" , group1_p,SRC_TOP2 ,20 ,2 ), -MUX (0 ,"mout_aclk300_disp1" , group1_p,SRC_TOP2 ,24 ,2 ), -MUX (0 ,"mout_aclk300_gscl" , group1_p,SRC_TOP2 ,28 ,2 ), - -MUX (0 ,"mout_user_aclk400_mscl" , user_aclk400_mscl_p, +MUX (0 ,"mout_aclk200" , mout_group1_p,SRC_TOP0 ,8 ,2 ), +MUX (0 ,"mout_aclk200_fsys2" , mout_group1_p,SRC_TOP0 ,12 ,2 ), +MUX (0 ,"mout_aclk200_fsys" , mout_group1_p,SRC_TOP0 ,28 ,2 ), + +MUX (0 ,"mout_aclk333_432_gscl" , mout_group4_p,SRC_TOP1 ,0 ,2 ), +MUX (0 ,"mout_aclk66" , mout_group1_p,SRC_TOP1 ,8 ,2 ), +MUX (0 ,"mout_aclk266" , mout_group1_p,SRC_TOP1 ,20 ,2 ), +MUX (0 ,"mout_aclk166" , mout_group1_p,SRC_TOP1 ,24 ,2 ), +MUX (0 ,"mout_aclk333" , mout_group1_p,SRC_TOP1 ,28 ,2 ), + +MUX (0 ,"mout_aclk333_g2d" , mout_group1_p,SRC_TOP2 ,8 ,2 ), +MUX (0 ,"mout_aclk266_g2d" , mout_group1_p,SRC_TOP2 ,12 ,2 ), +MUX (0 ,"mout_aclk_g3d" , mout_group5_p,SRC_TOP2 ,16 ,1 ), +MUX (0 ,"mout_aclk300_jpeg" , mout_group1_p,SRC_TOP2 ,20 ,2 ), +MUX (0 ,"mout_aclk300_disp1" , mout_group1_p,SRC_TOP2 ,24 ,2 ), +MUX (0 ,"mout_aclk300_gscl" , mout_group1_p,SRC_TOP2 ,28 ,2 ), + +MUX (0 ,"mout_user_aclk400_mscl" , mout_user_aclk400_mscl_p,SRC_TOP3 ,4 ,1 ), -MUX_A (0 ,"mout_aclk200_disp1" , aclk200_disp1_p, -SRC_TOP3 ,8 ,1 ,"aclk200_disp1" ), -MUX (0 ,"mout_user_aclk200_fsys2" , user_aclk200_fsys2_p, +MUX (0 ,"mout_aclk200_disp1" , mout_aclk200_disp1_p,SRC_TOP3 ,8 ,1 ), +MUX (0 ,"mout_user_aclk200_fsys2" , mout_user_aclk200_fsys2_p,SRC_TOP3 ,12 ,1 ), -MUX (0 ,"mout_user_aclk200_fsys" , user_aclk200_fsys_p, +MUX (0 ,"mout_user_aclk200_fsys" , mout_user_aclk200_fsys_p,SRC_TOP3 ,28 ,1 ), -MUX (0 ,"mout_user_aclk333_432_gscl" , user_aclk333_432_gscl_p, +MUX (0 ,"mout_user_aclk333_432_gscl" , mout_user_aclk333_432_gscl_p,SRC_TOP4 ,0 ,1 ), -MUX (0 ,"mout_aclk66_peric" , aclk66_peric_p,SRC_TOP4 ,8 ,1 ), -MUX (0 ,"mout_user_aclk266" , user_aclk266_p,SRC_TOP4 ,20 ,1 ), -MUX (0 ,"mout_user_aclk166" , user_aclk166_p,SRC_TOP4 ,24 ,1 ), -MUX (0 ,"mout_user_aclk333" , user_aclk333_p,SRC_TOP4 ,28 ,1 ), - -MUX (0 ,"mout_aclk66_psgen" , aclk66_peric_p,SRC_TOP5 ,4 ,1 ), -MUX (0 ,"mout_user_aclk333_g2d" , user_aclk333_g2d_p,SRC_TOP5 ,8 ,1 ), -MUX (0 ,"mout_user_aclk266_g2d" , user_aclk266_g2d_p,SRC_TOP5 ,12 ,1 ), -MUX_A (0 ,"mout_user_aclk_g3d" , user_aclk_g3d_p, +MUX (0 ,"mout_user_aclk66_peric" , mout_user_aclk66_peric_p, +SRC_TOP4 ,8 ,1 ), +MUX (0 ,"mout_user_aclk266" , mout_user_aclk266_p,SRC_TOP4 ,20 ,1 ), +MUX (0 ,"mout_user_aclk166" , mout_user_aclk166_p,SRC_TOP4 ,24 ,1 ), +MUX (0 ,"mout_user_aclk333" , mout_user_aclk333_p,SRC_TOP4 ,28 ,1 ), + +MUX (0 ,"mout_user_aclk66_psgen" , mout_user_aclk66_peric_p,SRC_TOP5 , +4 ,1 ), +MUX (0 ,"mout_user_aclk333_g2d" , mout_user_aclk333_g2d_p,SRC_TOP5 , +8 ,1 ), +MUX (0 ,"mout_user_aclk266_g2d" , mout_user_aclk266_g2d_p,SRC_TOP5 , +12 ,1 ), +MUX_A (0 ,"mout_user_aclk_g3d" , mout_user_aclk_g3d_p,SRC_TOP5 ,16 ,1 ,"aclkg3d" ), -MUX (0 ,"mout_user_aclk300_jpeg" , user_aclk300_jpeg_p, +MUX (0 ,"mout_user_aclk300_jpeg" , mout_user_aclk300_jpeg_p,SRC_TOP5 ,20 ,1 ), -MUX (0 ,"mout_user_aclk300_disp1" , user_aclk300_disp1_p, +MUX (0 ,"mout_user_aclk300_disp1" , mout_user_aclk300_disp1_p,SRC_TOP5 ,24 ,1 ), -MUX (0 ,"mout_user_aclk300_gscl" , user_aclk300_gscl_p, +MUX (0 ,"mout_user_aclk300_gscl" , mout_user_aclk300_gscl_p,SRC_TOP5 ,28 ,1 ), -MUX (0 ,"sclk_mpll" , mpll_p,SRC_TOP6 ,0 ,1 ), -MUX (0 ,"sclk_vpll" , vpll_p,SRC_TOP6 ,4 ,1 ), -MUX (0 ,"sclk_spll" , spll_p,SRC_TOP6 ,8 ,1 ), -MUX (0 ,"sclk_ipll" , ipll_p,SRC_TOP6 ,12 ,1 ), -MUX (0 ,"sclk_rpll" , rpll_p,SRC_TOP6 ,16 ,1 ), -MUX (0 ,"sclk_epll" , epll_p,SRC_TOP6 ,20 ,1 ), -MUX (0 ,"sclk_dpll" , dpll_p,SRC_TOP6 ,24 ,1 ), -MUX (0 ,"sclk_cpll" , cpll_p,SRC_TOP6 ,28 ,1 ), - -MUX (0 ,"mout_sw_aclk400_mscl" , sw_aclk400_mscl_p,SRC_TOP10 ,4 ,1 ), -MUX (0 ,"mout_sw_aclk200" , sw_aclk200_p,SRC_TOP10 ,8 ,1 ), -MUX (0 ,"mout_sw_aclk200_fsys2" , sw_aclk200_fsys2_p, +MUX (0 ,"mout_sclk_mpll" , mout_mpll_p,SRC_TOP6 ,0 ,1 ), +MUX (0 ,"mout_sclk_vpll" , mout_vpll_p,SRC_TOP6 ,4 ,1 ), +MUX (0 ,"mout_sclk_spll" , mout_spll_p,SRC_TOP6 ,8 ,1 ), +MUX (0 ,"mout_sclk_ipll" , mout_ipll_p,SRC_TOP6 ,12 ,1 ), +MUX (0 ,"mout_sclk_rpll" , mout_rpll_p,SRC_TOP6 ,16 ,1 ), +MUX (0 ,"mout_sclk_epll" , mout_epll_p,SRC_TOP6 ,20 ,1 ), +MUX (0 ,"mout_sclk_dpll" , mout_dpll_p,SRC_TOP6 ,24 ,1 ), +MUX (0 ,"mout_sclk_cpll" , mout_cpll_p,SRC_TOP6 ,28 ,1 ), + +MUX (0 ,"mout_sw_aclk400_mscl" , mout_sw_aclk400_mscl_p, +SRC_TOP10 ,4 ,1 ), +MUX (0 ,"mout_sw_aclk200" , mout_sw_aclk200_p,SRC_TOP10 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk200_fsys2" , mout_sw_aclk200_fsys2_p,SRC_TOP10 ,12 ,1 ), -MUX (0 ,"mout_sw_aclk200_fsys" , sw_aclk200_fsys_p,SRC_TOP10 ,28 ,1 ), - -MUX (0 ,"mout_sw_aclk333_432_gscl" , sw_aclk333_432_gscl_p, +MUX (0 ,"mout_sw_aclk200_fsys" , mout_sw_aclk200_fsys_p, +SRC_TOP10 ,28 ,1 ), +MUX (0 ,"mout_sw_aclk333_432_gscl" , mout_sw_aclk333_432_gscl_p,SRC_TOP11 ,0 ,1 ), -MUX (0 ,"mout_sw_aclk66" , sw_aclk66_p,SRC_TOP11 ,8 ,1 ), -MUX (0 ,"mout_sw_aclk266" , sw_aclk266_p,SRC_TOP11 ,20 ,1 ), -MUX (0 ,"mout_sw_aclk166" , sw_aclk166_p,SRC_TOP11 ,24 ,1 ), -MUX (0 ,"mout_sw_aclk333" , sw_aclk333_p,SRC_TOP11 ,28 ,1 ), - -MUX (0 ,"mout_sw_aclk333_g2d" , sw_aclk333_g2d_p,SRC_TOP12 ,8 ,1 ), -MUX (0 ,"mout_sw_aclk266_g2d" , sw_aclk266_g2d_p,SRC_TOP12 ,12 ,1 ), -MUX (0 ,"mout_sw_aclk_g3d" , sw_aclk_g3d_p,SRC_TOP12 ,16 ,1 ), -MUX (0 ,"mout_sw_aclk300_jpeg" , sw_aclk300_jpeg_p,SRC_TOP12 ,20 ,1 ), -MUX (0 ,"mout_sw_aclk300_disp1" , sw_aclk300_disp1_p, +MUX (0 ,"mout_sw_aclk66" , mout_sw_aclk66_p,SRC_TOP11 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk266" , mout_sw_aclk266_p,SRC_TOP11 ,20 ,1 ), +MUX (0 ,"mout_sw_aclk166" , mout_sw_aclk166_p,SRC_TOP11 ,24 ,1 ), +MUX (0 ,"mout_sw_aclk333" , mout_sw_aclk333_p,SRC_TOP11 ,28 ,1 ), + +MUX (0 ,"mout_sw_aclk333_g2d" , mout_sw_aclk333_g2d_p, +SRC_TOP12 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk266_g2d" , mout_sw_aclk266_g2d_p, +SRC_TOP12 ,12 ,1 ), +MUX (0 ,"mout_sw_aclk_g3d" , mout_sw_aclk_g3d_p,SRC_TOP12 ,16 ,1 ), +MUX (0 ,"mout_sw_aclk300_jpeg" , mout_sw_aclk300_jpeg_p, +SRC_TOP12 ,20 ,1 ), +MUX (0 ,"mout_sw_aclk300_disp1" , mout_sw_aclk300_disp1_p,SRC_TOP12 ,24 ,1 ), -MUX (0 ,"mout_sw_aclk300_gscl" , sw_aclk300_gscl_p,SRC_TOP12 ,28 ,1 ), +MUX (0 ,"mout_sw_aclk300_gscl" , mout_sw_aclk300_gscl_p, +SRC_TOP12 ,28 ,1 ),/* DISP1 Block */ -MUX (0 ,"mout_fimd1" , group3_p,SRC_DISP10 ,4 ,1 ), -MUX (0 ,"mout_mipi1" , group2_p,SRC_DISP10 ,16 ,3 ), -MUX (0 ,"mout_dp1" , group2_p,SRC_DISP10 ,20 ,3 ), -MUX (0 ,"mout_pixel" , group2_p,SRC_DISP10 ,24 ,3 ), -MUX (CLK_MOUT_HDMI ,"mout_hdmi" , hdmi_p,SRC_DISP10 ,28 ,1 ), +MUX (0 ,"mout_fimd1" , mout_group3_p,SRC_DISP10 ,4 ,1 ), +MUX (0 ,"mout_mipi1" , mout_group2_p,SRC_DISP10 ,16 ,3 ), +MUX (0 ,"mout_dp1" , mout_group2_p,SRC_DISP10 ,20 ,3 ), +MUX (0 ,"mout_pixel" , mout_group2_p,SRC_DISP10 ,24 ,3 ), +MUX (CLK_MOUT_HDMI ,"mout_hdmi" , mout_hdmi_p,SRC_DISP10 ,28 ,1 ),/* MAU Block */ -MUX (0 ,"mout_maudio0" , maudio0_p,SRC_MAU ,28 ,3 ), +MUX (0 ,"mout_maudio0" , mout_maudio0_p,SRC_MAU ,28 ,3 ),/* FSYS Block */ -MUX (0 ,"mout_usbd301" , group2_p,SRC_FSYS ,4 ,3 ), -MUX (0 ,"mout_mmc0" , group2_p,SRC_FSYS ,8 ,3 ), -MUX (0 ,"mout_mmc1" , group2_p,SRC_FSYS ,12 ,3 ), -MUX (0 ,"mout_mmc2" , group2_p,SRC_FSYS ,16 ,3 ), -MUX (0 ,"mout_usbd300" , group2_p,SRC_FSYS ,20 ,3 ), -MUX (0 ,"mout_unipro" , group2_p,SRC_FSYS ,24 ,3 ), +MUX (0 ,"mout_usbd301" , mout_group2_p,SRC_FSYS ,4 ,3 ), +MUX (0 ,"mout_mmc0" , mout_group2_p,SRC_FSYS ,8 ,3 ), +MUX (0 ,"mout_mmc1" , mout_group2_p,SRC_FSYS ,12 ,3 ), +MUX (0 ,"mout_mmc2" , mout_group2_p,SRC_FSYS ,16 ,3 ), +MUX (0 ,"mout_usbd300" , mout_group2_p,SRC_FSYS ,20 ,3 ), +MUX (0 ,"mout_unipro" , mout_group2_p,SRC_FSYS ,24 ,3 ),/* PERIC Block */ -MUX (0 ,"mout_uart0" , group2_p,SRC_PERIC0 ,4 ,3 ), -MUX (0 ,"mout_uart1" , group2_p,SRC_PERIC0 ,8 ,3 ), -MUX (0 ,"mout_uart2" , group2_p,SRC_PERIC0 ,12 ,3 ), -MUX (0 ,"mout_uart3" , group2_p,SRC_PERIC0 ,16 ,3 ), -MUX (0 ,"mout_pwm" , group2_p,SRC_PERIC0 ,24 ,3 ), -MUX (0 ,"mout_spdif" , spdif_p,SRC_PERIC0 ,28 ,3 ), -MUX (0 ,"mout_audio0" , audio0_p,SRC_PERIC1 ,8 ,3 ), -MUX (0 ,"mout_audio1" , audio1_p,SRC_PERIC1 ,12 ,3 ), -MUX (0 ,"mout_audio2" , audio2_p,SRC_PERIC1 ,16 ,3 ), -MUX (0 ,"mout_spi0" , group2_p,SRC_PERIC1 ,20 ,3 ), -MUX (0 ,"mout_spi1" , group2_p,SRC_PERIC1 ,24 ,3 ), -MUX (0 ,"mout_spi2" , group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_uart0" , mout_group2_p,SRC_PERIC0 ,4 ,3 ), +MUX (0 ,"mout_uart1" , mout_group2_p,SRC_PERIC0 ,8 ,3 ), +MUX (0 ,"mout_uart2" , mout_group2_p,SRC_PERIC0 ,12 ,3 ), +MUX (0 ,"mout_uart3" , mout_group2_p,SRC_PERIC0 ,16 ,3 ), +MUX (0 ,"mout_pwm" , mout_group2_p,SRC_PERIC0 ,24 ,3 ), +MUX (0 ,"mout_spdif" , mout_spdif_p,SRC_PERIC0 ,28 ,3 ), +MUX (0 ,"mout_audio0" , mout_audio0_p,SRC_PERIC1 ,8 ,3 ), +MUX (0 ,"mout_audio1" , mout_audio1_p,SRC_PERIC1 ,12 ,3 ), +MUX (0 ,"mout_audio2" , mout_audio2_p,SRC_PERIC1 ,16 ,3 ), +MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ), +MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ), +MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), };static struct samsung_div_clock exynos5420_div_clks[]__initdata = {
Signature · 1 line
1.7.9.5
PATCH v3 1/16 clk: exynos5420: rename parent clocks
Hi Shaik
Quoted 6 lines · Shaik Ameer Basha
This patch modifies the defined parent clock names as per the exynos5420 datasheet.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>---
This looks good. Mostly renaming is done here.
For this you have my
Reviewed-by Alim Akhtar <[email protected]>
Quoted 415 lines
drivers/clk/samsung/clk-exynos5420.c | 359 ++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 172 deletions(-) mode change 100644 => 100755 drivers/clk/samsung/clk-exynos5420.cdrivers/clk/samsung/clk-exynos5420.c +187
-173@@ -217,85 +217,92 @@ static void exynos5420_clk_sleep_init(void) {}#endif /* list of all parent clocks */ -PNAME (mspll_cpu_p) = {"sclk_cpll" ,"sclk_dpll" , -"sclk_mpll" ,"sclk_spll" }; -PNAME (cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; -PNAME (kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; -PNAME (apll_p) = {"fin_pll" ,"fout_apll" , }; -PNAME (bpll_p) = {"fin_pll" ,"fout_bpll" , }; -PNAME (cpll_p) = {"fin_pll" ,"fout_cpll" , }; -PNAME (dpll_p) = {"fin_pll" ,"fout_dpll" , }; -PNAME (epll_p) = {"fin_pll" ,"fout_epll" , }; -PNAME (ipll_p) = {"fin_pll" ,"fout_ipll" , }; -PNAME (kpll_p) = {"fin_pll" ,"fout_kpll" , }; -PNAME (mpll_p) = {"fin_pll" ,"fout_mpll" , }; -PNAME (rpll_p) = {"fin_pll" ,"fout_rpll" , }; -PNAME (spll_p) = {"fin_pll" ,"fout_spll" , }; -PNAME (vpll_p) = {"fin_pll" ,"fout_vpll" , }; - -PNAME (group1_p) = {"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group2_p) = {"fin_pll" ,"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (group3_p) = {"sclk_rpll" ,"sclk_spll" }; -PNAME (group4_p) = {"sclk_ipll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group5_p) = {"sclk_vpll" ,"sclk_dpll" }; - -PNAME (sw_aclk66_p) = {"dout_aclk66" ,"sclk_spll" }; -PNAME (aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; - -PNAME (sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"sclk_spll" }; -PNAME (user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; - -PNAME (sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"sclk_spll" }; -PNAME (user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; - -PNAME (sw_aclk200_p) = {"dout_aclk200" ,"sclk_spll" }; -PNAME (aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; - -PNAME (sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"sclk_spll" }; -PNAME (user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; - -PNAME (sw_aclk333_p) = {"dout_aclk333" ,"sclk_spll" }; -PNAME (user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; - -PNAME (sw_aclk166_p) = {"dout_aclk166" ,"sclk_spll" }; -PNAME (user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; - -PNAME (sw_aclk266_p) = {"dout_aclk266" ,"sclk_spll" }; -PNAME (user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; - -PNAME (sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"sclk_spll" }; -PNAME (user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; - -PNAME (sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"sclk_spll" }; -PNAME (user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; - -PNAME (sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"sclk_spll" }; -PNAME (user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; - -PNAME (sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"sclk_spll" }; -PNAME (user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; - -PNAME (sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"sclk_spll" }; -PNAME (user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; - -PNAME (sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"sclk_spll" }; -PNAME (user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; - -PNAME (sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"sclk_spll" }; -PNAME (user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; - -PNAME (audio0_p) = {"fin_pll" ,"cdclk0" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio1_p) = {"fin_pll" ,"cdclk1" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio2_p) = {"fin_pll" ,"cdclk2" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" ,"dout_audio2" , -"spdif_extclk" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; -PNAME (maudio0_p) = {"fin_pll" ,"maudio_clk" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; +PNAME (mout_mspll_cpu_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" }; +PNAME (mout_cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; +PNAME (mout_kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; +PNAME (mout_apll_p) = {"fin_pll" ,"fout_apll" }; +PNAME (mout_bpll_p) = {"fin_pll" ,"fout_bpll" }; +PNAME (mout_cpll_p) = {"fin_pll" ,"fout_cpll" }; +PNAME (mout_dpll_p) = {"fin_pll" ,"fout_dpll" }; +PNAME (mout_epll_p) = {"fin_pll" ,"fout_epll" }; +PNAME (mout_ipll_p) = {"fin_pll" ,"fout_ipll" }; +PNAME (mout_kpll_p) = {"fin_pll" ,"fout_kpll" }; +PNAME (mout_mpll_p) = {"fin_pll" ,"fout_mpll" }; +PNAME (mout_rpll_p) = {"fin_pll" ,"fout_rpll" }; +PNAME (mout_spll_p) = {"fin_pll" ,"fout_spll" }; +PNAME (mout_vpll_p) = {"fin_pll" ,"fout_vpll" }; + +PNAME (mout_group1_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" }; +PNAME (mout_group2_p) = {"fin_pll" ,"mout_sclk_cpll" , +"mout_sclk_dpll" ,"mout_sclk_mpll" ,"mout_sclk_spll" , +"mout_sclk_ipll" ,"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_group3_p) = {"mout_sclk_rpll" ,"mout_sclk_spll" }; +PNAME (mout_group4_p) = {"mout_sclk_ipll" ,"mout_sclk_dpll" ,"mout_sclk_mpll" }; +PNAME (mout_group5_p) = {"mout_sclk_vpll" ,"mout_sclk_dpll" }; + +PNAME (mout_sw_aclk66_p) = {"dout_aclk66" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; + +PNAME (mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; + +PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; + +PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" }; +PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; + +PNAME (mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; + +PNAME (mout_sw_aclk333_p) = {"dout_aclk333" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; + +PNAME (mout_sw_aclk166_p) = {"dout_aclk166" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; + +PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; + +PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; + +PNAME (mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; + +PNAME (mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; + +PNAME (mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; + +PNAME (mout_sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; + +PNAME (mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; + +PNAME (mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; + +PNAME (mout_audio0_p) = {"fin_pll" ,"cdclk0" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_audio1_p) = {"fin_pll" ,"cdclk1" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_audio2_p) = {"fin_pll" ,"cdclk2" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" , +"dout_audio2" ,"spdif_extclk" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; +PNAME (mout_maudio0_p) = {"fin_pll" ,"maudio_clk" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[]__initdata = {@@ -316,123 +323,131 @@ static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initda };static struct samsung_mux_clock exynos5420_mux_clks[]__initdata = { -MUX (0 ,"mout_mspll_kfc" , mspll_cpu_p,SRC_TOP7 ,8 ,2 ), -MUX (0 ,"mout_mspll_cpu" , mspll_cpu_p,SRC_TOP7 ,12 ,2 ), -MUX (0 ,"mout_apll" , apll_p,SRC_CPU ,0 ,1 ), -MUX (0 ,"mout_cpu" , cpu_p,SRC_CPU ,16 ,1 ), -MUX (0 ,"mout_kpll" , kpll_p,SRC_KFC ,0 ,1 ), -MUX (0 ,"mout_cpu_kfc" , kfc_p,SRC_KFC ,16 ,1 ), +MUX (0 ,"mout_mspll_kfc" , mout_mspll_cpu_p,SRC_TOP7 ,8 ,2 ), +MUX (0 ,"mout_mspll_cpu" , mout_mspll_cpu_p,SRC_TOP7 ,12 ,2 ), +MUX (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ), +MUX (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ), +MUX (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 ), +MUX (0 ,"mout_kfc" , mout_kfc_p,SRC_KFC ,16 ,1 ), -MUX (0 ,"sclk_bpll" , bpll_p,SRC_CDREX ,0 ,1 ), +MUX (0 ,"sclk_bpll" , mout_bpll_p,SRC_CDREX ,0 ,1 ), -MUX_A (0 ,"mout_aclk400_mscl" , group1_p, +MUX_A (0 ,"mout_aclk400_mscl" , mout_group1_p,SRC_TOP0 ,4 ,2 ,"aclk400_mscl" ), -MUX (0 ,"mout_aclk200" , group1_p,SRC_TOP0 ,8 ,2 ), -MUX (0 ,"mout_aclk200_fsys2" , group1_p,SRC_TOP0 ,12 ,2 ), -MUX (0 ,"mout_aclk200_fsys" , group1_p,SRC_TOP0 ,28 ,2 ), - -MUX (0 ,"mout_aclk333_432_gscl" , group4_p,SRC_TOP1 ,0 ,2 ), -MUX (0 ,"mout_aclk66" , group1_p,SRC_TOP1 ,8 ,2 ), -MUX (0 ,"mout_aclk266" , group1_p,SRC_TOP1 ,20 ,2 ), -MUX (0 ,"mout_aclk166" , group1_p,SRC_TOP1 ,24 ,2 ), -MUX (0 ,"mout_aclk333" , group1_p,SRC_TOP1 ,28 ,2 ), - -MUX (0 ,"mout_aclk333_g2d" , group1_p,SRC_TOP2 ,8 ,2 ), -MUX (0 ,"mout_aclk266_g2d" , group1_p,SRC_TOP2 ,12 ,2 ), -MUX (0 ,"mout_aclk_g3d" , group5_p,SRC_TOP2 ,16 ,1 ), -MUX (0 ,"mout_aclk300_jpeg" , group1_p,SRC_TOP2 ,20 ,2 ), -MUX (0 ,"mout_aclk300_disp1" , group1_p,SRC_TOP2 ,24 ,2 ), -MUX (0 ,"mout_aclk300_gscl" , group1_p,SRC_TOP2 ,28 ,2 ), - -MUX (0 ,"mout_user_aclk400_mscl" , user_aclk400_mscl_p, +MUX (0 ,"mout_aclk200" , mout_group1_p,SRC_TOP0 ,8 ,2 ), +MUX (0 ,"mout_aclk200_fsys2" , mout_group1_p,SRC_TOP0 ,12 ,2 ), +MUX (0 ,"mout_aclk200_fsys" , mout_group1_p,SRC_TOP0 ,28 ,2 ), + +MUX (0 ,"mout_aclk333_432_gscl" , mout_group4_p,SRC_TOP1 ,0 ,2 ), +MUX (0 ,"mout_aclk66" , mout_group1_p,SRC_TOP1 ,8 ,2 ), +MUX (0 ,"mout_aclk266" , mout_group1_p,SRC_TOP1 ,20 ,2 ), +MUX (0 ,"mout_aclk166" , mout_group1_p,SRC_TOP1 ,24 ,2 ), +MUX (0 ,"mout_aclk333" , mout_group1_p,SRC_TOP1 ,28 ,2 ), + +MUX (0 ,"mout_aclk333_g2d" , mout_group1_p,SRC_TOP2 ,8 ,2 ), +MUX (0 ,"mout_aclk266_g2d" , mout_group1_p,SRC_TOP2 ,12 ,2 ), +MUX (0 ,"mout_aclk_g3d" , mout_group5_p,SRC_TOP2 ,16 ,1 ), +MUX (0 ,"mout_aclk300_jpeg" , mout_group1_p,SRC_TOP2 ,20 ,2 ), +MUX (0 ,"mout_aclk300_disp1" , mout_group1_p,SRC_TOP2 ,24 ,2 ), +MUX (0 ,"mout_aclk300_gscl" , mout_group1_p,SRC_TOP2 ,28 ,2 ), + +MUX (0 ,"mout_user_aclk400_mscl" , mout_user_aclk400_mscl_p,SRC_TOP3 ,4 ,1 ), -MUX_A (0 ,"mout_aclk200_disp1" , aclk200_disp1_p, -SRC_TOP3 ,8 ,1 ,"aclk200_disp1" ), -MUX (0 ,"mout_user_aclk200_fsys2" , user_aclk200_fsys2_p, +MUX (0 ,"mout_aclk200_disp1" , mout_aclk200_disp1_p,SRC_TOP3 ,8 ,1 ), +MUX (0 ,"mout_user_aclk200_fsys2" , mout_user_aclk200_fsys2_p,SRC_TOP3 ,12 ,1 ), -MUX (0 ,"mout_user_aclk200_fsys" , user_aclk200_fsys_p, +MUX (0 ,"mout_user_aclk200_fsys" , mout_user_aclk200_fsys_p,SRC_TOP3 ,28 ,1 ), -MUX (0 ,"mout_user_aclk333_432_gscl" , user_aclk333_432_gscl_p, +MUX (0 ,"mout_user_aclk333_432_gscl" , mout_user_aclk333_432_gscl_p,SRC_TOP4 ,0 ,1 ), -MUX (0 ,"mout_aclk66_peric" , aclk66_peric_p,SRC_TOP4 ,8 ,1 ), -MUX (0 ,"mout_user_aclk266" , user_aclk266_p,SRC_TOP4 ,20 ,1 ), -MUX (0 ,"mout_user_aclk166" , user_aclk166_p,SRC_TOP4 ,24 ,1 ), -MUX (0 ,"mout_user_aclk333" , user_aclk333_p,SRC_TOP4 ,28 ,1 ), - -MUX (0 ,"mout_aclk66_psgen" , aclk66_peric_p,SRC_TOP5 ,4 ,1 ), -MUX (0 ,"mout_user_aclk333_g2d" , user_aclk333_g2d_p,SRC_TOP5 ,8 ,1 ), -MUX (0 ,"mout_user_aclk266_g2d" , user_aclk266_g2d_p,SRC_TOP5 ,12 ,1 ), -MUX_A (0 ,"mout_user_aclk_g3d" , user_aclk_g3d_p, +MUX (0 ,"mout_user_aclk66_peric" , mout_user_aclk66_peric_p, +SRC_TOP4 ,8 ,1 ), +MUX (0 ,"mout_user_aclk266" , mout_user_aclk266_p,SRC_TOP4 ,20 ,1 ), +MUX (0 ,"mout_user_aclk166" , mout_user_aclk166_p,SRC_TOP4 ,24 ,1 ), +MUX (0 ,"mout_user_aclk333" , mout_user_aclk333_p,SRC_TOP4 ,28 ,1 ), + +MUX (0 ,"mout_user_aclk66_psgen" , mout_user_aclk66_peric_p,SRC_TOP5 , +4 ,1 ), +MUX (0 ,"mout_user_aclk333_g2d" , mout_user_aclk333_g2d_p,SRC_TOP5 , +8 ,1 ), +MUX (0 ,"mout_user_aclk266_g2d" , mout_user_aclk266_g2d_p,SRC_TOP5 , +12 ,1 ), +MUX_A (0 ,"mout_user_aclk_g3d" , mout_user_aclk_g3d_p,SRC_TOP5 ,16 ,1 ,"aclkg3d" ), -MUX (0 ,"mout_user_aclk300_jpeg" , user_aclk300_jpeg_p, +MUX (0 ,"mout_user_aclk300_jpeg" , mout_user_aclk300_jpeg_p,SRC_TOP5 ,20 ,1 ), -MUX (0 ,"mout_user_aclk300_disp1" , user_aclk300_disp1_p, +MUX (0 ,"mout_user_aclk300_disp1" , mout_user_aclk300_disp1_p,SRC_TOP5 ,24 ,1 ), -MUX (0 ,"mout_user_aclk300_gscl" , user_aclk300_gscl_p, +MUX (0 ,"mout_user_aclk300_gscl" , mout_user_aclk300_gscl_p,SRC_TOP5 ,28 ,1 ), -MUX (0 ,"sclk_mpll" , mpll_p,SRC_TOP6 ,0 ,1 ), -MUX (0 ,"sclk_vpll" , vpll_p,SRC_TOP6 ,4 ,1 ), -MUX (0 ,"sclk_spll" , spll_p,SRC_TOP6 ,8 ,1 ), -MUX (0 ,"sclk_ipll" , ipll_p,SRC_TOP6 ,12 ,1 ), -MUX (0 ,"sclk_rpll" , rpll_p,SRC_TOP6 ,16 ,1 ), -MUX (0 ,"sclk_epll" , epll_p,SRC_TOP6 ,20 ,1 ), -MUX (0 ,"sclk_dpll" , dpll_p,SRC_TOP6 ,24 ,1 ), -MUX (0 ,"sclk_cpll" , cpll_p,SRC_TOP6 ,28 ,1 ), - -MUX (0 ,"mout_sw_aclk400_mscl" , sw_aclk400_mscl_p,SRC_TOP10 ,4 ,1 ), -MUX (0 ,"mout_sw_aclk200" , sw_aclk200_p,SRC_TOP10 ,8 ,1 ), -MUX (0 ,"mout_sw_aclk200_fsys2" , sw_aclk200_fsys2_p, +MUX (0 ,"mout_sclk_mpll" , mout_mpll_p,SRC_TOP6 ,0 ,1 ), +MUX (0 ,"mout_sclk_vpll" , mout_vpll_p,SRC_TOP6 ,4 ,1 ), +MUX (0 ,"mout_sclk_spll" , mout_spll_p,SRC_TOP6 ,8 ,1 ), +MUX (0 ,"mout_sclk_ipll" , mout_ipll_p,SRC_TOP6 ,12 ,1 ), +MUX (0 ,"mout_sclk_rpll" , mout_rpll_p,SRC_TOP6 ,16 ,1 ), +MUX (0 ,"mout_sclk_epll" , mout_epll_p,SRC_TOP6 ,20 ,1 ), +MUX (0 ,"mout_sclk_dpll" , mout_dpll_p,SRC_TOP6 ,24 ,1 ), +MUX (0 ,"mout_sclk_cpll" , mout_cpll_p,SRC_TOP6 ,28 ,1 ), + +MUX (0 ,"mout_sw_aclk400_mscl" , mout_sw_aclk400_mscl_p, +SRC_TOP10 ,4 ,1 ), +MUX (0 ,"mout_sw_aclk200" , mout_sw_aclk200_p,SRC_TOP10 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk200_fsys2" , mout_sw_aclk200_fsys2_p,SRC_TOP10 ,12 ,1 ), -MUX (0 ,"mout_sw_aclk200_fsys" , sw_aclk200_fsys_p,SRC_TOP10 ,28 ,1 ), - -MUX (0 ,"mout_sw_aclk333_432_gscl" , sw_aclk333_432_gscl_p, +MUX (0 ,"mout_sw_aclk200_fsys" , mout_sw_aclk200_fsys_p, +SRC_TOP10 ,28 ,1 ), +MUX (0 ,"mout_sw_aclk333_432_gscl" , mout_sw_aclk333_432_gscl_p,SRC_TOP11 ,0 ,1 ), -MUX (0 ,"mout_sw_aclk66" , sw_aclk66_p,SRC_TOP11 ,8 ,1 ), -MUX (0 ,"mout_sw_aclk266" , sw_aclk266_p,SRC_TOP11 ,20 ,1 ), -MUX (0 ,"mout_sw_aclk166" , sw_aclk166_p,SRC_TOP11 ,24 ,1 ), -MUX (0 ,"mout_sw_aclk333" , sw_aclk333_p,SRC_TOP11 ,28 ,1 ), - -MUX (0 ,"mout_sw_aclk333_g2d" , sw_aclk333_g2d_p,SRC_TOP12 ,8 ,1 ), -MUX (0 ,"mout_sw_aclk266_g2d" , sw_aclk266_g2d_p,SRC_TOP12 ,12 ,1 ), -MUX (0 ,"mout_sw_aclk_g3d" , sw_aclk_g3d_p,SRC_TOP12 ,16 ,1 ), -MUX (0 ,"mout_sw_aclk300_jpeg" , sw_aclk300_jpeg_p,SRC_TOP12 ,20 ,1 ), -MUX (0 ,"mout_sw_aclk300_disp1" , sw_aclk300_disp1_p, +MUX (0 ,"mout_sw_aclk66" , mout_sw_aclk66_p,SRC_TOP11 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk266" , mout_sw_aclk266_p,SRC_TOP11 ,20 ,1 ), +MUX (0 ,"mout_sw_aclk166" , mout_sw_aclk166_p,SRC_TOP11 ,24 ,1 ), +MUX (0 ,"mout_sw_aclk333" , mout_sw_aclk333_p,SRC_TOP11 ,28 ,1 ), + +MUX (0 ,"mout_sw_aclk333_g2d" , mout_sw_aclk333_g2d_p, +SRC_TOP12 ,8 ,1 ), +MUX (0 ,"mout_sw_aclk266_g2d" , mout_sw_aclk266_g2d_p, +SRC_TOP12 ,12 ,1 ), +MUX (0 ,"mout_sw_aclk_g3d" , mout_sw_aclk_g3d_p,SRC_TOP12 ,16 ,1 ), +MUX (0 ,"mout_sw_aclk300_jpeg" , mout_sw_aclk300_jpeg_p, +SRC_TOP12 ,20 ,1 ), +MUX (0 ,"mout_sw_aclk300_disp1" , mout_sw_aclk300_disp1_p,SRC_TOP12 ,24 ,1 ), -MUX (0 ,"mout_sw_aclk300_gscl" , sw_aclk300_gscl_p,SRC_TOP12 ,28 ,1 ), +MUX (0 ,"mout_sw_aclk300_gscl" , mout_sw_aclk300_gscl_p, +SRC_TOP12 ,28 ,1 ),/* DISP1 Block */ -MUX (0 ,"mout_fimd1" , group3_p,SRC_DISP10 ,4 ,1 ), -MUX (0 ,"mout_mipi1" , group2_p,SRC_DISP10 ,16 ,3 ), -MUX (0 ,"mout_dp1" , group2_p,SRC_DISP10 ,20 ,3 ), -MUX (0 ,"mout_pixel" , group2_p,SRC_DISP10 ,24 ,3 ), -MUX (CLK_MOUT_HDMI ,"mout_hdmi" , hdmi_p,SRC_DISP10 ,28 ,1 ), +MUX (0 ,"mout_fimd1" , mout_group3_p,SRC_DISP10 ,4 ,1 ), +MUX (0 ,"mout_mipi1" , mout_group2_p,SRC_DISP10 ,16 ,3 ), +MUX (0 ,"mout_dp1" , mout_group2_p,SRC_DISP10 ,20 ,3 ), +MUX (0 ,"mout_pixel" , mout_group2_p,SRC_DISP10 ,24 ,3 ), +MUX (CLK_MOUT_HDMI ,"mout_hdmi" , mout_hdmi_p,SRC_DISP10 ,28 ,1 ),/* MAU Block */ -MUX (0 ,"mout_maudio0" , maudio0_p,SRC_MAU ,28 ,3 ), +MUX (0 ,"mout_maudio0" , mout_maudio0_p,SRC_MAU ,28 ,3 ),/* FSYS Block */ -MUX (0 ,"mout_usbd301" , group2_p,SRC_FSYS ,4 ,3 ), -MUX (0 ,"mout_mmc0" , group2_p,SRC_FSYS ,8 ,3 ), -MUX (0 ,"mout_mmc1" , group2_p,SRC_FSYS ,12 ,3 ), -MUX (0 ,"mout_mmc2" , group2_p,SRC_FSYS ,16 ,3 ), -MUX (0 ,"mout_usbd300" , group2_p,SRC_FSYS ,20 ,3 ), -MUX (0 ,"mout_unipro" , group2_p,SRC_FSYS ,24 ,3 ), +MUX (0 ,"mout_usbd301" , mout_group2_p,SRC_FSYS ,4 ,3 ), +MUX (0 ,"mout_mmc0" , mout_group2_p,SRC_FSYS ,8 ,3 ), +MUX (0 ,"mout_mmc1" , mout_group2_p,SRC_FSYS ,12 ,3 ), +MUX (0 ,"mout_mmc2" , mout_group2_p,SRC_FSYS ,16 ,3 ), +MUX (0 ,"mout_usbd300" , mout_group2_p,SRC_FSYS ,20 ,3 ), +MUX (0 ,"mout_unipro" , mout_group2_p,SRC_FSYS ,24 ,3 ),/* PERIC Block */ -MUX (0 ,"mout_uart0" , group2_p,SRC_PERIC0 ,4 ,3 ), -MUX (0 ,"mout_uart1" , group2_p,SRC_PERIC0 ,8 ,3 ), -MUX (0 ,"mout_uart2" , group2_p,SRC_PERIC0 ,12 ,3 ), -MUX (0 ,"mout_uart3" , group2_p,SRC_PERIC0 ,16 ,3 ), -MUX (0 ,"mout_pwm" , group2_p,SRC_PERIC0 ,24 ,3 ), -MUX (0 ,"mout_spdif" , spdif_p,SRC_PERIC0 ,28 ,3 ), -MUX (0 ,"mout_audio0" , audio0_p,SRC_PERIC1 ,8 ,3 ), -MUX (0 ,"mout_audio1" , audio1_p,SRC_PERIC1 ,12 ,3 ), -MUX (0 ,"mout_audio2" , audio2_p,SRC_PERIC1 ,16 ,3 ), -MUX (0 ,"mout_spi0" , group2_p,SRC_PERIC1 ,20 ,3 ), -MUX (0 ,"mout_spi1" , group2_p,SRC_PERIC1 ,24 ,3 ), -MUX (0 ,"mout_spi2" , group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_uart0" , mout_group2_p,SRC_PERIC0 ,4 ,3 ), +MUX (0 ,"mout_uart1" , mout_group2_p,SRC_PERIC0 ,8 ,3 ), +MUX (0 ,"mout_uart2" , mout_group2_p,SRC_PERIC0 ,12 ,3 ), +MUX (0 ,"mout_uart3" , mout_group2_p,SRC_PERIC0 ,16 ,3 ), +MUX (0 ,"mout_pwm" , mout_group2_p,SRC_PERIC0 ,24 ,3 ), +MUX (0 ,"mout_spdif" , mout_spdif_p,SRC_PERIC0 ,28 ,3 ), +MUX (0 ,"mout_audio0" , mout_audio0_p,SRC_PERIC1 ,8 ,3 ), +MUX (0 ,"mout_audio1" , mout_audio1_p,SRC_PERIC1 ,12 ,3 ), +MUX (0 ,"mout_audio2" , mout_audio2_p,SRC_PERIC1 ,16 ,3 ), +MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ), +MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ), +MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), };static struct samsung_div_clock exynos5420_div_clks[]__initdata = { --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 1/16 clk: exynos5420: rename parent clocks
In reply to Shaik Ameer BashaQuoted 10 lines · Shaik Ameer Basha
This patch modifies the defined parent clock names as per the exynos5420 datasheet.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 359 ++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 172 deletions(-) mode change 100644 => 100755 drivers/clk/samsung/clk-exynos5420.c
File mode should not be changed.
Signature · 1 line
Tushar Behera
PATCH v3 1/16 clk: exynos5420: rename parent clocks
In reply to Shaik Ameer BashaHi Shaik,
Thanks for splitting the series into reasonably-sized patches. It's much more convenient to review them now.
Quoted 194 lines · Shaik Ameer Basha
This patch modifies the defined parent clock names as per the exynos5420 datasheet.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 359 ++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 172 deletions(-)mode change 100644 => 100755
drivers/clk/samsung/clk-exynos5420.cdrivers/clk/samsung/clk-exynos5420.c +86
-81@@ -217,85 +217,92 @@ static void exynos5420_clk_sleep_init(void) {}#endif /* list of all parent clocks */ -PNAME (mspll_cpu_p) = {"sclk_cpll" ,"sclk_dpll" , -"sclk_mpll" ,"sclk_spll" }; -PNAME (cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; -PNAME (kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; -PNAME (apll_p) = {"fin_pll" ,"fout_apll" , }; -PNAME (bpll_p) = {"fin_pll" ,"fout_bpll" , }; -PNAME (cpll_p) = {"fin_pll" ,"fout_cpll" , }; -PNAME (dpll_p) = {"fin_pll" ,"fout_dpll" , }; -PNAME (epll_p) = {"fin_pll" ,"fout_epll" , }; -PNAME (ipll_p) = {"fin_pll" ,"fout_ipll" , }; -PNAME (kpll_p) = {"fin_pll" ,"fout_kpll" , }; -PNAME (mpll_p) = {"fin_pll" ,"fout_mpll" , }; -PNAME (rpll_p) = {"fin_pll" ,"fout_rpll" , }; -PNAME (spll_p) = {"fin_pll" ,"fout_spll" , }; -PNAME (vpll_p) = {"fin_pll" ,"fout_vpll" , }; - -PNAME (group1_p) = {"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group2_p) = {"fin_pll" ,"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (group3_p) = {"sclk_rpll" ,"sclk_spll" }; -PNAME (group4_p) = {"sclk_ipll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group5_p) = {"sclk_vpll" ,"sclk_dpll" }; - -PNAME (sw_aclk66_p) = {"dout_aclk66" ,"sclk_spll" }; -PNAME (aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; - -PNAME (sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"sclk_spll" }; -PNAME (user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; - -PNAME (sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"sclk_spll" }; -PNAME (user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; - -PNAME (sw_aclk200_p) = {"dout_aclk200" ,"sclk_spll" }; -PNAME (aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; - -PNAME (sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"sclk_spll" }; -PNAME (user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; - -PNAME (sw_aclk333_p) = {"dout_aclk333" ,"sclk_spll" }; -PNAME (user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; - -PNAME (sw_aclk166_p) = {"dout_aclk166" ,"sclk_spll" }; -PNAME (user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; - -PNAME (sw_aclk266_p) = {"dout_aclk266" ,"sclk_spll" }; -PNAME (user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; - -PNAME (sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"sclk_spll" }; -PNAME (user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; - -PNAME (sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"sclk_spll" }; -PNAME (user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; - -PNAME (sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"sclk_spll" }; -PNAME (user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; - -PNAME (sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"sclk_spll" }; -PNAME (user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; - -PNAME (sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"sclk_spll" }; -PNAME (user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; - -PNAME (sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"sclk_spll" }; -PNAME (user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; - -PNAME (sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"sclk_spll" }; -PNAME (user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; - -PNAME (audio0_p) = {"fin_pll" ,"cdclk0" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio1_p) = {"fin_pll" ,"cdclk1" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio2_p) = {"fin_pll" ,"cdclk2" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" ,"dout_audio2" , -"spdif_extclk" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; -PNAME (maudio0_p) = {"fin_pll" ,"maudio_clk" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; +PNAME (mout_mspll_cpu_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" }; +PNAME (mout_cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; +PNAME (mout_kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; +PNAME (mout_apll_p) = {"fin_pll" ,"fout_apll" }; +PNAME (mout_bpll_p) = {"fin_pll" ,"fout_bpll" }; +PNAME (mout_cpll_p) = {"fin_pll" ,"fout_cpll" }; +PNAME (mout_dpll_p) = {"fin_pll" ,"fout_dpll" }; +PNAME (mout_epll_p) = {"fin_pll" ,"fout_epll" }; +PNAME (mout_ipll_p) = {"fin_pll" ,"fout_ipll" }; +PNAME (mout_kpll_p) = {"fin_pll" ,"fout_kpll" }; +PNAME (mout_mpll_p) = {"fin_pll" ,"fout_mpll" }; +PNAME (mout_rpll_p) = {"fin_pll" ,"fout_rpll" }; +PNAME (mout_spll_p) = {"fin_pll" ,"fout_spll" }; +PNAME (mout_vpll_p) = {"fin_pll" ,"fout_vpll" }; + +PNAME (mout_group1_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" }; +PNAME (mout_group2_p) = {"fin_pll" ,"mout_sclk_cpll" , +"mout_sclk_dpll" ,"mout_sclk_mpll" ,"mout_sclk_spll" , +"mout_sclk_ipll" ,"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_group3_p) = {"mout_sclk_rpll" ,"mout_sclk_spll" }; +PNAME (mout_group4_p) = {"mout_sclk_ipll" ,"mout_sclk_dpll" ,"mout_sclk_mpll" }; +PNAME (mout_group5_p) = {"mout_sclk_vpll" ,"mout_sclk_dpll" }; + +PNAME (mout_sw_aclk66_p) = {"dout_aclk66" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; + +PNAME (mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; + +PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; + +PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" }; +PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; + +PNAME (mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; + +PNAME (mout_sw_aclk333_p) = {"dout_aclk333" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; + +PNAME (mout_sw_aclk166_p) = {"dout_aclk166" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; + +PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; + +PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; + +PNAME (mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; + +PNAME (mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; + +PNAME (mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; + +PNAME (mout_sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; + +PNAME (mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; + +PNAME (mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; + +PNAME (mout_audio0_p) = {"fin_pll" ,"cdclk0" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_audio1_p) = {"fin_pll" ,"cdclk1" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_audio2_p) = {"fin_pll" ,"cdclk2" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" , +"dout_audio2" ,"spdif_extclk" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; +PNAME (mout_maudio0_p) = {"fin_pll" ,"maudio_clk" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[]__initdata = {@@ -316,123 +323,131 @@ static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initda };static struct samsung_mux_clock exynos5420_mux_clks[]__initdata = { -MUX (0 ,"mout_mspll_kfc" , mspll_cpu_p,SRC_TOP7 ,8 ,2 ), -MUX (0 ,"mout_mspll_cpu" , mspll_cpu_p,SRC_TOP7 ,12 ,2 ),
drivers/clk/samsung/clk-exynos5420.c static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initda · line 331
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +6
-4-MUX (0 ,"mout_apll" , apll_p,SRC_CPU ,0 ,1 ), -MUX (0 ,"mout_cpu" , cpu_p,SRC_CPU ,16 ,1 ), -MUX (0 ,"mout_kpll" , kpll_p,SRC_KFC ,0 ,1 ), - MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), +MUX (0 ,"mout_mspll_kfc" , mout_mspll_cpu_p,SRC_TOP7 ,8 ,2 ), +MUX (0 ,"mout_mspll_cpu" , mout_mspll_cpu_p,SRC_TOP7 ,12 ,2 ), +MUX (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ), +MUX (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ), +MUX (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 ), + MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
It looks like a lot of changes done in this patch is not actually clock renaming, but rather renaming of parent arrays. Do you really need to rename them? I don't think we need this at least in cases that are just adding "mout_" prefix to variable names, as it's obvious that parent arrays are relevant only to mux clocks.
Best regards,
Tomasz
PATCH v3 1/16 clk: exynos5420: rename parent clocks
Hi Tomasz,
Quoted 237 lines · Tomasz Figa
Hi Shaik,
Thanks for splitting the series into reasonably-sized patches. It's much more convenient to review them now.
Quoted 230 lines · Shaik Ameer Basha
This patch modifies the defined parent clock names as per the exynos5420 datasheet.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 359 ++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 172 deletions(-)mode change 100644 => 100755
drivers/clk/samsung/clk-exynos5420.cdrivers/clk/samsung/clk-exynos5420.c +0
-78@@ -217,85 +217,92 @@ static void exynos5420_clk_sleep_init(void) {}#endif /* list of all parent clocks */ -PNAME (mspll_cpu_p) = {"sclk_cpll" ,"sclk_dpll" , -"sclk_mpll" ,"sclk_spll" }; -PNAME (cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; -PNAME (kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; -PNAME (apll_p) = {"fin_pll" ,"fout_apll" , }; -PNAME (bpll_p) = {"fin_pll" ,"fout_bpll" , }; -PNAME (cpll_p) = {"fin_pll" ,"fout_cpll" , }; -PNAME (dpll_p) = {"fin_pll" ,"fout_dpll" , }; -PNAME (epll_p) = {"fin_pll" ,"fout_epll" , }; -PNAME (ipll_p) = {"fin_pll" ,"fout_ipll" , }; -PNAME (kpll_p) = {"fin_pll" ,"fout_kpll" , }; -PNAME (mpll_p) = {"fin_pll" ,"fout_mpll" , }; -PNAME (rpll_p) = {"fin_pll" ,"fout_rpll" , }; -PNAME (spll_p) = {"fin_pll" ,"fout_spll" , }; -PNAME (vpll_p) = {"fin_pll" ,"fout_vpll" , }; - -PNAME (group1_p) = {"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group2_p) = {"fin_pll" ,"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" , "sclk_rpll" }; -PNAME (group3_p) = {"sclk_rpll" ,"sclk_spll" }; -PNAME (group4_p) = {"sclk_ipll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group5_p) = {"sclk_vpll" ,"sclk_dpll" }; - -PNAME (sw_aclk66_p) = {"dout_aclk66" ,"sclk_spll" }; -PNAME (aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; - -PNAME (sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"sclk_spll" }; -PNAME (user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; - -PNAME (sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"sclk_spll" }; -PNAME (user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; - -PNAME (sw_aclk200_p) = {"dout_aclk200" ,"sclk_spll" }; -PNAME (aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; - -PNAME (sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"sclk_spll" }; -PNAME (user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; - -PNAME (sw_aclk333_p) = {"dout_aclk333" ,"sclk_spll" }; -PNAME (user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; - -PNAME (sw_aclk166_p) = {"dout_aclk166" ,"sclk_spll" }; -PNAME (user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; - -PNAME (sw_aclk266_p) = {"dout_aclk266" ,"sclk_spll" }; -PNAME (user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; - -PNAME (sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"sclk_spll" }; -PNAME (user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; - -PNAME (sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"sclk_spll" }; -PNAME (user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; - -PNAME (sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"sclk_spll" }; -PNAME (user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; - -PNAME (sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"sclk_spll" }; -PNAME (user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; - -PNAME (sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"sclk_spll" }; -PNAME (user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; - -PNAME (sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"sclk_spll" }; -PNAME (user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; - -PNAME (sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"sclk_spll" }; -PNAME (user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; - -PNAME (audio0_p) = {"fin_pll" ,"cdclk0" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio1_p) = {"fin_pll" ,"cdclk1" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio2_p) = {"fin_pll" ,"cdclk2" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" , "dout_audio2", -"spdif_extclk" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; -PNAME (maudio0_p) = {"fin_pll" ,"maudio_clk" ,"sclk_dpll" ,"
sclk_mpll",
- "sclk_spll", "sclk_ipll", "sclk_epll",
"sclk_rpll" };drivers/clk/samsung/clk-exynos5420.c +20
-0+PNAME (mout_mspll_cpu_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" }; +PNAME (mout_cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; +PNAME (mout_kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; +PNAME (mout_apll_p) = {"fin_pll" ,"fout_apll" }; +PNAME (mout_bpll_p) = {"fin_pll" ,"fout_bpll" }; +PNAME (mout_cpll_p) = {"fin_pll" ,"fout_cpll" }; +PNAME (mout_dpll_p) = {"fin_pll" ,"fout_dpll" }; +PNAME (mout_epll_p) = {"fin_pll" ,"fout_epll" }; +PNAME (mout_ipll_p) = {"fin_pll" ,"fout_ipll" }; +PNAME (mout_kpll_p) = {"fin_pll" ,"fout_kpll" }; +PNAME (mout_mpll_p) = {"fin_pll" ,"fout_mpll" }; +PNAME (mout_rpll_p) = {"fin_pll" ,"fout_rpll" }; +PNAME (mout_spll_p) = {"fin_pll" ,"fout_spll" }; +PNAME (mout_vpll_p) = {"fin_pll" ,"fout_vpll" }; + +PNAME (mout_group1_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" }; +PNAME (mout_group2_p) = {"fin_pll" ,"mout_sclk_cpll" , +"mout_sclk_dpll" ,"mout_sclk_mpll" ,"
mout_sclk_spll",
+ "mout_sclk_ipll", "mout_sclk_epll",
"mout_sclk_rpll"};drivers/clk/samsung/clk-exynos5420.c +2
-0+PNAME (mout_group3_p) = {"mout_sclk_rpll" ,"mout_sclk_spll" }; +PNAME (mout_group4_p) = {"mout_sclk_ipll" ,"mout_sclk_dpll" ,"
mout_sclk_mpll"};drivers/clk/samsung/clk-exynos5420.c +7
-0+PNAME (mout_group5_p) = {"mout_sclk_vpll" ,"mout_sclk_dpll" }; + +PNAME (mout_sw_aclk66_p) = {"dout_aclk66" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; + +PNAME (mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys_p) = {"fin_pll" ,"
mout_sw_aclk200_fsys"};drivers/clk/samsung/clk-exynos5420.c +2
-0+ +PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"
mout_sclk_spll"};drivers/clk/samsung/clk-exynos5420.c +7
-0+PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; + +PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" }; +PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; + +PNAME (mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_mscl_p) = {"fin_pll" ,"
mout_sw_aclk400_mscl"};drivers/clk/samsung/clk-exynos5420.c +11
-0+ +PNAME (mout_sw_aclk333_p) = {"dout_aclk333" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; + +PNAME (mout_sw_aclk166_p) = {"dout_aclk166" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; + +PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; + +PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"
mout_sclk_spll"}; +PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};drivers/clk/samsung/clk-exynos5420.c +3
-0+ +PNAME (mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_gscl_p) = {"fin_pll" ,"
mout_sw_aclk300_gscl"};drivers/clk/samsung/clk-exynos5420.c +2
-0+ +PNAME (mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"
mout_sclk_spll"};drivers/clk/samsung/clk-exynos5420.c +16
-0+PNAME (mout_user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; + +PNAME (mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; + +PNAME (mout_sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; + +PNAME (mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; + +PNAME (mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; + +PNAME (mout_audio0_p) = {"fin_pll" ,"cdclk0" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",drivers/clk/samsung/clk-exynos5420.c +3
-0+ "mout_sclk_epll", "mout_sclk_rpll"}; +PNAME (mout_audio1_p ) = {"fin_pll" ,"cdclk1" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",drivers/clk/samsung/clk-exynos5420.c +3
-0+ "mout_sclk_epll", "mout_sclk_rpll"}; +PNAME (mout_audio2_p ) = {"fin_pll" ,"cdclk2" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",drivers/clk/samsung/clk-exynos5420.c +7
-0+ "mout_sclk_epll", "mout_sclk_rpll"}; +PNAME (mout_spdif_p ) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" , +"dout_audio2" ,"spdif_extclk" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; +PNAME (mout_maudio0_p) = {"fin_pll" ,"maudio_clk" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",
+ "mout_sclk_epll", "mout_sclk_rpll"};/* fixed rate clocks generated outside the soc */
static structsamsung_fixed_rate_clockexynos5420_fixed_rate_ext_clks[]__initdata= {drivers/clk/samsung/clk-exynos5420.c +0
-0@@ -316,123 +323,131 @@ static struct samsung_fixed_factor_clockexynos5420_fixed_factor_clks[]
__initda
};static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {drivers/clk/samsung/clk-exynos5420.c +5
-6-MUX (0 ,"mout_mspll_kfc" , mspll_cpu_p,SRC_TOP7 ,8 ,2 ), -MUX (0 ,"mout_mspll_cpu" , mspll_cpu_p,SRC_TOP7 ,12 ,2 ), -MUX (0 ,"mout_apll" , apll_p,SRC_CPU ,0 ,1 ), -MUX (0 ,"mout_cpu" , cpu_p,SRC_CPU ,16 ,1 ), -MUX (0 ,"mout_kpll" , kpll_p,SRC_KFC ,0 ,1 ), - MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), +MUX (0 ,"mout_mspll_kfc" , mout_mspll_cpu_p,SRC_TOP7 ,8 ,2 ), +MUX (0 ,"mout_mspll_cpu" , mout_mspll_cpu_p,SRC_TOP7 ,12 ,2 ), +MUX (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ), +MUX (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ), + MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
Quoted 8 lines
Quoted 1 line
+
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),It looks like a lot of changes done in this patch is not actually clock renaming, but rather renaming of parent arrays. Do you really need to rename them? I don't think we need this at least in cases that are just adding "
mout_" prefix to variable names, as it's obvious that parent arrays are relevant only to mux clocks.
Agreed. But I am trying to follow the naming conventions from exynos5420 and 5620.
I will keep the renaming part and change the subject and commit message as per your comments.
Regards,
Shaik Ameer Basha
Quoted 3 lines
Best regards,
Tomasz
PATCH v3 1/16 clk: exynos5420: rename parent clocks
Quoted 250 lines · Shaik Ameer Basha
Hi Tomasz,
Quoted 237 lines · Tomasz Figa
Hi Shaik,
Thanks for splitting the series into reasonably-sized patches. It's much more convenient to review them now.
Quoted 230 lines · Shaik Ameer Basha
This patch modifies the defined parent clock names as per the exynos5420 datasheet.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 359 ++++++++++++++++++---------------- 1 file changed, 187 insertions(+), 172 deletions(-)mode change 100644 => 100755
drivers/clk/samsung/clk-exynos5420.cdrivers/clk/samsung/clk-exynos5420.c +0
-78@@ -217,85 +217,92 @@ static void exynos5420_clk_sleep_init(void) {}#endif /* list of all parent clocks */ -PNAME (mspll_cpu_p) = {"sclk_cpll" ,"sclk_dpll" , -"sclk_mpll" ,"sclk_spll" }; -PNAME (cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; -PNAME (kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; -PNAME (apll_p) = {"fin_pll" ,"fout_apll" , }; -PNAME (bpll_p) = {"fin_pll" ,"fout_bpll" , }; -PNAME (cpll_p) = {"fin_pll" ,"fout_cpll" , }; -PNAME (dpll_p) = {"fin_pll" ,"fout_dpll" , }; -PNAME (epll_p) = {"fin_pll" ,"fout_epll" , }; -PNAME (ipll_p) = {"fin_pll" ,"fout_ipll" , }; -PNAME (kpll_p) = {"fin_pll" ,"fout_kpll" , }; -PNAME (mpll_p) = {"fin_pll" ,"fout_mpll" , }; -PNAME (rpll_p) = {"fin_pll" ,"fout_rpll" , }; -PNAME (spll_p) = {"fin_pll" ,"fout_spll" , }; -PNAME (vpll_p) = {"fin_pll" ,"fout_vpll" , }; - -PNAME (group1_p) = {"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group2_p) = {"fin_pll" ,"sclk_cpll" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" , "sclk_rpll" }; -PNAME (group3_p) = {"sclk_rpll" ,"sclk_spll" }; -PNAME (group4_p) = {"sclk_ipll" ,"sclk_dpll" ,"sclk_mpll" }; -PNAME (group5_p) = {"sclk_vpll" ,"sclk_dpll" }; - -PNAME (sw_aclk66_p) = {"dout_aclk66" ,"sclk_spll" }; -PNAME (aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; - -PNAME (sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"sclk_spll" }; -PNAME (user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" }; - -PNAME (sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"sclk_spll" }; -PNAME (user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; - -PNAME (sw_aclk200_p) = {"dout_aclk200" ,"sclk_spll" }; -PNAME (aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; - -PNAME (sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"sclk_spll" }; -PNAME (user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" }; - -PNAME (sw_aclk333_p) = {"dout_aclk333" ,"sclk_spll" }; -PNAME (user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; - -PNAME (sw_aclk166_p) = {"dout_aclk166" ,"sclk_spll" }; -PNAME (user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; - -PNAME (sw_aclk266_p) = {"dout_aclk266" ,"sclk_spll" }; -PNAME (user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; - -PNAME (sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"sclk_spll" }; -PNAME (user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" }; - -PNAME (sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"sclk_spll" }; -PNAME (user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" }; - -PNAME (sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"sclk_spll" }; -PNAME (user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; - -PNAME (sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"sclk_spll" }; -PNAME (user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; - -PNAME (sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"sclk_spll" }; -PNAME (user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; - -PNAME (sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"sclk_spll" }; -PNAME (user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; - -PNAME (sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"sclk_spll" }; -PNAME (user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; - -PNAME (audio0_p) = {"fin_pll" ,"cdclk0" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio1_p) = {"fin_pll" ,"cdclk1" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (audio2_p) = {"fin_pll" ,"cdclk2" ,"sclk_dpll" ,"sclk_mpll" , -"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" , "dout_audio2", -"spdif_extclk" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; -PNAME (maudio0_p) = {"fin_pll" ,"maudio_clk" ,"sclk_dpll" ,"
sclk_mpll",
- "sclk_spll", "sclk_ipll", "sclk_epll",
"sclk_rpll" };drivers/clk/samsung/clk-exynos5420.c +20
-0+PNAME (mout_mspll_cpu_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" }; +PNAME (mout_cpu_p) = {"mout_apll" ,"mout_mspll_cpu" }; +PNAME (mout_kfc_p) = {"mout_kpll" ,"mout_mspll_kfc" }; +PNAME (mout_apll_p) = {"fin_pll" ,"fout_apll" }; +PNAME (mout_bpll_p) = {"fin_pll" ,"fout_bpll" }; +PNAME (mout_cpll_p) = {"fin_pll" ,"fout_cpll" }; +PNAME (mout_dpll_p) = {"fin_pll" ,"fout_dpll" }; +PNAME (mout_epll_p) = {"fin_pll" ,"fout_epll" }; +PNAME (mout_ipll_p) = {"fin_pll" ,"fout_ipll" }; +PNAME (mout_kpll_p) = {"fin_pll" ,"fout_kpll" }; +PNAME (mout_mpll_p) = {"fin_pll" ,"fout_mpll" }; +PNAME (mout_rpll_p) = {"fin_pll" ,"fout_rpll" }; +PNAME (mout_spll_p) = {"fin_pll" ,"fout_spll" }; +PNAME (mout_vpll_p) = {"fin_pll" ,"fout_vpll" }; + +PNAME (mout_group1_p) = {"mout_sclk_cpll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" }; +PNAME (mout_group2_p) = {"fin_pll" ,"mout_sclk_cpll" , +"mout_sclk_dpll" ,"mout_sclk_mpll" ,"
mout_sclk_spll",
+ "mout_sclk_ipll", "mout_sclk_epll",
"mout_sclk_rpll"};drivers/clk/samsung/clk-exynos5420.c +2
-0+PNAME (mout_group3_p) = {"mout_sclk_rpll" ,"mout_sclk_spll" }; +PNAME (mout_group4_p) = {"mout_sclk_ipll" ,"mout_sclk_dpll" ,"
mout_sclk_mpll"};drivers/clk/samsung/clk-exynos5420.c +7
-0+PNAME (mout_group5_p) = {"mout_sclk_vpll" ,"mout_sclk_dpll" }; + +PNAME (mout_sw_aclk66_p) = {"dout_aclk66" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; + +PNAME (mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk200_fsys_p) = {"fin_pll" ,"
mout_sw_aclk200_fsys"};drivers/clk/samsung/clk-exynos5420.c +2
-0+ +PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"
mout_sclk_spll"};drivers/clk/samsung/clk-exynos5420.c +7
-0+PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; + +PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" }; +PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; + +PNAME (mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_mscl_p) = {"fin_pll" ,"
mout_sw_aclk400_mscl"};drivers/clk/samsung/clk-exynos5420.c +11
-0+ +PNAME (mout_sw_aclk333_p) = {"dout_aclk333" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_p) = {"fin_pll" ,"mout_sw_aclk333" }; + +PNAME (mout_sw_aclk166_p) = {"dout_aclk166" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk166_p) = {"fin_pll" ,"mout_sw_aclk166" }; + +PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; + +PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"
mout_sclk_spll"}; +PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};drivers/clk/samsung/clk-exynos5420.c +3
-0+ +PNAME (mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_gscl_p) = {"fin_pll" ,"
mout_sw_aclk300_gscl"};drivers/clk/samsung/clk-exynos5420.c +2
-0+ +PNAME (mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"
mout_sclk_spll"};drivers/clk/samsung/clk-exynos5420.c +16
-0+PNAME (mout_user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; + +PNAME (mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" }; + +PNAME (mout_sw_aclk_g3d_p) = {"dout_aclk_g3d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk_g3d_p) = {"fin_pll" ,"mout_sw_aclk_g3d" }; + +PNAME (mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk266_g2d_p) = {"fin_pll" ,"mout_sw_aclk266_g2d" }; + +PNAME (mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_g2d_p) = {"fin_pll" ,"mout_sw_aclk333_g2d" }; + +PNAME (mout_audio0_p) = {"fin_pll" ,"cdclk0" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",drivers/clk/samsung/clk-exynos5420.c +3
-0+ "mout_sclk_epll", "mout_sclk_rpll"}; +PNAME (mout_audio1_p ) = {"fin_pll" ,"cdclk1" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",drivers/clk/samsung/clk-exynos5420.c +3
-0+ "mout_sclk_epll", "mout_sclk_rpll"}; +PNAME (mout_audio2_p ) = {"fin_pll" ,"cdclk2" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",drivers/clk/samsung/clk-exynos5420.c +7
-0+ "mout_sclk_epll", "mout_sclk_rpll"}; +PNAME (mout_spdif_p ) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" , +"dout_audio2" ,"spdif_extclk" ,"mout_sclk_ipll" , +"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" }; +PNAME (mout_maudio0_p) = {"fin_pll" ,"maudio_clk" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" ,"
mout_sclk_ipll",
+ "mout_sclk_epll", "mout_sclk_rpll"};/* fixed rate clocks generated outside the soc */
static structsamsung_fixed_rate_clockexynos5420_fixed_rate_ext_clks[]__initdata= {drivers/clk/samsung/clk-exynos5420.c +0
-0@@ -316,123 +323,131 @@ static struct samsung_fixed_factor_clockexynos5420_fixed_factor_clks[]
__initda
};static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {drivers/clk/samsung/clk-exynos5420.c +5
-6-MUX (0 ,"mout_mspll_kfc" , mspll_cpu_p,SRC_TOP7 ,8 ,2 ), -MUX (0 ,"mout_mspll_cpu" , mspll_cpu_p,SRC_TOP7 ,12 ,2 ), -MUX (0 ,"mout_apll" , apll_p,SRC_CPU ,0 ,1 ), -MUX (0 ,"mout_cpu" , cpu_p,SRC_CPU ,16 ,1 ), -MUX (0 ,"mout_kpll" , kpll_p,SRC_KFC ,0 ,1 ), - MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), +MUX (0 ,"mout_mspll_kfc" , mout_mspll_cpu_p,SRC_TOP7 ,8 ,2 ), +MUX (0 ,"mout_mspll_cpu" , mout_mspll_cpu_p,SRC_TOP7 ,12 ,2 ), +MUX (0 ,"mout_apll" , mout_apll_p,SRC_CPU ,0 ,1 ), +MUX (0 ,"mout_cpu" , mout_cpu_p,SRC_CPU ,16 ,1 ), + MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),Quoted 8 lines
Quoted 1 line
+
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),It looks like a lot of changes done in this patch is not actually clock renaming, but rather renaming of parent arrays. Do you really need to rename them? I don't think we need this at least in cases that are just adding "
mout_" prefix to variable names, as it's obvious that parent arrays are relevant only to mux clocks.
Quoted 2 lines
Agreed. But I am trying to follow the naming conventions from exynos5420 and 5620.
sorry. Its exynos5260
Quoted 9 lines
I will keep the renaming part and change the subject and commit message as per your comments.
Regards,
Shaik Ameer BashaQuoted 3 lines
Best regards,
Tomasz
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
In reply to Shaik Ameer BashaThis patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)
drivers/clk/samsung/clk-exynos5420.c +80 -0
@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288
@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c
@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 ,DIV_TOP1 , DIV_TOP2,
@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 ,GATE_IP_GSCL1 , GATE_IP_MFC,
@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp0" }; + +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp" };PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" };PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" };
@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" };PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" };
@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp0" , mout_user_aclk333_432_isp0_p, +SRC_TOP4 ,12 ,1 ), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, +SRC_TOP4 ,16 ,1 ), + +/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), + MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), }; static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ),DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), + +/* ISP Block */ +DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), +DIV (0 ,"dout_aclk333_432_isp0" ,"mout_aclk333_432_isp0" , +DIV_TOP1 ,16 ,3 ), +DIV (0 ,"dout_aclk333_432_isp" ,"mout_aclk333_432_isp" , +DIV_TOP1 ,4 ,3 ), +DIV (0 ,"dout_pwm_isp" ,"mout_pwm_isp" ,SCLK_DIV_ISP1 ,28 ,4 ), +DIV (0 ,"dout_uart_isp" ,"mout_uart_isp" ,SCLK_DIV_ISP1 ,24 ,4 ), +DIV (0 ,"dout_spi0_isp" ,"mout_spi0_isp" ,SCLK_DIV_ISP1 ,16 ,4 ), +DIV (0 ,"dout_spi1_isp" ,"mout_spi1_isp" ,SCLK_DIV_ISP1 ,20 ,4 ), +DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), +DIV (0 ,"dout_spi1_isp_pre" ,"dout_spi1_isp" ,SCLK_DIV_ISP1 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor0" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor1" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,16 ,8 ), + DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), }; static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
@@ -759,6 +818,27 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +GATE (0 ,"aclk266_isp" ,"mout_user_aclk266_isp" , +GATE_BUS_TOP ,13 ,0 ,0 ), +GATE (0 ,"aclk400_isp" ,"mout_user_aclk400_isp" , +GATE_BUS_TOP ,16 ,0 ,0 ), +GATE (0 ,"aclk333_432_isp0" , +"mout_user_aclk333_432_isp0" ,GATE_BUS_TOP ,5 ,0 ,0 ), +GATE (0 ,"aclk333_432_isp" , +"mout_user_aclk333_432_isp" ,GATE_BUS_TOP ,8 ,0 ,0 ), +/* ISP */ +GATE (0 ,"sclk_pwm_isp" ,"dout_pwm_isp" ,GATE_TOP_SCLK_ISP ,3 ,0 ,0 ), +GATE (0 ,"sclk_uart_isp" ,"dout_uart_isp" ,GATE_TOP_SCLK_ISP ,0 ,0 ,0 ), +GATE (0 ,"sclk_spi0_isp" ,"dout_spi0_isp_pre" , +GATE_TOP_SCLK_ISP ,1 ,0 ,0 ), +GATE (0 ,"sclk_spi1_isp" ,"dout_spi1_isp_pre" , +GATE_TOP_SCLK_ISP ,2 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor0" ,"dout_isp_sensor0" , +GATE_TOP_SCLK_ISP ,4 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor1" ,"dout_isp_sensor1" , +GATE_TOP_SCLK_ISP ,8 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor2" ,"dout_isp_sensor2" , +GATE_TOP_SCLK_ISP ,12 ,0 ,0 ),/* SSS */ GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
Signature · 1 line
1.7.9.5
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
Hi Shaik,
Quoted 97 lines · Shaik Ameer Basha
This patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)drivers/clk/samsung/clk-exynos5420.c +27
-0@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 ,DIV_TOP1 , DIV_TOP2,@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 ,GATE_IP_GSCL1 , GATE_IP_MFC,@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp0" }; + +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp" };PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" };PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" };@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" };PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" };@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), + MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
drivers/clk/samsung/clk-exynos5420.c static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { · line 487
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+ SRC_TOP4, 12, 1), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, + SRC_TOP4, 16, 1), +
It is nice to sort then based on the same order as mentioned in there register discription. Thats really halps in fast review. And to be consistance with other code in this file.
e.g Should have all the SRC_TOP4 in one place, like:MUX(......, SRC_TOP4, 4, 1),MUX(......, SRC_TOP4,12, 1),MUX(......, SRC_TOP4,16, 1),
etc..
drivers/clk/samsung/clk-exynos5420.c static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { · line 494
Quoted 7 lines
drivers/clk/samsung/clk-exynos5420.c +6
-0+/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), + MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), };
Same as above..please sort...
Quoted 7 lines
drivers/clk/samsung/clk-exynos5420.c +1
-0static struct samsung_div_clock exynos5420_div_clks[]__initdata = {@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ),DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ), DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), +
drivers/clk/samsung/clk-exynos5420.c static struct samsung_div_clock exynos5420_div_clks[] __initdata = { · line 584
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+/* ISP Block */ +DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), +DIV (0 ,"dout_aclk333_432_isp0" ,"mout_aclk333_432_isp0" , +DIV_TOP1 ,16 ,3 ), +DIV (0 ,"dout_aclk333_432_isp" ,"mout_aclk333_432_isp" , +DIV_TOP1 ,4 ,3 ), +DIV (0 ,"dout_pwm_isp" ,"mout_pwm_isp" ,SCLK_DIV_ISP1 ,28 ,4 ), +DIV (0 ,"dout_uart_isp" ,"mout_uart_isp" ,SCLK_DIV_ISP1 ,24 ,4 ), +DIV (0 ,"dout_spi0_isp" ,"mout_spi0_isp" ,SCLK_DIV_ISP1 ,16 ,4 ), + DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
Same as above..
drivers/clk/samsung/clk-exynos5420.c static struct samsung_div_clock exynos5420_div_clks[] __initdata = { · line 590
Quoted 6 lines
drivers/clk/samsung/clk-exynos5420.c +5
-0+DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), +DIV (0 ,"dout_spi1_isp_pre" ,"dout_spi1_isp" ,SCLK_DIV_ISP1 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor0" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor1" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,16 ,8 ), + DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), };
This is nice.
Quoted 9 lines
drivers/clk/samsung/clk-exynos5420.c +3
-0static struct samsung_gate_clock exynos5420_gate_clks[]__initdata = {@@ -759,6 +818,27 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +GATE (0 ,"aclk266_isp" ,"mout_user_aclk266_isp" , +GATE_BUS_TOP ,13 ,0 ,0 ), + GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
drivers/clk/samsung/clk-exynos5420.c static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { · line 833
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+ GATE_BUS_TOP, 16, 0, 0), +GATE (0 ,"aclk333_432_isp0" , +"mout_user_aclk333_432_isp0" ,GATE_BUS_TOP ,5 ,0 ,0 ), +GATE (0 ,"aclk333_432_isp" , +"mout_user_aclk333_432_isp" ,GATE_BUS_TOP ,8 ,0 ,0 ), +/* ISP */ +GATE (0 ,"sclk_pwm_isp" ,"dout_pwm_isp" ,GATE_TOP_SCLK_ISP ,3 ,0 ,0 ), +GATE (0 ,"sclk_uart_isp" ,"dout_uart_isp" ,GATE_TOP_SCLK_ISP ,0 ,0 ,0 ), +GATE (0 ,"sclk_spi0_isp" ,"dout_spi0_isp_pre" , + GATE_TOP_SCLK_ISP, 1, 0, 0),
same as above...please sort..
drivers/clk/samsung/clk-exynos5420.c static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { · line 842
Quoted 9 lines
drivers/clk/samsung/clk-exynos5420.c +8
-0+GATE (0 ,"sclk_spi1_isp" ,"dout_spi1_isp_pre" , +GATE_TOP_SCLK_ISP ,2 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor0" ,"dout_isp_sensor0" , +GATE_TOP_SCLK_ISP ,4 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor1" ,"dout_isp_sensor1" , +GATE_TOP_SCLK_ISP ,8 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor2" ,"dout_isp_sensor2" , + GATE_TOP_SCLK_ISP, 12, 0, 0),
Over all looks good.
Reviewed-by Alim Akhtar <[email protected]>
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +0
-1/* SSS */ GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
Hi Alim,
Thanks for the review comments.
Quoted 111 lines · Alim Akhtar
Hi Shaik,
Quoted 97 lines · Shaik Ameer Basha
This patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)drivers/clk/samsung/clk-exynos5420.c +27
-0@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 ,DIV_TOP1 , DIV_TOP2,@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 ,GATE_IP_GSCL1 , GATE_IP_MFC,@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp0" }; + +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp" };PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" };PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" };@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" };PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" };@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), + MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,drivers/clk/samsung/clk-exynos5420.c static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { · line 487
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+ SRC_TOP4, 12, 1), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, + SRC_TOP4, 16, 1), +
Quoted 8 lines
It is nice to sort then based on the same order as mentioned in there register discription. Thats really halps in fast review. And to be consistance with other code in this file.
e.g Should have all theSRC_TOP4in one place, like:MUX(......, SRC_TOP4, 4, 1),MUX(......, SRC_TOP4,12, 1),MUX(......, SRC_TOP4,16, 1),
etc..
Ok. Will update in the next series.
Will take care of the same for all the patches in this series.
Regards,
Shaik Ameer Basha
Quoted 82 lines
drivers/clk/samsung/clk-exynos5420.c static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { · line 494
Quoted 8 lines
drivers/clk/samsung/clk-exynos5420.c +6
-0+/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), + MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), };Same as above..please sort...
Quoted 7 lines
drivers/clk/samsung/clk-exynos5420.c +1
-0static struct samsung_div_clock exynos5420_div_clks[]__initdata = {@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ),DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ), DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), +drivers/clk/samsung/clk-exynos5420.c static struct samsung_div_clock exynos5420_div_clks[] __initdata = { · line 584
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+/* ISP Block */ +DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), +DIV (0 ,"dout_aclk333_432_isp0" ,"mout_aclk333_432_isp0" , +DIV_TOP1 ,16 ,3 ), +DIV (0 ,"dout_aclk333_432_isp" ,"mout_aclk333_432_isp" , +DIV_TOP1 ,4 ,3 ), +DIV (0 ,"dout_pwm_isp" ,"mout_pwm_isp" ,SCLK_DIV_ISP1 ,28 ,4 ), +DIV (0 ,"dout_uart_isp" ,"mout_uart_isp" ,SCLK_DIV_ISP1 ,24 ,4 ), +DIV (0 ,"dout_spi0_isp" ,"mout_spi0_isp" ,SCLK_DIV_ISP1 ,16 ,4 ), + DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),Same as above..
drivers/clk/samsung/clk-exynos5420.c static struct samsung_div_clock exynos5420_div_clks[] __initdata = { · line 590
Quoted 6 lines
drivers/clk/samsung/clk-exynos5420.c +5
-0+DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), +DIV (0 ,"dout_spi1_isp_pre" ,"dout_spi1_isp" ,SCLK_DIV_ISP1 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor0" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor1" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,16 ,8 ), + DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), };This is nice.
Quoted 9 lines
drivers/clk/samsung/clk-exynos5420.c +3
-0static struct samsung_gate_clock exynos5420_gate_clks[]__initdata = {@@ -759,6 +818,27 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +GATE (0 ,"aclk266_isp" ,"mout_user_aclk266_isp" , +GATE_BUS_TOP ,13 ,0 ,0 ), + GATE(0, "aclk400_isp", "mout_user_aclk400_isp",drivers/clk/samsung/clk-exynos5420.c static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { · line 833
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+ GATE_BUS_TOP, 16, 0, 0), +GATE (0 ,"aclk333_432_isp0" , +"mout_user_aclk333_432_isp0" ,GATE_BUS_TOP ,5 ,0 ,0 ), +GATE (0 ,"aclk333_432_isp" , +"mout_user_aclk333_432_isp" ,GATE_BUS_TOP ,8 ,0 ,0 ), +/* ISP */ +GATE (0 ,"sclk_pwm_isp" ,"dout_pwm_isp" ,GATE_TOP_SCLK_ISP ,3 ,0 ,0 ), +GATE (0 ,"sclk_uart_isp" ,"dout_uart_isp" ,GATE_TOP_SCLK_ISP ,0 ,0 ,0 ), +GATE (0 ,"sclk_spi0_isp" ,"dout_spi0_isp_pre" , + GATE_TOP_SCLK_ISP, 1, 0, 0),same as above...please sort..
drivers/clk/samsung/clk-exynos5420.c static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { · line 842
Quoted 9 lines
drivers/clk/samsung/clk-exynos5420.c +8
-0+GATE (0 ,"sclk_spi1_isp" ,"dout_spi1_isp_pre" , +GATE_TOP_SCLK_ISP ,2 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor0" ,"dout_isp_sensor0" , +GATE_TOP_SCLK_ISP ,4 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor1" ,"dout_isp_sensor1" , +GATE_TOP_SCLK_ISP ,8 ,0 ,0 ), +GATE (0 ,"sclk_isp_sensor2" ,"dout_isp_sensor2" , + GATE_TOP_SCLK_ISP, 12, 0, 0),Over all looks good.
Reviewed-by Alim Akhtar <[email protected]>Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +0
-1/* SSS */ GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), --1.7.9.5
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Regards,
Alim
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
In reply to Shaik Ameer BashaHi Shaik,
Quoted 123 lines · Shaik Ameer Basha
This patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)drivers/clk/samsung/clk-exynos5420.c +46
-0@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 ,DIV_TOP1 , DIV_TOP2,@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 ,GATE_IP_GSCL1 , GATE_IP_MFC,@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp0" }; + +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp" };PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" };PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" };@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" };PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" };@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp0" , mout_user_aclk333_432_isp0_p, +SRC_TOP4 ,12 ,1 ), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, +SRC_TOP4 ,16 ,1 ), + +/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), + MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), }; static struct samsung_div_clock exynos5420_div_clks[] __initdata = {@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ),DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), + +/* ISP Block */ + DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
drivers/clk/samsung/clk-exynos5420.c static struct samsung_div_clock exynos5420_div_clks[] __initdata = { · line 586
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +10
-0+DIV (0 ,"dout_aclk333_432_isp0" ,"mout_aclk333_432_isp0" , +DIV_TOP1 ,16 ,3 ), +DIV (0 ,"dout_aclk333_432_isp" ,"mout_aclk333_432_isp" , +DIV_TOP1 ,4 ,3 ), +DIV (0 ,"dout_pwm_isp" ,"mout_pwm_isp" ,SCLK_DIV_ISP1 ,28 ,4 ), +DIV (0 ,"dout_uart_isp" ,"mout_uart_isp" ,SCLK_DIV_ISP1 ,24 ,4 ), +DIV (0 ,"dout_spi0_isp" ,"mout_spi0_isp" ,SCLK_DIV_ISP1 ,16 ,4 ), +DIV (0 ,"dout_spi1_isp" ,"mout_spi1_isp" ,SCLK_DIV_ISP1 ,20 ,4 ), +DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), + DIV(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8),
I think we should have the SET_RATE_PARENT flag set here so that both dividers can be configured together when clk_set_rate() is being called on the _pre clock.
Best regards,
Tomasz
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
Quoted 147 lines · Tomasz Figa
Hi Shaik,
Quoted 144 lines · Shaik Ameer Basha
This patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)drivers/clk/samsung/clk-exynos5420.c +5
-0@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 , DIV_TOP1,DIV_TOP2,drivers/clk/samsung/clk-exynos5420.c +3
-0@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 , GATE_IP_GSCL1,
GATE_IP_MFC,drivers/clk/samsung/clk-exynos5420.c +6
-0@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"
mout_sw_aclk333_432_isp0"};drivers/clk/samsung/clk-exynos5420.c +2
-0+ +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"
mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll",
"mout_sw_aclk333_432_isp"};PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};drivers/clk/samsung/clk-exynos5420.c +1
-0@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"
mout_sclk_spll"};
PNAME(mout_user_aclk333_432_gscl_p)= {"fin_pll",
"mout_sw_aclk333_432_gscl"};drivers/clk/samsung/clk-exynos5420.c +25
-0@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp0" , mout_user_aclk333_432_isp0_p, +SRC_TOP4 ,12 ,1 ), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, +SRC_TOP4 ,16 ,1 ), + +/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), +MUX (0 ,"mout_isp_sensor" , mout_group2_p,SRC_ISP ,28 ,3 ), };static struct samsung_div_clock exynos5420_div_clks[] __initdata = {drivers/clk/samsung/clk-exynos5420.c +9
-0@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), + +/* ISP Block */ + DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), + DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", + DIV_TOP1, 16, 3), + DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", + DIV_TOP1, 4, 3), + DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), + DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
Quoted 8 lines
drivers/clk/samsung/clk-exynos5420.c static struct samsung_div_clock exynos5420_div_clks[] __initdata = { · line 586
Quoted 4 lines
drivers/clk/samsung/clk-exynos5420.c +4
-0+DIV (0 ,"dout_spi0_isp" ,"mout_spi0_isp" ,SCLK_DIV_ISP1 ,16 ,4 ), +DIV (0 ,"dout_spi1_isp" ,"mout_spi1_isp" ,SCLK_DIV_ISP1 ,20 ,4 ), +DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), + DIV(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8),I think we should have the
SET_RATE_PARENTflag set here so that both dividers can be configured together whenclk_set_rate()is being called on the_preclock.
Actually the same is also true for all the SCLK gate clocks that have dividers as their parents, so that a driver can just take a reference to the gate clock and control rate of the clock without references to particular dividers.
Best regards,
Tomasz
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
Hi Tomasz,
Thanks for the review comments.
Quoted 161 lines · Tomasz Figa
Quoted 150 lines · Tomasz Figa
Hi Shaik,
Quoted 146 lines · Shaik Ameer Basha
This patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)drivers/clk/samsung/clk-exynos5420.c +5
-0@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 , DIV_TOP1,DIV_TOP2,drivers/clk/samsung/clk-exynos5420.c +3
-0@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 , GATE_IP_GSCL1,
GATE_IP_MFC,drivers/clk/samsung/clk-exynos5420.c +6
-0@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"
mout_sw_aclk333_432_isp0"};drivers/clk/samsung/clk-exynos5420.c +2
-0+ +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"
mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll",
"mout_sw_aclk333_432_isp"};PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};drivers/clk/samsung/clk-exynos5420.c +1
-0@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"
mout_sclk_spll"};
PNAME(mout_user_aclk333_432_gscl_p)= {"fin_pll",
"mout_sw_aclk333_432_gscl"};drivers/clk/samsung/clk-exynos5420.c +25
-0@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp0" , mout_user_aclk333_432_isp0_p, +SRC_TOP4 ,12 ,1 ), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, +SRC_TOP4 ,16 ,1 ), + +/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), +MUX (0 ,"mout_isp_sensor" , mout_group2_p,SRC_ISP ,28 ,3 ), };static struct samsung_div_clock exynos5420_div_clks[] __initdata = {drivers/clk/samsung/clk-exynos5420.c +10
-0@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), + +/* ISP Block */ + DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), + DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", + DIV_TOP1, 16, 3), + DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", + DIV_TOP1, 4, 3), + DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), + DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), + DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),Quoted 8 lines
drivers/clk/samsung/clk-exynos5420.c static struct samsung_div_clock exynos5420_div_clks[] __initdata = { · line 586
Quoted 3 lines
drivers/clk/samsung/clk-exynos5420.c +3
-0+DIV (0 ,"dout_spi1_isp" ,"mout_spi1_isp" ,SCLK_DIV_ISP1 ,20 ,4 ), +DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), + DIV(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8),I think we should have the
SET_RATE_PARENTflag set here so that both dividers can be configured together whenclk_set_rate()is being called on the_preclock.
Quoted 4 lines
Actually the same is also true for all the SCLK gate clocks that have dividers as their parents, so that a driver can just take a reference to the gate clock and control rate of the clock without references to particular dividers.
Ok. Will take care in next series.
Regards,
Shaik Ameer Basha
Quoted 4 lines
Best regards,
Tomasz
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
In reply to Shaik Ameer BashaQuoted 141 lines · Shaik Ameer Basha
This patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)drivers/clk/samsung/clk-exynos5420.c +59
-0@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 ,DIV_TOP1 , DIV_TOP2,@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 ,GATE_IP_GSCL1 , GATE_IP_MFC,@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp0" }; + +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp" };PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" };PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" };@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"mout_sclk_spll" };PNAME (mout_user_aclk333_432_gscl_p) = {"fin_pll" ,"mout_sw_aclk333_432_gscl" };@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp0" , mout_user_aclk333_432_isp0_p, +SRC_TOP4 ,12 ,1 ), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, +SRC_TOP4 ,16 ,1 ), + +/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), + MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), }; static struct samsung_div_clock exynos5420_div_clks[] __initdata = {@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ),DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), + +/* ISP Block */ +DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), +DIV (0 ,"dout_aclk333_432_isp0" ,"mout_aclk333_432_isp0" , +DIV_TOP1 ,16 ,3 ), +DIV (0 ,"dout_aclk333_432_isp" ,"mout_aclk333_432_isp" , +DIV_TOP1 ,4 ,3 ), +DIV (0 ,"dout_pwm_isp" ,"mout_pwm_isp" ,SCLK_DIV_ISP1 ,28 ,4 ), +DIV (0 ,"dout_uart_isp" ,"mout_uart_isp" ,SCLK_DIV_ISP1 ,24 ,4 ), +DIV (0 ,"dout_spi0_isp" ,"mout_spi0_isp" ,SCLK_DIV_ISP1 ,16 ,4 ), +DIV (0 ,"dout_spi1_isp" ,"mout_spi1_isp" ,SCLK_DIV_ISP1 ,20 ,4 ), +DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), +DIV (0 ,"dout_spi1_isp_pre" ,"dout_spi1_isp" ,SCLK_DIV_ISP1 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor0" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor1" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,16 ,8 ), + DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), }; static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {@@ -759,6 +818,27 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 0),
drivers/clk/samsung/clk-exynos5420.c static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { · line 828
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +8
-0GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +GATE (0 ,"aclk266_isp" ,"mout_user_aclk266_isp" , +GATE_BUS_TOP ,13 ,0 ,0 ), +GATE (0 ,"aclk400_isp" ,"mout_user_aclk400_isp" , +GATE_BUS_TOP ,16 ,0 ,0 ), +GATE (0 ,"aclk333_432_isp0" , +"mout_user_aclk333_432_isp0" ,GATE_BUS_TOP ,5 ,0 ,0 ), +GATE (0 ,"aclk333_432_isp" , + "mout_user_aclk333_432_isp", GATE_BUS_TOP, 8, 0, 0),
What are these 4 gate clocks needed for? Do we really need this kind of gating granularity? Isn't there a gate bit in one of GATE_IP_* registers?
Best regards,
Tomasz
PATCH v3 2/16 clk: exynos5420: add clocks for ISP block
Hi Tomasz,
Quoted 169 lines · Tomasz Figa
Quoted 168 lines · Shaik Ameer Basha
This patch adds missing clocks for ISP block
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+)drivers/clk/samsung/clk-exynos5420.c +5
-0@@ -57,6 +57,7 @@#define SRC_FSYS 0x10244#define SRC_PERIC0 0x10250#define SRC_PERIC1 0x10254 +#define SRC_ISP 0x10270#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288@@ -77,12 +78,15 @@#define DIV_PERIC2 0x10560#define DIV_PERIC3 0x10564#define DIV_PERIC4 0x10568 +#define SCLK_DIV_ISP0 0x10580 +#define SCLK_DIV_ISP1 0x10584#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920#define GATE_IP_MFC 0x1092c@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_MASK_FSYS ,SRC_MASK_PERIC0 ,SRC_MASK_PERIC1 , +SRC_ISP ,DIV_TOP0 , DIV_TOP1,DIV_TOP2,drivers/clk/samsung/clk-exynos5420.c +3
-0@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC2 ,DIV_PERIC3 ,DIV_PERIC4 , +SCLK_DIV_ISP0 , +SCLK_DIV_ISP1 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 , GATE_IP_GSCL1,
GATE_IP_MFC,drivers/clk/samsung/clk-exynos5420.c +8
-0@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" }; + +PNAME (mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0" , +"mout_sclk_spll" }; +PNAME (mout_user_aclk333_432_isp0_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp0" }; + +PNAME (mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp" ,"
mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll",
"mout_sw_aclk333_432_isp"};PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};drivers/clk/samsung/clk-exynos5420.c +1
-0@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};PNAME (mout_sw_aclk266_p) = {"dout_aclk266" ,"mout_sclk_spll" };PNAME (mout_user_aclk266_p) = {"fin_pll" ,"mout_sw_aclk266" }; +PNAME (mout_user_aclk266_isp_p) = {"fin_pll" ,"mout_sw_aclk266" };PNAME (mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl" ,"
mout_sclk_spll"};
PNAME(mout_user_aclk333_432_gscl_p)= {"fin_pll",
"mout_sw_aclk333_432_gscl"};drivers/clk/samsung/clk-exynos5420.c +25
-0@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[]__initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ), +MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, +SRC_TOP10 ,0 ,1 ), +MUX (0 ,"mout_user_aclk400_isp" , mout_user_aclk400_isp_p, +SRC_TOP3 ,0 ,1 ), +MUX (0 ,"mout_aclk333_432_isp0" , mout_group4_p,SRC_TOP1 ,12 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp0" , mout_sw_aclk333_432_isp0_p, +SRC_TOP11 ,12 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp0" , mout_user_aclk333_432_isp0_p, +SRC_TOP4 ,12 ,1 ), +MUX (0 ,"mout_aclk333_432_isp" , mout_group4_p, +SRC_TOP1 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk333_432_isp" , mout_sw_aclk333_432_isp_p, +SRC_TOP11 ,4 ,1 ), +MUX (0 ,"mout_user_aclk333_432_isp" , mout_user_aclk333_432_isp_p, +SRC_TOP4 ,4 ,1 ), +MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p, +SRC_TOP4 ,16 ,1 ), + +/* ISP Block */ +MUX (0 ,"mout_pwm_isp" , mout_group2_p,SRC_ISP ,24 ,3 ), +MUX (0 ,"mout_uart_isp" , mout_group2_p,SRC_ISP ,20 ,3 ), +MUX (0 ,"mout_spi0_isp" , mout_group2_p,SRC_ISP ,12 ,3 ), +MUX (0 ,"mout_spi1_isp" , mout_group2_p,SRC_ISP ,16 ,3 ), +MUX (0 ,"mout_isp_sensor" , mout_group2_p,SRC_ISP ,28 ,3 ), };static struct samsung_div_clock exynos5420_div_clks[] __initdata = {drivers/clk/samsung/clk-exynos5420.c +16
-0@@ -528,6 +571,22 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ),DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), + +/* ISP Block */ +DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), +DIV (0 ,"dout_aclk333_432_isp0" ,"mout_aclk333_432_isp0" , +DIV_TOP1 ,16 ,3 ), +DIV (0 ,"dout_aclk333_432_isp" ,"mout_aclk333_432_isp" , +DIV_TOP1 ,4 ,3 ), +DIV (0 ,"dout_pwm_isp" ,"mout_pwm_isp" ,SCLK_DIV_ISP1 ,28 ,4 ), +DIV (0 ,"dout_uart_isp" ,"mout_uart_isp" ,SCLK_DIV_ISP1 ,24 ,4 ), +DIV (0 ,"dout_spi0_isp" ,"mout_spi0_isp" ,SCLK_DIV_ISP1 ,16 ,4 ), +DIV (0 ,"dout_spi1_isp" ,"mout_spi1_isp" ,SCLK_DIV_ISP1 ,20 ,4 ), +DIV (0 ,"dout_spi0_isp_pre" ,"dout_spi0_isp" ,SCLK_DIV_ISP1 ,0 ,8 ), +DIV (0 ,"dout_spi1_isp_pre" ,"dout_spi1_isp" ,SCLK_DIV_ISP1 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor0" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,8 ,8 ), +DIV (0 ,"dout_isp_sensor1" ,"mout_isp_sensor" ,SCLK_DIV_ISP0 ,16 ,8 ), + DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24,8),
};static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {drivers/clk/samsung/clk-exynos5420.c +5
-0@@ -759,6 +818,27 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +GATE (0 ,"aclk266_isp" ,"mout_user_aclk266_isp" , +GATE_BUS_TOP ,13 ,0 ,0 ), +GATE (0 ,"aclk400_isp" ,"mout_user_aclk400_isp" , +GATE_BUS_TOP ,16 ,0 ,0 ), + GATE(0, "aclk333_432_isp0",
Quoted 8 lines
Quoted 5 lines
drivers/clk/samsung/clk-exynos5420.c +3
-0+ "mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0), + GATE(0, "aclk333_432_isp", + "mout_user_aclk333_432_isp", GATE_BUS_TOP, 8, 0,0),
What are these 4 gate clocks needed for? Do we really need this kind of
These are the clocks coming out of CMU_TOP and provided to the ISP block. These clocks are provided to IPs like ISP, DRC, SCALERC, SCALERP, Coreted-A5, FD etc.,
Actually there are gates specific to each IP after the above four gates. CMU_TOP ---> Above Four Gates ---> Gates specific to ISP IPs ---> ISP IPs
Above four gates will not be used directly by any driver.
Quoted 1 line
gating granularity? Isn't there a gate bit in one of GATE_IP_* registers?
Yes, these clocks doesn't have gate bits in any of GATE_IP_* registers.
Regards,
Shaik Ameer Basha
Quoted 3 lines
Best regards,
Tomasz
PATCH v3 3/16 clk: exynos5420: update clocks for GSCL and MSCL blocks
In reply to Shaik Ameer BashaThis patch adds the missing GSCL and MSCL block clocks and corrects some wrong parent-child relationships.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 41 +++++++++++++++++++++----------- include/dt-bindings/clock/exynos5420.h | 2 +- 2 files changed, 28 insertions(+), 15 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +27 -14
@@ -80,6 +80,7 @@#define DIV_PERIC4 0x10568#define SCLK_DIV_ISP0 0x10580#define SCLK_DIV_ISP1 0x10584 +#define DIV2_RATIO0 0x10590#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750
@@ -165,6 +166,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC4 ,SCLK_DIV_ISP0 ,SCLK_DIV_ISP1 , +DIV2_RATIO0 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 , GATE_BUS_PERIC,
@@ -572,6 +574,11 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), +/* GSCL Block */ +DIV (0 ,"dout_gscl_blk_300" ,"mout_user_aclk300_gscl" , +DIV2_RATIO0 ,4 ,2 ), +DIV (0 ,"dout_gscl_blk_333" ,"aclk333_432_gscl" ,DIV2_RATIO0 ,6 ,2 ), +/* ISP Block */ DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
@@ -666,9 +673,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_SCLK_USBD301 ,"sclk_unipro" ,"dout_unipro" ,SRC_MASK_FSYS ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (CLK_SCLK_GSCL_WA ,"sclk_gscl_wa" ,"aclK333_432_gscl" , +GATE (CLK_SCLK_GSCL_WA ,"sclk_gscl_wa" ,"mout_user_aclk333_432_gscl" ,GATE_TOP_SCLK_GSCL ,6 ,CLK_SET_RATE_PARENT ,0 ), -GATE (CLK_SCLK_GSCL_WB ,"sclk_gscl_wb" ,"aclk333_432_gscl" , +GATE (CLK_SCLK_GSCL_WB ,"sclk_gscl_wb" ,"mout_user_aclk333_432_gscl" , GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),/* Display */
@@ -766,22 +773,25 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_GSCL0 ,"gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,0 ,0 ,0 ),GATE (CLK_GSCL1 ,"gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,1 ,0 ,0 ), -GATE (CLK_CLK_3AA ,"clk_3aa" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,4 ,0 ,0 ), +GATE (CLK_FIMC_3AA ,"fimc_3aa" ,"aclk333_432_gscl" , +GATE_IP_GSCL0 ,4 ,0 ,0 ), -GATE (CLK_SMMU_3AA ,"smmu_3aa" ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,2 ,0 , -0 ), -GATE (CLK_SMMU_FIMCL0 ,"smmu_fimcl0" ,"aclk333_432_gscl" , +GATE (CLK_SMMU_3AA ,"smmu_3aa" ,"dout_gscl_blk_333" , +GATE_IP_GSCL1 ,2 ,0 ,0 ), +GATE (CLK_SMMU_FIMCL0 ,"smmu_fimcl0" ,"dout_gscl_blk_333" ,GATE_IP_GSCL1 ,3 ,0 ,0 ), -GATE (CLK_SMMU_FIMCL1 ,"smmu_fimcl1" ,"aclk333_432_gscl" , +GATE (CLK_SMMU_FIMCL1 ,"smmu_fimcl1" ,"dout_gscl_blk_333" ,GATE_IP_GSCL1 ,4 ,0 ,0 ), -GATE (CLK_SMMU_GSCL0 ,"smmu_gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,6 ,0 , -0 ), -GATE (CLK_SMMU_GSCL1 ,"smmu_gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,7 ,0 , -0 ), -GATE (CLK_GSCL_WA ,"gscl_wa" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,12 ,0 ,0 ), -GATE (CLK_GSCL_WB ,"gscl_wb" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,13 ,0 ,0 ), -GATE (CLK_SMMU_FIMCL3 ,"smmu_fimcl3," ,"aclk333_432_gscl" , +GATE (CLK_SMMU_GSCL0 ,"smmu_gscl0" ,"dout_gscl_blk_300" , +GATE_IP_GSCL1 ,6 ,0 ,0 ), +GATE (CLK_SMMU_GSCL1 ,"smmu_gscl1" ,"dout_gscl_blk_300" , +GATE_IP_GSCL1 ,7 ,0 ,0 ), +GATE (CLK_GSCL_WA ,"gscl_wa" ,"sclk_gscl_wa" ,GATE_IP_GSCL1 ,12 ,0 ,0 ), +GATE (CLK_GSCL_WB ,"gscl_wb" ,"sclk_gscl_wb" ,GATE_IP_GSCL1 ,13 ,0 ,0 ), +GATE (CLK_SMMU_FIMCL3 ,"smmu_fimcl3," ,"dout_gscl_blk_333" ,GATE_IP_GSCL1 ,16 ,0 ,0 ), +GATE (0 ,"fimc_lite0" ,"aclk333_432_gscl" ,GATE_IP_GSCL0 ,5 ,0 ,0 ), +GATE (0 ,"fimc_lite1" ,"aclk333_432_gscl" ,GATE_IP_GSCL0 ,6 ,0 ,0 ),GATE (CLK_FIMC_LITE3 ,"fimc_lite3" ,"aclk333_432_gscl" , GATE_IP_GSCL1, 17, 0, 0),
@@ -818,6 +828,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +/* gating of aclk300_gscl causes system hang. It should not be gated. */ +GATE (CLK_ACLK400_MSCL ,"aclk400_mscl" ,"mout_user_aclk400_mscl" , +GATE_BUS_TOP ,17 ,CLK_IGNORE_UNUSED ,0 ),GATE (0 ,"aclk266_isp" ,"mout_user_aclk266_isp" ,GATE_BUS_TOP ,13 ,0 ,0 ), GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
include/dt-bindings/clock/exynos5420.h +1 -1
@@ -159,7 +159,7 @@#define CLK_GSCL_WB 464#define CLK_GSCL0 465#define CLK_GSCL1 466 -#define CLK_CLK_3AA 467 +#define CLK_FIMC_3AA 467#define CLK_ACLK266_G2D 470#define CLK_SSS 471#define CLK_SLIM_SSS 472
Signature · 1 line
1.7.9.5
PATCH v3 3/16 clk: exynos5420: update clocks for GSCL and MSCL blocks
Hi Shaik
Quoted 6 lines · Shaik Ameer Basha
This patch adds the missing GSCL and MSCL block clocks and corrects some wrong parent-child relationships.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>---
Looks ok
Reviewed-by Alim Akhtar <[email protected]>
Quoted 87 lines
drivers/clk/samsung/clk-exynos5420.c | 41 +++++++++++++++++++++----------- include/dt-bindings/clock/exynos5420.h | 2 +- 2 files changed, 28 insertions(+), 15 deletions(-)drivers/clk/samsung/clk-exynos5420.c +24
-14@@ -80,6 +80,7 @@#define DIV_PERIC4 0x10568#define SCLK_DIV_ISP0 0x10580#define SCLK_DIV_ISP1 0x10584 +#define DIV2_RATIO0 0x10590#define GATE_BUS_TOP 0x10700#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750@@ -165,6 +166,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_PERIC4 ,SCLK_DIV_ISP0 ,SCLK_DIV_ISP1 , +DIV2_RATIO0 ,GATE_BUS_TOP ,GATE_BUS_FSYS0 , GATE_BUS_PERIC,@@ -572,6 +574,11 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), +/* GSCL Block */ +DIV (0 ,"dout_gscl_blk_300" ,"mout_user_aclk300_gscl" , +DIV2_RATIO0 ,4 ,2 ), +DIV (0 ,"dout_gscl_blk_333" ,"aclk333_432_gscl" ,DIV2_RATIO0 ,6 ,2 ), +/* ISP Block */ DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",@@ -666,9 +673,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_SCLK_USBD301 ,"sclk_unipro" ,"dout_unipro" ,SRC_MASK_FSYS ,24 ,CLK_SET_RATE_PARENT ,0 ), -GATE (CLK_SCLK_GSCL_WA ,"sclk_gscl_wa" ,"aclK333_432_gscl" , +GATE (CLK_SCLK_GSCL_WA ,"sclk_gscl_wa" ,"mout_user_aclk333_432_gscl" ,GATE_TOP_SCLK_GSCL ,6 ,CLK_SET_RATE_PARENT ,0 ), -GATE (CLK_SCLK_GSCL_WB ,"sclk_gscl_wb" ,"aclk333_432_gscl" , +GATE (CLK_SCLK_GSCL_WB ,"sclk_gscl_wb" ,"mout_user_aclk333_432_gscl" , GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),/* Display */ @@ -766,22 +773,25 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_GSCL0 ,"gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,0 ,0 ,0 ),GATE (CLK_GSCL1 ,"gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,1 ,0 ,0 ), -GATE (CLK_CLK_3AA ,"clk_3aa" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,4 ,0 ,0 ), +GATE (CLK_FIMC_3AA ,"fimc_3aa" ,"aclk333_432_gscl" , +GATE_IP_GSCL0 ,4 ,0 ,0 ), -GATE (CLK_SMMU_3AA ,"smmu_3aa" ,"aclk333_432_gscl" ,GATE_IP_GSCL1 ,2 ,0 , -0 ), -GATE (CLK_SMMU_FIMCL0 ,"smmu_fimcl0" ,"aclk333_432_gscl" , +GATE (CLK_SMMU_3AA ,"smmu_3aa" ,"dout_gscl_blk_333" , +GATE_IP_GSCL1 ,2 ,0 ,0 ), +GATE (CLK_SMMU_FIMCL0 ,"smmu_fimcl0" ,"dout_gscl_blk_333" ,GATE_IP_GSCL1 ,3 ,0 ,0 ), -GATE (CLK_SMMU_FIMCL1 ,"smmu_fimcl1" ,"aclk333_432_gscl" , +GATE (CLK_SMMU_FIMCL1 ,"smmu_fimcl1" ,"dout_gscl_blk_333" ,GATE_IP_GSCL1 ,4 ,0 ,0 ), -GATE (CLK_SMMU_GSCL0 ,"smmu_gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,6 ,0 , -0 ), -GATE (CLK_SMMU_GSCL1 ,"smmu_gscl1" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,7 ,0 , -0 ), -GATE (CLK_GSCL_WA ,"gscl_wa" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,12 ,0 ,0 ), -GATE (CLK_GSCL_WB ,"gscl_wb" ,"aclk300_gscl" ,GATE_IP_GSCL1 ,13 ,0 ,0 ), -GATE (CLK_SMMU_FIMCL3 ,"smmu_fimcl3," ,"aclk333_432_gscl" , +GATE (CLK_SMMU_GSCL0 ,"smmu_gscl0" ,"dout_gscl_blk_300" , +GATE_IP_GSCL1 ,6 ,0 ,0 ), +GATE (CLK_SMMU_GSCL1 ,"smmu_gscl1" ,"dout_gscl_blk_300" , +GATE_IP_GSCL1 ,7 ,0 ,0 ), +GATE (CLK_GSCL_WA ,"gscl_wa" ,"sclk_gscl_wa" ,GATE_IP_GSCL1 ,12 ,0 ,0 ), +GATE (CLK_GSCL_WB ,"gscl_wb" ,"sclk_gscl_wb" ,GATE_IP_GSCL1 ,13 ,0 ,0 ), +GATE (CLK_SMMU_FIMCL3 ,"smmu_fimcl3," ,"dout_gscl_blk_333" ,GATE_IP_GSCL1 ,16 ,0 ,0 ), +GATE (0 ,"fimc_lite0" ,"aclk333_432_gscl" ,GATE_IP_GSCL0 ,5 ,0 ,0 ), +GATE (0 ,"fimc_lite1" ,"aclk333_432_gscl" ,GATE_IP_GSCL0 ,6 ,0 ,0 ),GATE (CLK_FIMC_LITE3 ,"fimc_lite3" ,"aclk333_432_gscl" , GATE_IP_GSCL1, 17, 0, 0),
drivers/clk/samsung/clk-exynos5420.c static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { · line 831
Quoted 4 lines
drivers/clk/samsung/clk-exynos5420.c +1
-0@@ -818,6 +828,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 , 0), +/* gating of aclk300_gscl causes system hang. It should not be gated. */
[nit] Probably.... s/aclk300_gscl/aclk400_mscl
Quoted 26 lines
drivers/clk/samsung/clk-exynos5420.c +2
-0+GATE (CLK_ACLK400_MSCL ,"aclk400_mscl" ,"mout_user_aclk400_mscl" , +GATE_BUS_TOP ,17 ,CLK_IGNORE_UNUSED ,0 ),GATE (0 ,"aclk266_isp" ,"mout_user_aclk266_isp" ,GATE_BUS_TOP ,13 ,0 ,0 ), GATE(0, "aclk400_isp", "mout_user_aclk400_isp",include/dt-bindings/clock/exynos5420.h +1
-2@@ -159,7 +159,7 @@#define CLK_GSCL_WB 464#define CLK_GSCL0 465#define CLK_GSCL1 466 -#define CLK_CLK_3AA 467 +#define CLK_FIMC_3AA 467#define CLK_ACLK266_G2D 470#define CLK_SSS 471#define CLK_SLIM_SSS 472 --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 4/16 clk: exynos5420: correct clock parents for mscl sysmmu
In reply to Shaik Ameer BashaSigned-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +9 -6
@@ -579,6 +579,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV2_RATIO0, 4, 2),DIV (0 ,"dout_gscl_blk_333" ,"aclk333_432_gscl" ,DIV2_RATIO0 ,6 ,2 ), +/* MSCL Blk */ +DIV (0 ,"dout_mscl_blk" ,"aclk400_mscl" ,DIV2_RATIO0 ,28 ,2 ), +/* ISP Block */ DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
@@ -820,12 +823,12 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_MSCL0 ,"mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,0 ,0 ,0 ),GATE (CLK_MSCL1 ,"mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,1 ,0 ,0 ),GATE (CLK_MSCL2 ,"mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,2 ,0 ,0 ), -GATE (CLK_SMMU_MSCL0 ,"smmu_mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,8 ,0 , -0 ), -GATE (CLK_SMMU_MSCL1 ,"smmu_mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,9 ,0 , -0 ), -GATE (CLK_SMMU_MSCL2 ,"smmu_mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,10 ,0 , -0 ), +GATE (CLK_SMMU_MSCL0 ,"smmu_mscl0" ,"dout_mscl_blk" , +GATE_IP_MSCL ,8 ,0 ,0 ), +GATE (CLK_SMMU_MSCL1 ,"smmu_mscl1" ,"dout_mscl_blk" , +GATE_IP_MSCL ,9 ,0 ,0 ), +GATE (CLK_SMMU_MSCL2 ,"smmu_mscl2" ,"dout_mscl_blk" , +GATE_IP_MSCL ,10 ,0 ,0 ),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 , 0),/* gating of aclk300_gscl causes system hang. It should not be gated. */
Signature · 1 line
1.7.9.5
PATCH v3 4/16 clk: exynos5420: correct clock parents for mscl sysmmu
Hi Shaik,
Quoted 3 lines · Shaik Ameer Basha
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>---
Reviewed-by Alim Akhtar <[email protected]>
Quoted 44 lines
drivers/clk/samsung/clk-exynos5420.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-)drivers/clk/samsung/clk-exynos5420.c +9
-7@@ -579,6 +579,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV2_RATIO0, 4, 2),DIV (0 ,"dout_gscl_blk_333" ,"aclk333_432_gscl" ,DIV2_RATIO0 ,6 ,2 ), +/* MSCL Blk */ +DIV (0 ,"dout_mscl_blk" ,"aclk400_mscl" ,DIV2_RATIO0 ,28 ,2 ), +/* ISP Block */ DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",@@ -820,12 +823,12 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_MSCL0 ,"mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,0 ,0 ,0 ),GATE (CLK_MSCL1 ,"mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,1 ,0 ,0 ),GATE (CLK_MSCL2 ,"mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,2 ,0 ,0 ), -GATE (CLK_SMMU_MSCL0 ,"smmu_mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,8 ,0 , -0 ), -GATE (CLK_SMMU_MSCL1 ,"smmu_mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,9 ,0 , -0 ), -GATE (CLK_SMMU_MSCL2 ,"smmu_mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,10 ,0 , -0 ), +GATE (CLK_SMMU_MSCL0 ,"smmu_mscl0" ,"dout_mscl_blk" , +GATE_IP_MSCL ,8 ,0 ,0 ), +GATE (CLK_SMMU_MSCL1 ,"smmu_mscl1" ,"dout_mscl_blk" , +GATE_IP_MSCL ,9 ,0 ,0 ), +GATE (CLK_SMMU_MSCL2 ,"smmu_mscl2" ,"dout_mscl_blk" , +GATE_IP_MSCL ,10 ,0 ,0 ),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), /* gating of aclk300_gscl causes system hang. It should not be gated. */ --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 5/16 clk: exynos5420: update clocks for G2D block
In reply to Shaik Ameer BashaAddign more G2D block clocks.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 10 ++++++++++ include/dt-bindings/clock/exynos5420.h | 3 +++ 2 files changed, 13 insertions(+) mode change 100644 => 100755 include/dt-bindings/clock/exynos5420.h
drivers/clk/samsung/clk-exynos5420.c +10 -0
@@ -815,6 +815,10 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_ROTATOR ,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ),GATE (CLK_JPEG ,"jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,2 ,0 ,0 ),GATE (CLK_JPEG2 ,"jpeg2" ,"aclk300_jpeg" ,GATE_IP_GEN ,3 ,0 ,0 ), +GATE (CLK_MDMA0 ,"mdma0" ,"aclk266_g2d" , +GATE_IP_G2D ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_SMMU_MDMA0 ,"smmu_mdma0" ,"aclk266_g2d" , +GATE_IP_G2D ,5 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_MDMA1 ,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ),GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
@@ -842,6 +846,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { "mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0),GATE (0 ,"aclk333_432_isp" ,"mout_user_aclk333_432_isp" ,GATE_BUS_TOP ,8 ,0 ,0 ), +/* G2D */ +GATE (CLK_G2D ,"g2d" ,"aclk333_g2d" , +GATE_IP_G2D ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_SMMU_G2D ,"smmu_g2d" ,"aclk333_g2d" , +GATE_IP_G2D ,7 ,CLK_IGNORE_UNUSED ,0 ),/* ISP */ GATE (0 ,"sclk_pwm_isp" ,"dout_pwm_isp" ,GATE_TOP_SCLK_ISP ,3 ,0 ,0 ), GATE(0, "sclk_uart_isp", "dout_uart_isp", GATE_TOP_SCLK_ISP, 0, 0, 0),
@@ -858,6 +867,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {/* SSS */ GATE (CLK_SSS ,"sss" ,"aclk266_g2d" ,GATE_IP_G2D ,2 ,0 ,0 ), + GATE(CLK_SMMU_SSS, "smmu_sss", "aclk266_g2d", GATE_IP_G2D, 6, 0, 0), }; static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
include/dt-bindings/clock/exynos5420.h +3 -0
@@ -175,6 +175,9 @@#define CLK_ACLK_G3D 500#define CLK_G3D 501#define CLK_SMMU_MIXER 502 +#define CLK_SMMU_G2D 503 +#define CLK_SMMU_MDMA0 504 +#define CLK_SMMU_SSS 505/* mux clocks */ #define CLK_MOUT_HDMI 640
Signature · 1 line
1.7.9.5
PATCH v3 5/16 clk: exynos5420: update clocks for G2D block
Hi Shaik,
Quoted 38 lines · Shaik Ameer Basha
Addign more G2D block clocks.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 10 ++++++++++ include/dt-bindings/clock/exynos5420.h | 3 +++ 2 files changed, 13 insertions(+) mode change 100644 => 100755 include/dt-bindings/clock/exynos5420.hdrivers/clk/samsung/clk-exynos5420.c +9
-0@@ -815,6 +815,10 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_ROTATOR ,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ),GATE (CLK_JPEG ,"jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,2 ,0 ,0 ),GATE (CLK_JPEG2 ,"jpeg2" ,"aclk300_jpeg" ,GATE_IP_GEN ,3 ,0 ,0 ), +GATE (CLK_MDMA0 ,"mdma0" ,"aclk266_g2d" , +GATE_IP_G2D ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_SMMU_MDMA0 ,"smmu_mdma0" ,"aclk266_g2d" , +GATE_IP_G2D ,5 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_MDMA1 ,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ),GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),@@ -842,6 +846,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { "mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0),GATE (0 ,"aclk333_432_isp" ,"mout_user_aclk333_432_isp" ,GATE_BUS_TOP ,8 ,0 ,0 ), +/* G2D */ +GATE (CLK_G2D ,"g2d" ,"aclk333_g2d" , +GATE_IP_G2D ,3 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_SMMU_G2D ,"smmu_g2d" ,"aclk333_g2d" , +GATE_IP_G2D ,7 ,CLK_IGNORE_UNUSED ,0 ),/* ISP */ GATE (0 ,"sclk_pwm_isp" ,"dout_pwm_isp" ,GATE_TOP_SCLK_ISP ,3 ,0 ,0 ), GATE(0, "sclk_uart_isp", "dout_uart_isp", GATE_TOP_SCLK_ISP, 0, 0, 0),
drivers/clk/samsung/clk-exynos5420.c static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { · line 870
Quoted 4 lines
drivers/clk/samsung/clk-exynos5420.c +1
-0@@ -858,6 +867,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {/* SSS */ GATE (CLK_SSS ,"sss" ,"aclk266_g2d" ,GATE_IP_G2D ,2 ,0 ,0 ), + GATE(CLK_SMMU_SSS, "smmu_sss", "aclk266_g2d", GATE_IP_G2D, 6, 0, 0),
Probably couple of G2D block clocks are still missing, can you please take a look?
Quoted 27 lines
drivers/clk/samsung/clk-exynos5420.c +0
-0};static struct samsung_pll_clock exynos5420_plls[nr_plls]__initdata = {include/dt-bindings/clock/exynos5420.h +3
-1@@ -175,6 +175,9 @@#define CLK_ACLK_G3D 500#define CLK_G3D 501#define CLK_SMMU_MIXER 502 +#define CLK_SMMU_G2D 503 +#define CLK_SMMU_MDMA0 504 +#define CLK_SMMU_SSS 505/* mux clocks */ #define CLK_MOUT_HDMI 640 --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 6/16 clk: exynos5420: update clocks for DISP1 block
In reply to Shaik Ameer BashaThis patch corrects some child-parent clock relationships, and updates the clocks according to the latest datasheet.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 44 ++++++++++++++++++++++++-------- include/dt-bindings/clock/exynos5420.h | 3 ++- 2 files changed, 36 insertions(+), 11 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +34 -10
@@ -61,6 +61,7 @@#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288 +#define SRC_MASK_TOP2 0x10308#define SRC_MASK_DISP10 0x1032c#define SRC_MASK_FSYS 0x10340#define SRC_MASK_PERIC0 0x10350
@@ -100,6 +101,7 @@#define GATE_TOP_SCLK_MAU 0x1083c#define GATE_TOP_SCLK_FSYS 0x10840#define GATE_TOP_SCLK_PERIC 0x10850 +#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110#define SRC_CDREX 0x20200
@@ -146,6 +148,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SRC_TOP10 ,SRC_TOP11 ,SRC_TOP12 , +SRC_MASK_TOP2 ,SRC_MASK_DISP10 ,SRC_MASK_FSYS , SRC_MASK_PERIC0,
@@ -186,6 +189,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_TOP_SCLK_MAU ,GATE_TOP_SCLK_FSYS ,GATE_TOP_SCLK_PERIC , +TOP_SPARE2 ,SRC_CDREX ,SRC_KFC , DIV_KFC0,
@@ -252,6 +256,7 @@ PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};PNAME (mout_group4_p) = {"mout_sclk_ipll" ,"mout_sclk_dpll" ,"mout_sclk_mpll" };PNAME (mout_group5_p) = {"mout_sclk_vpll" ,"mout_sclk_dpll" }; +PNAME (mout_fimd1_final_p) = {"mout_fimd1" ,"mout_fimd1_opt" };PNAME (mout_sw_aclk66_p) = {"dout_aclk66" ,"mout_sclk_spll" };PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" };
@@ -271,7 +276,7 @@ PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};PNAME (mout_user_aclk333_432_isp_p) = {"fin_pll" ,"mout_sw_aclk333_432_isp" };PNAME (mout_sw_aclk200_p) = {"dout_aclk200" ,"mout_sclk_spll" }; -PNAME (mout_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" }; +PNAME (mout_user_aclk200_disp1_p) = {"fin_pll" ,"mout_sw_aclk200" };PNAME (mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl" ,"mout_sclk_spll" };PNAME (mout_user_aclk400_mscl_p) = {"fin_pll" ,"mout_sw_aclk400_mscl" };
@@ -293,7 +298,9 @@ PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};PNAME (mout_user_aclk300_gscl_p) = {"fin_pll" ,"mout_sw_aclk300_gscl" };PNAME (mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1" ,"mout_sclk_spll" }; +PNAME (mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1" ,"mout_sclk_spll" };PNAME (mout_user_aclk300_disp1_p) = {"fin_pll" ,"mout_sw_aclk300_disp1" }; +PNAME (mout_user_aclk400_disp1_p) = {"fin_pll" ,"mout_sw_aclk400_disp1" };PNAME (mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg" ,"mout_sclk_spll" };PNAME (mout_user_aclk300_jpeg_p) = {"fin_pll" ,"mout_sw_aclk300_jpeg" };
@@ -373,7 +380,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_user_aclk400_mscl" , mout_user_aclk400_mscl_p,SRC_TOP3 ,4 ,1 ), -MUX (0 ,"mout_aclk200_disp1" , mout_aclk200_disp1_p,SRC_TOP3 ,8 ,1 ), +MUX (0 ,"mout_user_aclk200_disp1" , mout_user_aclk200_disp1_p, +SRC_TOP3 ,8 ,1 ),MUX (0 ,"mout_user_aclk200_fsys2" , mout_user_aclk200_fsys2_p,SRC_TOP3 ,12 ,1 ), MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
@@ -443,6 +451,10 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_dp1" , mout_group2_p,SRC_DISP10 ,20 ,3 ),MUX (0 ,"mout_pixel" , mout_group2_p,SRC_DISP10 ,24 ,3 ),MUX (CLK_MOUT_HDMI ,"mout_hdmi" , mout_hdmi_p,SRC_DISP10 ,28 ,1 ), +MUX_F (0 ,"mout_fimd1_opt" , mout_group2_p, +SRC_DISP10 ,8 ,3 ,CLK_SET_RATE_PARENT ,0 ), +MUX_F (0 ,"mout_fimd1_final" , mout_fimd1_final_p, +TOP_SPARE2 ,8 ,1 ,CLK_SET_RATE_PARENT ,0 ),/* MAU Block */ MUX(0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
@@ -486,6 +498,11 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { SRC_TOP4, 4, 1),MUX (0 ,"mout_user_aclk266_isp" , mout_user_aclk266_isp_p,SRC_TOP4 ,16 ,1 ), +MUX (0 ,"mout_aclk400_disp1" , mout_group1_p,SRC_TOP2 ,4 ,2 ), +MUX (0 ,"mout_sw_aclk400_disp1" , mout_sw_aclk400_disp1_p, +SRC_TOP12 ,4 ,1 ), +MUX (0 ,"mout_user_aclk400_disp1" , mout_user_aclk400_disp1_p, +SRC_TOP5 ,0 ,1 ),/* ISP Block */ MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
@@ -519,15 +536,16 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_aclk266_g2d" ,"mout_aclk266_g2d" ,DIV_TOP2 ,12 ,3 ),DIV (0 ,"dout_aclk_g3d" ,"mout_aclk_g3d" ,DIV_TOP2 ,16 ,3 ),DIV (0 ,"dout_aclk300_jpeg" ,"mout_aclk300_jpeg" ,DIV_TOP2 ,20 ,3 ), -DIV_A (0 ,"dout_aclk300_disp1" ,"mout_aclk300_disp1" , -DIV_TOP2 ,24 ,3 ,"aclk300_disp1" ), +DIV (0 ,"dout_aclk300_disp1" ,"mout_aclk300_disp1" ,DIV_TOP2 ,24 ,3 ),DIV (0 ,"dout_aclk300_gscl" ,"mout_aclk300_gscl" ,DIV_TOP2 ,28 ,3 ),/* DISP1 Block */ -DIV (0 ,"dout_fimd1" ,"mout_fimd1" ,DIV_DISP10 ,0 ,4 ), +DIV (0 ,"dout_fimd1" ,"mout_fimd1_final" ,DIV_DISP10 ,0 ,4 ),DIV (0 ,"dout_mipi1" ,"mout_mipi1" ,DIV_DISP10 ,16 ,8 ),DIV (0 ,"dout_dp1" ,"mout_dp1" ,DIV_DISP10 ,24 ,4 ),DIV (CLK_DOUT_PIXEL ,"dout_hdmi_pixel" ,"mout_pixel" ,DIV_DISP10 ,28 ,4 ), +DIV (0 ,"dout_disp1_blk" ,"aclk200_disp1" ,DIV2_RATIO0 ,16 ,2 ), +DIV (0 ,"dout_aclk400_disp1" ,"mout_aclk400_disp1" ,DIV_TOP2 ,4 ,3 ),/* Audio Block */ DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -801,10 +819,12 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_FIMD1 ,"fimd1" ,"aclk300_disp1" ,GATE_IP_DISP1 ,0 ,0 ,0 ),GATE (CLK_DSIM1 ,"dsim1" ,"aclk200_disp1" ,GATE_IP_DISP1 ,3 ,0 ,0 ),GATE (CLK_DP1 ,"dp1" ,"aclk200_disp1" ,GATE_IP_DISP1 ,4 ,0 ,0 ), -GATE (CLK_MIXER ,"mixer" ,"aclk166" ,GATE_IP_DISP1 ,5 ,0 ,0 ), +GATE (CLK_MIXER ,"mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,5 ,0 ,0 ),GATE (CLK_HDMI ,"hdmi" ,"aclk200_disp1" ,GATE_IP_DISP1 ,6 ,0 ,0 ), -GATE (CLK_SMMU_FIMD1 ,"smmu_fimd1" ,"aclk300_disp1" ,GATE_IP_DISP1 ,8 ,0 , -0 ), +GATE (CLK_SMMU_FIMD1M0 ,"smmu_fimd1m0" ,"dout_disp1_blk" , +GATE_IP_DISP1 ,7 ,0 ,0 ), +GATE (CLK_SMMU_FIMD1M1 ,"smmu_fimd1m1" ,"dout_disp1_blk" , +GATE_IP_DISP1 ,8 ,0 ,0 ),GATE (CLK_MFC ,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ), GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
@@ -833,8 +853,12 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_IP_MSCL, 9, 0, 0),GATE (CLK_SMMU_MSCL2 ,"smmu_mscl2" ,"dout_mscl_blk" ,GATE_IP_MSCL ,10 ,0 ,0 ), -GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 , -0 ), +GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" , +GATE_IP_DISP1 ,9 ,0 ,0 ), +GATE (0 ,"aclk200_disp1" ,"mout_user_aclk200_disp1" , +GATE_BUS_TOP ,18 ,CLK_IGNORE_UNUSED ,0 ), +GATE (0 ,"aclk300_disp1" ,"mout_user_aclk300_disp1" , +SRC_MASK_TOP2 ,24 ,CLK_IGNORE_UNUSED ,0 ),/* gating of aclk300_gscl causes system hang. It should not be gated. */ GATE (CLK_ACLK400_MSCL ,"aclk400_mscl" ,"mout_user_aclk400_mscl" , GATE_BUS_TOP, 17, CLK_IGNORE_UNUSED, 0),
include/dt-bindings/clock/exynos5420.h +2 -1
@@ -140,7 +140,8 @@#define CLK_HDMI 413#define CLK_ACLK300_DISP1 420#define CLK_FIMD1 421 -#define CLK_SMMU_FIMD1 422 +#define CLK_SMMU_FIMD1M0 422 +#define CLK_SMMU_FIMD1M1 423#define CLK_ACLK166 430#define CLK_MIXER 431#define CLK_ACLK266 440
Signature · 1 line
1.7.9.5
PATCH v3 7/16 clk: exynos5420: update clocks for PERIC block
In reply to Shaik Ameer BashaThis patch includes,
1] renaming of the HSI2C clocks
2] renaming of spi clocks according to the datasheet 3] fixes for child-parent relationships
4] adding of more clocks related to PERIC block
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- arch/arm/boot/dts/exynos5420.dtsi | 14 +++--- drivers/clk/samsung/clk-exynos5420.c | 73 ++++++++++++++++---------------- include/dt-bindings/clock/exynos5420.h | 14 +++--- 3 files changed, 50 insertions(+), 51 deletions(-)
arch/arm/boot/dts/exynos5420.dtsi +7 -7
@@ -549,7 +549,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock CLK_I2C4>; + clocks = <&clock CLK_USI0>; clock-names = "hsi2c"; status = "disabled"; };
@@ -562,7 +562,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock CLK_I2C5>; + clocks = <&clock CLK_USI1>; clock-names = "hsi2c"; status = "disabled"; };
@@ -575,7 +575,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock CLK_I2C6>; + clocks = <&clock CLK_USI2>; clock-names = "hsi2c"; status = "disabled"; };
@@ -588,7 +588,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock CLK_I2C7>; + clocks = <&clock CLK_USI3>; clock-names = "hsi2c"; status = "disabled"; };
@@ -601,7 +601,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_I2C8>; + clocks = <&clock CLK_USI4>; clock-names = "hsi2c"; status = "disabled"; };
@@ -614,7 +614,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_I2C9>; + clocks = <&clock CLK_USI5>; clock-names = "hsi2c"; status = "disabled"; };
@@ -627,7 +627,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_I2C10>; + clocks = <&clock CLK_USI6>; clock-names = "hsi2c"; status = "disabled"; };
drivers/clk/samsung/clk-exynos5420.c +36 -37
118 lines not on this page · raw message
include/dt-bindings/clock/exynos5420.h +7 -7
@@ -69,10 +69,10 @@#define CLK_I2C1 262#define CLK_I2C2 263#define CLK_I2C3 264 -#define CLK_I2C4 265 -#define CLK_I2C5 266 -#define CLK_I2C6 267 -#define CLK_I2C7 268 +#define CLK_USI0 265 +#define CLK_USI1 266 +#define CLK_USI2 267 +#define CLK_USI3 268#define CLK_I2C_HDMI 269#define CLK_TSADC 270#define CLK_SPI0 271
@@ -85,9 +85,9 @@#define CLK_PCM2 278#define CLK_PWM 279#define CLK_SPDIF 280 -#define CLK_I2C8 281 -#define CLK_I2C9 282 -#define CLK_I2C10 283 +#define CLK_USI4 281 +#define CLK_USI5 282 +#define CLK_USI6 283#define CLK_ACLK66_PSGEN 300#define CLK_CHIPID 301#define CLK_SYSREG 302
Signature · 1 line
1.7.9.5
PATCH v3 7/16 clk: exynos5420: update clocks for PERIC block
HI shaik,
Quoted 5 lines · Shaik Ameer Basha
This patch includes,
1] renaming of the HSI2C clocks
2] renaming of spi clocks according to the datasheet 3] fixes for child-parent relationships
4] adding of more clocks related to PERIC block
You are also fixing the gate clock, GATE_BUS_PERIC -> GATE_IP_PERIC Please add them in your commit message.
Quoted 244 lines
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>--- arch/arm/boot/dts/exynos5420.dtsi | 14 +++--- drivers/clk/samsung/clk-exynos5420.c | 73 ++++++++++++++++---------------- include/dt-bindings/clock/exynos5420.h | 14 +++--- 3 files changed, 50 insertions(+), 51 deletions(-)arch/arm/boot/dts/exynos5420.dtsi +7
-7@@ -549,7 +549,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock CLK_I2C4>; + clocks = <&clock CLK_USI0>; clock-names = "hsi2c"; status = "disabled"; };@@ -562,7 +562,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock CLK_I2C5>; + clocks = <&clock CLK_USI1>; clock-names = "hsi2c"; status = "disabled"; };@@ -575,7 +575,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock CLK_I2C6>; + clocks = <&clock CLK_USI2>; clock-names = "hsi2c"; status = "disabled"; };@@ -588,7 +588,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock CLK_I2C7>; + clocks = <&clock CLK_USI3>; clock-names = "hsi2c"; status = "disabled"; };@@ -601,7 +601,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_I2C8>; + clocks = <&clock CLK_USI4>; clock-names = "hsi2c"; status = "disabled"; };@@ -614,7 +614,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_I2C9>; + clocks = <&clock CLK_USI5>; clock-names = "hsi2c"; status = "disabled"; };@@ -627,7 +627,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_I2C10>; + clocks = <&clock CLK_USI6>; clock-names = "hsi2c"; status = "disabled"; };drivers/clk/samsung/clk-exynos5420.c +36
-37@@ -95,6 +95,7 @@#define GATE_IP_DISP1 0x10928#define GATE_IP_G3D 0x10930#define GATE_IP_GEN 0x10934 +#define GATE_IP_PERIC 0x10950#define GATE_IP_MSCL 0x10970#define GATE_TOP_SCLK_GSCL 0x10820#define GATE_TOP_SCLK_DISP1 0x10828@@ -183,6 +184,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_IP_DISP1 ,GATE_IP_G3D ,GATE_IP_GEN , +GATE_IP_PERIC ,GATE_IP_MSCL ,GATE_TOP_SCLK_GSCL , GATE_TOP_SCLK_DISP1,@@ -588,9 +590,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_audio2" ,"mout_audio2" ,DIV_PERIC3 ,28 ,4 ),/* SPI Pre-Ratio */ -DIV (0 ,"dout_pre_spi0" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ), -DIV (0 ,"dout_pre_spi1" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ), -DIV (0 ,"dout_pre_spi2" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), +DIV (0 ,"dout_spi0_pre" ,"dout_spi0" ,DIV_PERIC4 ,8 ,8 ), +DIV (0 ,"dout_spi1_pre" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ), +DIV (0 ,"dout_spi2_pre" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ),/* GSCL Block */ DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",@@ -641,8 +643,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),GATE (0 ,"aclk66_psgen" ,"mout_aclk66_psgen" ,GATE_BUS_TOP ,10 ,CLK_IGNORE_UNUSED ,0 ), -GATE (0 ,"aclk66_peric" ,"mout_aclk66_peric" , -GATE_BUS_TOP ,11 ,0 ,0 ), +GATE (0 ,"aclk66_peric" ,"mout_user_aclk66_peric" , +GATE_BUS_TOP ,11 ,CLK_IGNORE_UNUSED ,0 ),GATE (0 ,"aclk166" ,"mout_user_aclk166" ,GATE_BUS_TOP ,14 ,CLK_IGNORE_UNUSED ,0 ), GATE(0, "aclk333", "mout_aclk333",@@ -657,11 +659,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),GATE (CLK_SCLK_UART3 ,"sclk_uart3" ,"dout_uart3" ,GATE_TOP_SCLK_PERIC ,3 ,CLK_SET_RATE_PARENT ,0 ), -GATE (CLK_SCLK_SPI0 ,"sclk_spi0" ,"dout_pre_spi0" , +GATE (CLK_SCLK_SPI0 ,"sclk_spi0" ,"dout_spi0_pre" ,GATE_TOP_SCLK_PERIC ,6 ,CLK_SET_RATE_PARENT ,0 ), -GATE (CLK_SCLK_SPI1 ,"sclk_spi1" ,"dout_pre_spi1" , +GATE (CLK_SCLK_SPI1 ,"sclk_spi1" ,"dout_spi1_pre" ,GATE_TOP_SCLK_PERIC ,7 ,CLK_SET_RATE_PARENT ,0 ), -GATE (CLK_SCLK_SPI2 ,"sclk_spi2" ,"dout_pre_spi2" , +GATE (CLK_SCLK_SPI2 ,"sclk_spi2" ,"dout_spi2_pre" ,GATE_TOP_SCLK_PERIC ,8 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_SPDIF ,"sclk_spdif" ,"mout_spdif" , GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),@@ -732,42 +734,39 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_USBD301 ,"usbd301" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,28 ,0 ,0 ),/* UART */ -GATE (CLK_UART0 ,"uart0" ,"aclk66_peric" ,GATE_BUS_PERIC ,4 ,0 ,0 ), -GATE (CLK_UART1 ,"uart1" ,"aclk66_peric" ,GATE_BUS_PERIC ,5 ,0 ,0 ), -GATE_A (CLK_UART2 ,"uart2" ,"aclk66_peric" , -GATE_BUS_PERIC ,6 ,CLK_IGNORE_UNUSED ,0 ,"uart2" ), -GATE (CLK_UART3 ,"uart3" ,"aclk66_peric" ,GATE_BUS_PERIC ,7 ,0 ,0 ), +GATE (CLK_UART0 ,"uart0" ,"aclk66_peric" ,GATE_IP_PERIC ,0 ,0 ,0 ), +GATE (CLK_UART1 ,"uart1" ,"aclk66_peric" ,GATE_IP_PERIC ,1 ,0 ,0 ), +GATE (CLK_UART2 ,"uart2" ,"aclk66_peric" ,GATE_IP_PERIC ,2 ,0 ,0 ), +GATE (CLK_UART3 ,"uart3" ,"aclk66_peric" ,GATE_IP_PERIC ,3 ,0 ,0 ),/* I2C */ -GATE (CLK_I2C0 ,"i2c0" ,"aclk66_peric" ,GATE_BUS_PERIC ,9 ,0 ,0 ), -GATE (CLK_I2C1 ,"i2c1" ,"aclk66_peric" ,GATE_BUS_PERIC ,10 ,0 ,0 ), -GATE (CLK_I2C2 ,"i2c2" ,"aclk66_peric" ,GATE_BUS_PERIC ,11 ,0 ,0 ), -GATE (CLK_I2C3 ,"i2c3" ,"aclk66_peric" ,GATE_BUS_PERIC ,12 ,0 ,0 ), -GATE (CLK_I2C4 ,"i2c4" ,"aclk66_peric" ,GATE_BUS_PERIC ,13 ,0 ,0 ), -GATE (CLK_I2C5 ,"i2c5" ,"aclk66_peric" ,GATE_BUS_PERIC ,14 ,0 ,0 ), -GATE (CLK_I2C6 ,"i2c6" ,"aclk66_peric" ,GATE_BUS_PERIC ,15 ,0 ,0 ), -GATE (CLK_I2C7 ,"i2c7" ,"aclk66_peric" ,GATE_BUS_PERIC ,16 ,0 ,0 ), -GATE (CLK_I2C_HDMI ,"i2c_hdmi" ,"aclk66_peric" ,GATE_BUS_PERIC ,17 ,0 , -0 ), -GATE (CLK_TSADC ,"tsadc" ,"aclk66_peric" ,GATE_BUS_PERIC ,18 ,0 ,0 ), +GATE (CLK_I2C0 ,"i2c0" ,"aclk66_peric" ,GATE_IP_PERIC ,6 ,0 ,0 ), +GATE (CLK_I2C1 ,"i2c1" ,"aclk66_peric" ,GATE_IP_PERIC ,7 ,0 ,0 ), +GATE (CLK_I2C2 ,"i2c2" ,"aclk66_peric" ,GATE_IP_PERIC ,8 ,0 ,0 ), +GATE (CLK_I2C3 ,"i2c3" ,"aclk66_peric" ,GATE_IP_PERIC ,9 ,0 ,0 ), +GATE (CLK_USI0 ,"usi0" ,"aclk66_peric" ,GATE_IP_PERIC ,10 ,0 ,0 ), +GATE (CLK_USI1 ,"usi1" ,"aclk66_peric" ,GATE_IP_PERIC ,11 ,0 ,0 ), +GATE (CLK_USI2 ,"usi2" ,"aclk66_peric" ,GATE_IP_PERIC ,12 ,0 ,0 ), +GATE (CLK_USI3 ,"usi3" ,"aclk66_peric" ,GATE_IP_PERIC ,13 ,0 ,0 ), +GATE (CLK_USI4 ,"usi4" ,"aclk66_peric" ,GATE_IP_PERIC ,28 ,0 ,0 ), +GATE (CLK_USI5 ,"usi5" ,"aclk66_peric" ,GATE_IP_PERIC ,30 ,0 ,0 ), +GATE (CLK_USI6 ,"usi6" ,"aclk66_peric" ,GATE_IP_PERIC ,31 ,0 ,0 ), +GATE (CLK_I2C_HDMI ,"i2c_hdmi" ,"aclk66_peric" ,GATE_IP_PERIC ,14 ,0 ,0 ), +GATE (CLK_TSADC ,"tsadc" ,"aclk66_peric" ,GATE_IP_PERIC ,15 ,0 ,0 ),/* SPI */ -GATE (CLK_SPI0 ,"spi0" ,"aclk66_peric" ,GATE_BUS_PERIC ,19 ,0 ,0 ), -GATE (CLK_SPI1 ,"spi1" ,"aclk66_peric" ,GATE_BUS_PERIC ,20 ,0 ,0 ), -GATE (CLK_SPI2 ,"spi2" ,"aclk66_peric" ,GATE_BUS_PERIC ,21 ,0 ,0 ), +GATE (CLK_SPI0 ,"spi0" ,"aclk66_peric" ,GATE_IP_PERIC ,16 ,0 ,0 ), +GATE (CLK_SPI1 ,"spi1" ,"aclk66_peric" ,GATE_IP_PERIC ,17 ,0 ,0 ), +GATE (CLK_SPI2 ,"spi2" ,"aclk66_peric" ,GATE_IP_PERIC ,18 ,0 ,0 ),GATE (CLK_KEYIF ,"keyif" ,"aclk66_peric" ,GATE_BUS_PERIC ,22 ,0 ,0 ),/* I2S */ -GATE (CLK_I2S1 ,"i2s1" ,"aclk66_peric" ,GATE_BUS_PERIC ,23 ,0 ,0 ), -GATE (CLK_I2S2 ,"i2s2" ,"aclk66_peric" ,GATE_BUS_PERIC ,24 ,0 ,0 ), +GATE (CLK_I2S1 ,"i2s1" ,"aclk66_peric" ,GATE_IP_PERIC ,20 ,0 ,0 ), +GATE (CLK_I2S2 ,"i2s2" ,"aclk66_peric" ,GATE_IP_PERIC ,21 ,0 ,0 ),/* PCM */ -GATE (CLK_PCM1 ,"pcm1" ,"aclk66_peric" ,GATE_BUS_PERIC ,25 ,0 ,0 ), -GATE (CLK_PCM2 ,"pcm2" ,"aclk66_peric" ,GATE_BUS_PERIC ,26 ,0 ,0 ), +GATE (CLK_PCM1 ,"pcm1" ,"aclk66_peric" ,GATE_IP_PERIC ,22 ,0 ,0 ), +GATE (CLK_PCM2 ,"pcm2" ,"aclk66_peric" ,GATE_IP_PERIC ,23 ,0 ,0 ),/* PWM */ -GATE (CLK_PWM ,"pwm" ,"aclk66_peric" ,GATE_BUS_PERIC ,27 ,0 ,0 ), +GATE (CLK_PWM ,"pwm" ,"aclk66_peric" ,GATE_IP_PERIC ,24 ,0 ,0 ),/* SPDIF */ -GATE (CLK_SPDIF ,"spdif" ,"aclk66_peric" ,GATE_BUS_PERIC ,29 ,0 ,0 ), - -GATE (CLK_I2C8 ,"i2c8" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,0 ,0 ,0 ), -GATE (CLK_I2C9 ,"i2c9" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,1 ,0 ,0 ), -GATE (CLK_I2C10 ,"i2c10" ,"aclk66_peric" ,GATE_BUS_PERIC1 ,2 ,0 ,0 ), +GATE (CLK_SPDIF ,"spdif" ,"aclk66_peric" ,GATE_IP_PERIC ,26 ,0 ,0 ),GATE (CLK_CHIPID ,"chipid" ,"aclk66_psgen" , GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),include/dt-bindings/clock/exynos5420.h +7
-8@@ -69,10 +69,10 @@#define CLK_I2C1 262#define CLK_I2C2 263#define CLK_I2C3 264 -#define CLK_I2C4 265 -#define CLK_I2C5 266 -#define CLK_I2C6 267 -#define CLK_I2C7 268 +#define CLK_USI0 265 +#define CLK_USI1 266 +#define CLK_USI2 267 +#define CLK_USI3 268#define CLK_I2C_HDMI 269#define CLK_TSADC 270#define CLK_SPI0 271@@ -85,9 +85,9 @@#define CLK_PCM2 278#define CLK_PWM 279#define CLK_SPDIF 280 -#define CLK_I2C8 281 -#define CLK_I2C9 282 -#define CLK_I2C10 283 +#define CLK_USI4 281 +#define CLK_USI5 282 +#define CLK_USI6 283#define CLK_ACLK66_PSGEN 300#define CLK_CHIPID 301#define CLK_SYSREG 302 --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 8/16 clk: exynos5420: update clocks for PERIS and GEN blocks
In reply to Shaik Ameer BashaThis patch fixes some parent-child relationships according to the latest datasheet and adds more clocks related to PERIS and GEN blocks.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 70 ++++++++++++++++++++------------ include/dt-bindings/clock/exynos5420.h | 5 +++ 2 files changed, 48 insertions(+), 27 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +43 -27
@@ -83,6 +83,7 @@#define SCLK_DIV_ISP1 0x10584#define DIV2_RATIO0 0x10590#define GATE_BUS_TOP 0x10700 +#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754
@@ -96,6 +97,7 @@#define GATE_IP_G3D 0x10930#define GATE_IP_GEN 0x10934#define GATE_IP_PERIC 0x10950 +#define GATE_IP_PERIS 0x10960#define GATE_IP_MSCL 0x10970#define GATE_TOP_SCLK_GSCL 0x10820#define GATE_TOP_SCLK_DISP1 0x10828
@@ -172,6 +174,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SCLK_DIV_ISP1 ,DIV2_RATIO0 ,GATE_BUS_TOP , +GATE_BUS_GEN ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC , GATE_BUS_PERIC1,
@@ -185,6 +188,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_IP_G3D ,GATE_IP_GEN ,GATE_IP_PERIC , +GATE_IP_PERIS ,GATE_IP_MSCL ,GATE_TOP_SCLK_GSCL , GATE_TOP_SCLK_DISP1,
@@ -602,6 +606,10 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {/* MSCL Blk */ DIV (0 ,"dout_mscl_blk" ,"aclk400_mscl" ,DIV2_RATIO0 ,28 ,2 ), +/* PSGEN */ +DIV (0 ,"dout_gen_blk" ,"mout_user_aclk266" ,DIV2_RATIO0 ,8 ,1 ), +DIV (0 ,"dout_jpg_blk" ,"aclk166" ,DIV2_RATIO0 ,20 ,1 ), +/* ISP Block */ DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
@@ -620,9 +628,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { };static struct samsung_gate_clock exynos5420_gate_clks[]__initdata = { -/* TODO: Re-verify the CG bits for all the gate clocks */ -GATE_A (CLK_MCT ,"pclk_st" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,2 ,0 ,0 , -"mct" ), +GATE (CLK_MCT ,"mct" ,"aclk66_psgen" ,GATE_IP_PERIS ,18 ,0 ,0 ),GATE (0 ,"aclk200_fsys" ,"mout_user_aclk200_fsys" ,GATE_BUS_FSYS0 ,9 ,CLK_IGNORE_UNUSED ,0 ),
@@ -769,27 +775,30 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_SPDIF ,"spdif" ,"aclk66_peric" ,GATE_IP_PERIC ,26 ,0 ,0 ),GATE (CLK_CHIPID ,"chipid" ,"aclk66_psgen" , -GATE_BUS_PERIS0 ,12 ,CLK_IGNORE_UNUSED ,0 ), +GATE_IP_PERIS ,0 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SYSREG ,"sysreg" ,"aclk66_psgen" , -GATE_BUS_PERIS0 ,13 ,CLK_IGNORE_UNUSED ,0 ), -GATE (CLK_TZPC0 ,"tzpc0" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,18 ,0 ,0 ), -GATE (CLK_TZPC1 ,"tzpc1" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,19 ,0 ,0 ), -GATE (CLK_TZPC2 ,"tzpc2" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,20 ,0 ,0 ), -GATE (CLK_TZPC3 ,"tzpc3" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,21 ,0 ,0 ), -GATE (CLK_TZPC4 ,"tzpc4" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,22 ,0 ,0 ), -GATE (CLK_TZPC5 ,"tzpc5" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,23 ,0 ,0 ), -GATE (CLK_TZPC6 ,"tzpc6" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,24 ,0 ,0 ), -GATE (CLK_TZPC7 ,"tzpc7" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,25 ,0 ,0 ), -GATE (CLK_TZPC8 ,"tzpc8" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,26 ,0 ,0 ), -GATE (CLK_TZPC9 ,"tzpc9" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,27 ,0 ,0 ), - -GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,0 ,0 , -0 ), +GATE_IP_PERIS ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_TZPC0 ,"tzpc0" ,"aclk66_psgen" ,GATE_IP_PERIS ,6 ,0 ,0 ), +GATE (CLK_TZPC1 ,"tzpc1" ,"aclk66_psgen" ,GATE_IP_PERIS ,7 ,0 ,0 ), +GATE (CLK_TZPC2 ,"tzpc2" ,"aclk66_psgen" ,GATE_IP_PERIS ,8 ,0 ,0 ), +GATE (CLK_TZPC3 ,"tzpc3" ,"aclk66_psgen" ,GATE_IP_PERIS ,9 ,0 ,0 ), +GATE (CLK_TZPC4 ,"tzpc4" ,"aclk66_psgen" ,GATE_IP_PERIS ,10 ,0 ,0 ), +GATE (CLK_TZPC5 ,"tzpc5" ,"aclk66_psgen" ,GATE_IP_PERIS ,11 ,0 ,0 ), +GATE (CLK_TZPC6 ,"tzpc6" ,"aclk66_psgen" ,GATE_IP_PERIS ,12 ,0 ,0 ), +GATE (CLK_TZPC7 ,"tzpc7" ,"aclk66_psgen" ,GATE_IP_PERIS ,13 ,0 ,0 ), +GATE (CLK_TZPC8 ,"tzpc8" ,"aclk66_psgen" ,GATE_IP_PERIS ,14 ,0 ,0 ), +GATE (CLK_TZPC9 ,"tzpc9" ,"aclk66_psgen" ,GATE_IP_PERIS ,15 ,0 ,0 ), + +/* GATE_IP_PERIS doesn't list TZPC10,11 */ +GATE (CLK_TZPC10 ,"tzpc10" ,"aclk66_psgen" ,GATE_BUS_GEN ,30 ,0 ,0 ), +GATE (CLK_TZPC11 ,"tzpc11" ,"aclk66_psgen" ,GATE_BUS_GEN ,31 ,0 ,0 ), + +GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk66_psgen" ,GATE_IP_PERIS ,16 ,0 ,0 ),GATE (CLK_SECKEY ,"seckey" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,1 ,0 ,0 ), -GATE (CLK_WDT ,"wdt" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,3 ,0 ,0 ), -GATE (CLK_RTC ,"rtc" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,4 ,0 ,0 ), -GATE (CLK_TMU ,"tmu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,5 ,0 ,0 ), -GATE (CLK_TMU_GPU ,"tmu_gpu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,6 ,0 ,0 ), +GATE (CLK_WDT ,"wdt" ,"aclk66_psgen" ,GATE_IP_PERIS ,19 ,0 ,0 ), +GATE (CLK_RTC ,"rtc" ,"aclk66_psgen" ,GATE_IP_PERIS ,20 ,0 ,0 ), +GATE (CLK_TMU ,"tmu" ,"aclk66_psgen" ,GATE_IP_PERIS ,21 ,0 ,0 ), +GATE (CLK_TMU_GPU ,"tmu_gpu" ,"aclk66_psgen" ,GATE_IP_PERIS ,22 ,0 ,0 ),GATE (CLK_GSCL0 ,"gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,0 ,0 ,0 ), GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
@@ -831,17 +840,21 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_G3D ,"g3d" ,"aclkg3d" ,GATE_IP_G3D ,9 ,0 ,0 ), -GATE (CLK_ROTATOR ,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ), +GATE (CLK_ROTATOR ,"rotator" ,"mout_user_aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ),GATE (CLK_JPEG ,"jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,2 ,0 ,0 ),GATE (CLK_JPEG2 ,"jpeg2" ,"aclk300_jpeg" ,GATE_IP_GEN ,3 ,0 ,0 ), +GATE (CLK_MDMA1 ,"mdma1" ,"mout_user_aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), +GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"dout_gen_blk" , +GATE_IP_GEN ,6 ,0 ,0 ), +GATE (CLK_SMMU_JPEG ,"smmu_jpeg" ,"dout_jpg_blk" ,GATE_IP_GEN ,7 ,0 ,0 ), +GATE (CLK_SMMU_JPEG2 ,"smmu_jpeg2" ,"dout_jpg_blk" , +GATE_BUS_GEN ,28 ,0 ,0 ), +GATE (CLK_SMMU_MDMA1 ,"smmu_mdma1" ,"dout_gen_blk" , +GATE_IP_GEN ,9 ,0 ,0 ),GATE (CLK_MDMA0 ,"mdma0" ,"aclk266_g2d" ,GATE_IP_G2D ,1 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SMMU_MDMA0 ,"smmu_mdma0" ,"aclk266_g2d" ,GATE_IP_G2D ,5 ,CLK_IGNORE_UNUSED ,0 ), -GATE (CLK_MDMA1 ,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), -GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), -GATE (CLK_SMMU_JPEG ,"smmu_jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,7 ,0 ,0 ), -GATE (CLK_SMMU_MDMA1 ,"smmu_mdma1" ,"aclk266" ,GATE_IP_GEN ,9 ,0 ,0 ),GATE (CLK_MSCL0 ,"mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,0 ,0 ,0 ), GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
@@ -869,6 +882,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { "mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0),GATE (0 ,"aclk333_432_isp" ,"mout_user_aclk333_432_isp" ,GATE_BUS_TOP ,8 ,0 ,0 ), +GATE (CLK_MC ,"mc" ,"aclk66_psgen" ,GATE_BUS_GEN ,12 ,0 ,0 ), +GATE (CLK_TOP_RTC ,"top_rtc" ,"aclk66_psgen" ,GATE_IP_GEN ,5 ,0 ,0 ), +/* G2D */ GATE (CLK_G2D ,"g2d" ,"aclk333_g2d" , GATE_IP_G2D, 3, CLK_IGNORE_UNUSED, 0),
include/dt-bindings/clock/exynos5420.h +5 -0
@@ -153,6 +153,7 @@#define CLK_JPEG 451#define CLK_JPEG2 452#define CLK_SMMU_JPEG 453 +#define CLK_SMMU_JPEG2 454#define CLK_ACLK300_GSCL 460#define CLK_SMMU_GSCL0 461#define CLK_SMMU_GSCL1 462
@@ -179,6 +180,10 @@#define CLK_SMMU_G2D 503#define CLK_SMMU_MDMA0 504#define CLK_SMMU_SSS 505 +#define CLK_TZPC10 506 +#define CLK_TZPC11 507 +#define CLK_MC 508 +#define CLK_TOP_RTC 509/* mux clocks */ #define CLK_MOUT_HDMI 640
Signature · 1 line
1.7.9.5
PATCH v3 8/16 clk: exynos5420: update clocks for PERIS and GEN blocks
Hi Shaik,
Quoted 7 lines · Shaik Ameer Basha
This patch fixes some parent-child relationships according to the latest datasheet and adds more clocks related to PERIS and GEN blocks.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>---
Looks Good.
Reviewed-by Alim Akhtar <[email protected]>
Quoted 180 lines
drivers/clk/samsung/clk-exynos5420.c | 70 ++++++++++++++++++++------------ include/dt-bindings/clock/exynos5420.h | 5 +++ 2 files changed, 48 insertions(+), 27 deletions(-)drivers/clk/samsung/clk-exynos5420.c +43
-27@@ -83,6 +83,7 @@#define SCLK_DIV_ISP1 0x10584#define DIV2_RATIO0 0x10590#define GATE_BUS_TOP 0x10700 +#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754@@ -96,6 +97,7 @@#define GATE_IP_G3D 0x10930#define GATE_IP_GEN 0x10934#define GATE_IP_PERIC 0x10950 +#define GATE_IP_PERIS 0x10960#define GATE_IP_MSCL 0x10970#define GATE_TOP_SCLK_GSCL 0x10820#define GATE_TOP_SCLK_DISP1 0x10828@@ -172,6 +174,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SCLK_DIV_ISP1 ,DIV2_RATIO0 ,GATE_BUS_TOP , +GATE_BUS_GEN ,GATE_BUS_FSYS0 ,GATE_BUS_PERIC , GATE_BUS_PERIC1,@@ -185,6 +188,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_IP_G3D ,GATE_IP_GEN ,GATE_IP_PERIC , +GATE_IP_PERIS ,GATE_IP_MSCL ,GATE_TOP_SCLK_GSCL , GATE_TOP_SCLK_DISP1,@@ -602,6 +606,10 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {/* MSCL Blk */ DIV (0 ,"dout_mscl_blk" ,"aclk400_mscl" ,DIV2_RATIO0 ,28 ,2 ), +/* PSGEN */ +DIV (0 ,"dout_gen_blk" ,"mout_user_aclk266" ,DIV2_RATIO0 ,8 ,1 ), +DIV (0 ,"dout_jpg_blk" ,"aclk166" ,DIV2_RATIO0 ,20 ,1 ), +/* ISP Block */ DIV (0 ,"dout_aclk400_isp" ,"mout_aclk400_isp" ,DIV_TOP0 ,0 ,3 ), DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",@@ -620,9 +628,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { };static struct samsung_gate_clock exynos5420_gate_clks[]__initdata = { -/* TODO: Re-verify the CG bits for all the gate clocks */ -GATE_A (CLK_MCT ,"pclk_st" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,2 ,0 ,0 , -"mct" ), +GATE (CLK_MCT ,"mct" ,"aclk66_psgen" ,GATE_IP_PERIS ,18 ,0 ,0 ),GATE (0 ,"aclk200_fsys" ,"mout_user_aclk200_fsys" ,GATE_BUS_FSYS0 ,9 ,CLK_IGNORE_UNUSED ,0 ),@@ -769,27 +775,30 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_SPDIF ,"spdif" ,"aclk66_peric" ,GATE_IP_PERIC ,26 ,0 ,0 ),GATE (CLK_CHIPID ,"chipid" ,"aclk66_psgen" , -GATE_BUS_PERIS0 ,12 ,CLK_IGNORE_UNUSED ,0 ), +GATE_IP_PERIS ,0 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SYSREG ,"sysreg" ,"aclk66_psgen" , -GATE_BUS_PERIS0 ,13 ,CLK_IGNORE_UNUSED ,0 ), -GATE (CLK_TZPC0 ,"tzpc0" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,18 ,0 ,0 ), -GATE (CLK_TZPC1 ,"tzpc1" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,19 ,0 ,0 ), -GATE (CLK_TZPC2 ,"tzpc2" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,20 ,0 ,0 ), -GATE (CLK_TZPC3 ,"tzpc3" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,21 ,0 ,0 ), -GATE (CLK_TZPC4 ,"tzpc4" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,22 ,0 ,0 ), -GATE (CLK_TZPC5 ,"tzpc5" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,23 ,0 ,0 ), -GATE (CLK_TZPC6 ,"tzpc6" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,24 ,0 ,0 ), -GATE (CLK_TZPC7 ,"tzpc7" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,25 ,0 ,0 ), -GATE (CLK_TZPC8 ,"tzpc8" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,26 ,0 ,0 ), -GATE (CLK_TZPC9 ,"tzpc9" ,"aclk66_psgen" ,GATE_BUS_PERIS0 ,27 ,0 ,0 ), - -GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,0 ,0 , -0 ), +GATE_IP_PERIS ,1 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_TZPC0 ,"tzpc0" ,"aclk66_psgen" ,GATE_IP_PERIS ,6 ,0 ,0 ), +GATE (CLK_TZPC1 ,"tzpc1" ,"aclk66_psgen" ,GATE_IP_PERIS ,7 ,0 ,0 ), +GATE (CLK_TZPC2 ,"tzpc2" ,"aclk66_psgen" ,GATE_IP_PERIS ,8 ,0 ,0 ), +GATE (CLK_TZPC3 ,"tzpc3" ,"aclk66_psgen" ,GATE_IP_PERIS ,9 ,0 ,0 ), +GATE (CLK_TZPC4 ,"tzpc4" ,"aclk66_psgen" ,GATE_IP_PERIS ,10 ,0 ,0 ), +GATE (CLK_TZPC5 ,"tzpc5" ,"aclk66_psgen" ,GATE_IP_PERIS ,11 ,0 ,0 ), +GATE (CLK_TZPC6 ,"tzpc6" ,"aclk66_psgen" ,GATE_IP_PERIS ,12 ,0 ,0 ), +GATE (CLK_TZPC7 ,"tzpc7" ,"aclk66_psgen" ,GATE_IP_PERIS ,13 ,0 ,0 ), +GATE (CLK_TZPC8 ,"tzpc8" ,"aclk66_psgen" ,GATE_IP_PERIS ,14 ,0 ,0 ), +GATE (CLK_TZPC9 ,"tzpc9" ,"aclk66_psgen" ,GATE_IP_PERIS ,15 ,0 ,0 ), + +/* GATE_IP_PERIS doesn't list TZPC10,11 */ +GATE (CLK_TZPC10 ,"tzpc10" ,"aclk66_psgen" ,GATE_BUS_GEN ,30 ,0 ,0 ), +GATE (CLK_TZPC11 ,"tzpc11" ,"aclk66_psgen" ,GATE_BUS_GEN ,31 ,0 ,0 ), + +GATE (CLK_HDMI_CEC ,"hdmi_cec" ,"aclk66_psgen" ,GATE_IP_PERIS ,16 ,0 ,0 ),GATE (CLK_SECKEY ,"seckey" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,1 ,0 ,0 ), -GATE (CLK_WDT ,"wdt" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,3 ,0 ,0 ), -GATE (CLK_RTC ,"rtc" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,4 ,0 ,0 ), -GATE (CLK_TMU ,"tmu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,5 ,0 ,0 ), -GATE (CLK_TMU_GPU ,"tmu_gpu" ,"aclk66_psgen" ,GATE_BUS_PERIS1 ,6 ,0 ,0 ), +GATE (CLK_WDT ,"wdt" ,"aclk66_psgen" ,GATE_IP_PERIS ,19 ,0 ,0 ), +GATE (CLK_RTC ,"rtc" ,"aclk66_psgen" ,GATE_IP_PERIS ,20 ,0 ,0 ), +GATE (CLK_TMU ,"tmu" ,"aclk66_psgen" ,GATE_IP_PERIS ,21 ,0 ,0 ), +GATE (CLK_TMU_GPU ,"tmu_gpu" ,"aclk66_psgen" ,GATE_IP_PERIS ,22 ,0 ,0 ),GATE (CLK_GSCL0 ,"gscl0" ,"aclk300_gscl" ,GATE_IP_GSCL0 ,0 ,0 ,0 ), GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),@@ -831,17 +840,21 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_G3D ,"g3d" ,"aclkg3d" ,GATE_IP_G3D ,9 ,0 ,0 ), -GATE (CLK_ROTATOR ,"rotator" ,"aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ), +GATE (CLK_ROTATOR ,"rotator" ,"mout_user_aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ),GATE (CLK_JPEG ,"jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,2 ,0 ,0 ),GATE (CLK_JPEG2 ,"jpeg2" ,"aclk300_jpeg" ,GATE_IP_GEN ,3 ,0 ,0 ), +GATE (CLK_MDMA1 ,"mdma1" ,"mout_user_aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), +GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"dout_gen_blk" , +GATE_IP_GEN ,6 ,0 ,0 ), +GATE (CLK_SMMU_JPEG ,"smmu_jpeg" ,"dout_jpg_blk" ,GATE_IP_GEN ,7 ,0 ,0 ), +GATE (CLK_SMMU_JPEG2 ,"smmu_jpeg2" ,"dout_jpg_blk" , +GATE_BUS_GEN ,28 ,0 ,0 ), +GATE (CLK_SMMU_MDMA1 ,"smmu_mdma1" ,"dout_gen_blk" , +GATE_IP_GEN ,9 ,0 ,0 ),GATE (CLK_MDMA0 ,"mdma0" ,"aclk266_g2d" ,GATE_IP_G2D ,1 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SMMU_MDMA0 ,"smmu_mdma0" ,"aclk266_g2d" ,GATE_IP_G2D ,5 ,CLK_IGNORE_UNUSED ,0 ), -GATE (CLK_MDMA1 ,"mdma1" ,"aclk266" ,GATE_IP_GEN ,4 ,0 ,0 ), -GATE (CLK_SMMU_ROTATOR ,"smmu_rotator" ,"aclk266" ,GATE_IP_GEN ,6 ,0 ,0 ), -GATE (CLK_SMMU_JPEG ,"smmu_jpeg" ,"aclk300_jpeg" ,GATE_IP_GEN ,7 ,0 ,0 ), -GATE (CLK_SMMU_MDMA1 ,"smmu_mdma1" ,"aclk266" ,GATE_IP_GEN ,9 ,0 ,0 ),GATE (CLK_MSCL0 ,"mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,0 ,0 ,0 ), GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),@@ -869,6 +882,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { "mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0),GATE (0 ,"aclk333_432_isp" ,"mout_user_aclk333_432_isp" ,GATE_BUS_TOP ,8 ,0 ,0 ), +GATE (CLK_MC ,"mc" ,"aclk66_psgen" ,GATE_BUS_GEN ,12 ,0 ,0 ), +GATE (CLK_TOP_RTC ,"top_rtc" ,"aclk66_psgen" ,GATE_IP_GEN ,5 ,0 ,0 ), +/* G2D */ GATE (CLK_G2D ,"g2d" ,"aclk333_g2d" , GATE_IP_G2D, 3, CLK_IGNORE_UNUSED, 0),include/dt-bindings/clock/exynos5420.h +5
-1@@ -153,6 +153,7 @@#define CLK_JPEG 451#define CLK_JPEG2 452#define CLK_SMMU_JPEG 453 +#define CLK_SMMU_JPEG2 454#define CLK_ACLK300_GSCL 460#define CLK_SMMU_GSCL0 461#define CLK_SMMU_GSCL1 462@@ -179,6 +180,10 @@#define CLK_SMMU_G2D 503#define CLK_SMMU_MDMA0 504#define CLK_SMMU_SSS 505 +#define CLK_TZPC10 506 +#define CLK_TZPC11 507 +#define CLK_MC 508 +#define CLK_TOP_RTC 509/* mux clocks */ #define CLK_MOUT_HDMI 640 --1.7.9.5
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PATCH v3 8/16 clk: exynos5420: update clocks for PERIS and GEN blocks
In reply to Shaik Ameer BashaHi Shaik,
Quoted 3 lines · Shaik Ameer Basha
This patch fixes some parent-child relationships according to the latest datasheet and adds more clocks related to PERIS and GEN blocks.
Again, it is better to split up the fixes from other stuff so that it can go in the -rc
and can be back ported to stable if needed.
Signature · 2 lines
With warm regards, Sachin
PATCH v3 9/16 clk: exynos5420: update clocks for WCORE block
In reply to Shaik Ameer BashaThis patch adds missing clocks from WCORE block.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
drivers/clk/samsung/clk-exynos5420.c +28 -0
@@ -89,6 +89,7 @@#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_BUS_NOC 0x10770#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920
@@ -180,6 +181,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_BUS_NOC ,GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 , GATE_IP_GSCL1,
@@ -271,6 +273,13 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk100_noc_p) = {"dout_aclk100_noc" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk100_noc_p) = {"fin_pll" ,"mout_sw_aclk100_noc" }; + +PNAME (mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore" ,"mout_sclk_spll" }; +PNAME (mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore" ,"sclk_bpll" }; +PNAME (mout_user_aclk400_wcore_p) = {"fin_pll" ,"mout_sw_aclk400_wcore" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" };PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" };
@@ -486,6 +495,18 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk100_noc" , mout_group1_p,SRC_TOP0 ,20 ,2 ), +MUX (0 ,"mout_sw_aclk100_noc" , mout_sw_aclk100_noc_p, +SRC_TOP10 ,20 ,1 ), +MUX (0 ,"mout_user_aclk100_noc" , mout_user_aclk100_noc_p, +SRC_TOP3 ,20 ,1 ), +MUX (0 ,"mout_aclk400_wcore" , mout_group1_p,SRC_TOP0 ,16 ,2 ), +MUX (0 ,"mout_aclk400_wcore_bpll" , mout_aclk400_wcore_bpll_p, +TOP_SPARE2 ,4 ,1 ), +MUX (0 ,"mout_sw_aclk400_wcore" , mout_sw_aclk400_wcore_p, +SRC_TOP10 ,16 ,1 ), +MUX (0 ,"mout_user_aclk400_wcore" , mout_user_aclk400_wcore_p, +SRC_TOP3 ,16 ,1 ),MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ),MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, SRC_TOP10, 0, 1),
@@ -553,6 +574,10 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_disp1_blk" ,"aclk200_disp1" ,DIV2_RATIO0 ,16 ,2 ),DIV (0 ,"dout_aclk400_disp1" ,"mout_aclk400_disp1" ,DIV_TOP2 ,4 ,3 ), +DIV (0 ,"dout_aclk100_noc" ,"mout_aclk100_noc" ,DIV_TOP0 ,20 ,3 ), +DIV (0 ,"dout_aclk400_wcore" ,"mout_aclk400_wcore_bpll" , +DIV_TOP0 ,16 ,3 ), +/* Audio Block */ DIV (0 ,"dout_maudio0" ,"mout_maudio0" ,DIV_MAU ,20 ,4 ), DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
@@ -867,6 +892,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_IP_MSCL, 10, 0, 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +/* aclk266 also gates other IPs in psgen. It should not be gated. */ +GATE (0 ,"aclk266" ,"mout_user_aclk266" , +GATE_BUS_NOC ,22 ,CLK_IGNORE_UNUSED ,0 ),GATE (0 ,"aclk200_disp1" ,"mout_user_aclk200_disp1" ,GATE_BUS_TOP ,18 ,CLK_IGNORE_UNUSED ,0 ), GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
Signature · 1 line
1.7.9.5
PATCH v3 9/16 clk: exynos5420: update clocks for WCORE block
Hi Shaik,
Quoted 5 lines · Shaik Ameer Basha
This patch adds missing clocks from WCORE block.
Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Shaik Ameer Basha <[email protected]>---
Reviewed-by Alim Akhtar <[email protected]>
Quoted 85 lines
drivers/clk/samsung/clk-exynos5420.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)drivers/clk/samsung/clk-exynos5420.c +28
-1@@ -89,6 +89,7 @@#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760#define GATE_BUS_PERIS1 0x10764 +#define GATE_BUS_NOC 0x10770#define GATE_TOP_SCLK_ISP 0x10870#define GATE_IP_GSCL0 0x10910#define GATE_IP_GSCL1 0x10920@@ -180,6 +181,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_BUS_PERIC1 ,GATE_BUS_PERIS0 ,GATE_BUS_PERIS1 , +GATE_BUS_NOC ,GATE_TOP_SCLK_ISP ,GATE_IP_GSCL0 , GATE_IP_GSCL1,@@ -271,6 +273,13 @@ PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };PNAME (mout_user_aclk200_fsys2_p) = {"fin_pll" ,"mout_sw_aclk200_fsys2" }; +PNAME (mout_sw_aclk100_noc_p) = {"dout_aclk100_noc" ,"mout_sclk_spll" }; +PNAME (mout_user_aclk100_noc_p) = {"fin_pll" ,"mout_sw_aclk100_noc" }; + +PNAME (mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore" ,"mout_sclk_spll" }; +PNAME (mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore" ,"sclk_bpll" }; +PNAME (mout_user_aclk400_wcore_p) = {"fin_pll" ,"mout_sw_aclk400_wcore" }; +PNAME (mout_sw_aclk400_isp_p) = {"dout_aclk400_isp" ,"mout_sclk_spll" };PNAME (mout_user_aclk400_isp_p) = {"fin_pll" ,"mout_sw_aclk400_isp" };@@ -486,6 +495,18 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_aclk100_noc" , mout_group1_p,SRC_TOP0 ,20 ,2 ), +MUX (0 ,"mout_sw_aclk100_noc" , mout_sw_aclk100_noc_p, +SRC_TOP10 ,20 ,1 ), +MUX (0 ,"mout_user_aclk100_noc" , mout_user_aclk100_noc_p, +SRC_TOP3 ,20 ,1 ), +MUX (0 ,"mout_aclk400_wcore" , mout_group1_p,SRC_TOP0 ,16 ,2 ), +MUX (0 ,"mout_aclk400_wcore_bpll" , mout_aclk400_wcore_bpll_p, +TOP_SPARE2 ,4 ,1 ), +MUX (0 ,"mout_sw_aclk400_wcore" , mout_sw_aclk400_wcore_p, +SRC_TOP10 ,16 ,1 ), +MUX (0 ,"mout_user_aclk400_wcore" , mout_user_aclk400_wcore_p, +SRC_TOP3 ,16 ,1 ),MUX (0 ,"mout_aclk400_isp" , mout_group1_p,SRC_TOP0 ,0 ,2 ),MUX (0 ,"mout_sw_aclk400_isp" , mout_sw_aclk400_isp_p, SRC_TOP10, 0, 1),@@ -553,6 +574,10 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_disp1_blk" ,"aclk200_disp1" ,DIV2_RATIO0 ,16 ,2 ),DIV (0 ,"dout_aclk400_disp1" ,"mout_aclk400_disp1" ,DIV_TOP2 ,4 ,3 ), +DIV (0 ,"dout_aclk100_noc" ,"mout_aclk100_noc" ,DIV_TOP0 ,20 ,3 ), +DIV (0 ,"dout_aclk400_wcore" ,"mout_aclk400_wcore_bpll" , +DIV_TOP0 ,16 ,3 ), +/* Audio Block */ DIV (0 ,"dout_maudio0" ,"mout_maudio0" ,DIV_MAU ,20 ,4 ), DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),@@ -867,6 +892,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_IP_MSCL, 10, 0, 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), +/* aclk266 also gates other IPs in psgen. It should not be gated. */ +GATE (0 ,"aclk266" ,"mout_user_aclk266" , +GATE_BUS_NOC ,22 ,CLK_IGNORE_UNUSED ,0 ),GATE (0 ,"aclk200_disp1" ,"mout_user_aclk200_disp1" ,GATE_BUS_TOP ,18 ,CLK_IGNORE_UNUSED ,0 ), GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", --1.7.9.5
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PATCH v3 10/16 clk: exynos5420: update clocks for FSYS and FSYS2 blocks
In reply to Shaik Ameer BashaThis patch adds more clocks from FSYS and FSYS2 blocks and uses GATE_IP_* registers for gating IPs.
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 37 +++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 12 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +25 -12
@@ -85,6 +85,7 @@#define GATE_BUS_TOP 0x10700#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740 +#define GATE_BUS_FSYS2 0x10748#define GATE_BUS_PERIC 0x10750#define GATE_BUS_PERIC1 0x10754#define GATE_BUS_PERIS0 0x10760
@@ -97,6 +98,7 @@#define GATE_IP_DISP1 0x10928#define GATE_IP_G3D 0x10930#define GATE_IP_GEN 0x10934 +#define GATE_IP_FSYS 0x10944#define GATE_IP_PERIC 0x10950#define GATE_IP_PERIS 0x10960#define GATE_IP_MSCL 0x10970
@@ -177,6 +179,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_BUS_TOP ,GATE_BUS_GEN ,GATE_BUS_FSYS0 , +GATE_BUS_FSYS2 ,GATE_BUS_PERIC ,GATE_BUS_PERIC1 , GATE_BUS_PERIS0,
@@ -189,6 +192,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_IP_DISP1 ,GATE_IP_G3D ,GATE_IP_GEN , +GATE_IP_FSYS ,GATE_IP_PERIC ,GATE_IP_PERIS , GATE_IP_MSCL,
@@ -269,6 +273,8 @@ PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" };PNAME (mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"mout_sclk_spll" }; +PNAME (mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys" ,"mout_sclk_spll" }; +PNAME (mout_user_pclk200_fsys_p) = {"fin_pll" ,"mout_sw_pclk200_fsys" };PNAME (mout_user_aclk200_fsys_p) = {"fin_pll" ,"mout_sw_aclk200_fsys" };PNAME (mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2" ,"mout_sclk_spll" };
@@ -481,6 +487,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_mmc2" , mout_group2_p,SRC_FSYS ,16 ,3 ),MUX (0 ,"mout_usbd300" , mout_group2_p,SRC_FSYS ,20 ,3 ),MUX (0 ,"mout_unipro" , mout_group2_p,SRC_FSYS ,24 ,3 ), +MUX (0 ,"mout_mphy_refclk" , mout_group2_p,SRC_FSYS ,28 ,3 ),/* PERIC Block */ MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
@@ -495,6 +502,11 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), +MUX (0 ,"mout_pclk200_fsys" , mout_group1_p,SRC_TOP0 ,24 ,2 ), +MUX (0 ,"mout_sw_pclk200_fsys" , mout_sw_pclk200_fsys_p, +SRC_TOP10 ,24 ,1 ), +MUX (0 ,"mout_user_pclk200_fsys" , mout_user_pclk200_fsys_p, +SRC_TOP3 ,24 ,1 ),MUX (0 ,"mout_aclk100_noc" , mout_group1_p,SRC_TOP0 ,20 ,2 ),MUX (0 ,"mout_sw_aclk100_noc" , mout_sw_aclk100_noc_p, SRC_TOP10, 20, 1),
@@ -594,6 +606,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_mmc2" ,"mout_mmc2" ,DIV_FSYS1 ,20 ,10 ),DIV (0 ,"dout_unipro" ,"mout_unipro" ,DIV_FSYS2 ,24 ,8 ), +DIV (0 ,"dout_mphy_refclk" ,"mout_mphy_refclk" ,DIV_FSYS2 ,16 ,8 ),/* UART and PWM */ DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
@@ -720,12 +733,12 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_SCLK_USBPHY300 ,"sclk_usbphy300" ,"dout_usbphy300" ,GATE_TOP_SCLK_FSYS ,8 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_USBD300 ,"sclk_usbd300" ,"dout_usbd300" , -GATE_TOP_SCLK_FSYS ,9 ,CLK_SET_RATE_PARENT ,0 ), +GATE_TOP_SCLK_FSYS ,9 ,CLK_IGNORE_UNUSED ,0 ),GATE (CLK_SCLK_USBD301 ,"sclk_usbd301" ,"dout_usbd301" , -GATE_TOP_SCLK_FSYS ,10 ,CLK_SET_RATE_PARENT ,0 ), +GATE_TOP_SCLK_FSYS ,10 ,CLK_IGNORE_UNUSED ,0 ), -GATE (CLK_SCLK_USBD301 ,"sclk_unipro" ,"dout_unipro" , -SRC_MASK_FSYS ,24 ,CLK_SET_RATE_PARENT ,0 ), +GATE (CLK_SCLK_UNIPRO ,"sclk_unipro" ,"dout_unipro" , +GATE_IP_FSYS ,23 ,CLK_SET_RATE_PARENT ,0 ),GATE (CLK_SCLK_GSCL_WA ,"sclk_gscl_wa" ,"mout_user_aclk333_432_gscl" , GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
@@ -754,15 +767,15 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_PDMA0 ,"pdma0" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,1 ,0 ,0 ),GATE (CLK_PDMA1 ,"pdma1" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,2 ,0 ,0 ),GATE (CLK_UFS ,"ufs" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,3 ,0 ,0 ), -GATE (CLK_RTIC ,"rtic" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,5 ,0 ,0 ), -GATE (CLK_MMC0 ,"mmc0" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,12 ,0 ,0 ), -GATE (CLK_MMC1 ,"mmc1" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,13 ,0 ,0 ), -GATE (CLK_MMC2 ,"mmc2" ,"aclk200_fsys2" ,GATE_BUS_FSYS0 ,14 ,0 ,0 ), +GATE (CLK_RTIC ,"rtic" ,"aclk200_fsys" ,GATE_IP_FSYS ,9 ,0 ,0 ), +GATE (CLK_MMC0 ,"mmc0" ,"aclk200_fsys2" ,GATE_IP_FSYS ,12 ,0 ,0 ), +GATE (CLK_MMC1 ,"mmc1" ,"aclk200_fsys2" ,GATE_IP_FSYS ,13 ,0 ,0 ), +GATE (CLK_MMC2 ,"mmc2" ,"aclk200_fsys2" ,GATE_IP_FSYS ,14 ,0 ,0 ),GATE (CLK_SROMC ,"sromc" ,"aclk200_fsys2" , -GATE_BUS_FSYS0 ,19 ,CLK_IGNORE_UNUSED ,0 ), -GATE (CLK_USBH20 ,"usbh20" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,20 ,0 ,0 ), -GATE (CLK_USBD300 ,"usbd300" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,21 ,0 ,0 ), -GATE (CLK_USBD301 ,"usbd301" ,"aclk200_fsys" ,GATE_BUS_FSYS0 ,28 ,0 ,0 ), +GATE_IP_FSYS ,17 ,CLK_IGNORE_UNUSED ,0 ), +GATE (CLK_USBH20 ,"usbh20" ,"aclk200_fsys" ,GATE_IP_FSYS ,18 ,0 ,0 ), +GATE (CLK_USBD300 ,"usbd300" ,"aclk200_fsys" ,GATE_IP_FSYS ,19 ,0 ,0 ), +GATE (CLK_USBD301 ,"usbd301" ,"aclk200_fsys" ,GATE_IP_FSYS ,20 ,0 ,0 ),/* UART */ GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),
Signature · 1 line
1.7.9.5
PATCH v3 11/16 clk: exynos5420: correct sysmmu-mfc parent clocks
In reply to Shaik Ameer BashaThis patch corrects the wrong parent-child relationship between sysmmu-mfc clocks.
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +7 -2
@@ -82,6 +82,7 @@#define SCLK_DIV_ISP0 0x10580#define SCLK_DIV_ISP1 0x10584#define DIV2_RATIO0 0x10590 +#define DIV4_RATIO 0x105a0#define GATE_BUS_TOP 0x10700#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740
@@ -176,6 +177,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SCLK_DIV_ISP0 ,SCLK_DIV_ISP1 ,DIV2_RATIO0 , +DIV4_RATIO ,GATE_BUS_TOP ,GATE_BUS_GEN , GATE_BUS_FSYS0,
@@ -636,6 +638,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_spi1_pre" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_spi2_pre" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), +/* Mfc Blk */ +DIV (0 ,"dout_mfc_blk" ,"mout_user_aclk333" ,DIV4_RATIO ,0 ,2 ), +/* GSCL Block */ DIV (0 ,"dout_gscl_blk_300" ,"mout_user_aclk300_gscl" , DIV2_RATIO0, 4, 2),
@@ -873,8 +878,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_IP_DISP1, 8, 0, 0),GATE (CLK_MFC ,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ), -GATE (CLK_SMMU_MFCL ,"smmu_mfcl" ,"aclk333" ,GATE_IP_MFC ,1 ,0 ,0 ), -GATE (CLK_SMMU_MFCR ,"smmu_mfcr" ,"aclk333" ,GATE_IP_MFC ,2 ,0 ,0 ), +GATE (CLK_SMMU_MFCL ,"smmu_mfcl" ,"dout_mfc_blk" ,GATE_IP_MFC ,1 ,0 ,0 ), +GATE (CLK_SMMU_MFCR ,"smmu_mfcr" ,"dout_mfc_blk" ,GATE_IP_MFC ,2 ,0 ,0 ), GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
Signature · 1 line
1.7.9.5
PATCH v3 11/16 clk: exynos5420: correct sysmmu-mfc parent clocks
Hi Shaik,
Quoted 5 lines · Shaik Ameer Basha
This patch corrects the wrong parent-child relationship between sysmmu-mfc clocks.
Signed-off-by Shaik Ameer Basha <[email protected]>---
Hoping you have tested vedio playback with this patch, especially after across a suspend/resume cycles.
This looks ok.
Reviewed-by Alim Akhtar <[email protected]>
Quoted 52 lines
drivers/clk/samsung/clk-exynos5420.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)drivers/clk/samsung/clk-exynos5420.c +7
-3@@ -82,6 +82,7 @@#define SCLK_DIV_ISP0 0x10580#define SCLK_DIV_ISP1 0x10584#define DIV2_RATIO0 0x10590 +#define DIV4_RATIO 0x105a0#define GATE_BUS_TOP 0x10700#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740@@ -176,6 +177,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = {SCLK_DIV_ISP0 ,SCLK_DIV_ISP1 ,DIV2_RATIO0 , +DIV4_RATIO ,GATE_BUS_TOP ,GATE_BUS_GEN , GATE_BUS_FSYS0,@@ -636,6 +638,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (0 ,"dout_spi1_pre" ,"dout_spi1" ,DIV_PERIC4 ,16 ,8 ),DIV (0 ,"dout_spi2_pre" ,"dout_spi2" ,DIV_PERIC4 ,24 ,8 ), +/* Mfc Blk */ +DIV (0 ,"dout_mfc_blk" ,"mout_user_aclk333" ,DIV4_RATIO ,0 ,2 ), +/* GSCL Block */ DIV (0 ,"dout_gscl_blk_300" ,"mout_user_aclk300_gscl" , DIV2_RATIO0, 4, 2),@@ -873,8 +878,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_IP_DISP1, 8, 0, 0),GATE (CLK_MFC ,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ), -GATE (CLK_SMMU_MFCL ,"smmu_mfcl" ,"aclk333" ,GATE_IP_MFC ,1 ,0 ,0 ), -GATE (CLK_SMMU_MFCR ,"smmu_mfcr" ,"aclk333" ,GATE_IP_MFC ,2 ,0 ,0 ), +GATE (CLK_SMMU_MFCL ,"smmu_mfcl" ,"dout_mfc_blk" ,GATE_IP_MFC ,1 ,0 ,0 ), +GATE (CLK_SMMU_MFCR ,"smmu_mfcr" ,"dout_mfc_blk" ,GATE_IP_MFC ,2 ,0 ,0 ), GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 12/16 clk: exynos5420: fix register offset for sclk_bpll
In reply to Shaik Ameer BashaThis patch fixes the wrong register offset for sclk_bpll clock.
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +1 -3
@@ -111,7 +111,6 @@#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110 -#define SRC_CDREX 0x20200#define KPLL_LOCK 0x28000#define KPLL_CON0 0x28100#define SRC_KFC 0x28200
@@ -204,7 +203,6 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_TOP_SCLK_FSYS ,GATE_TOP_SCLK_PERIC ,TOP_SPARE2 , -SRC_CDREX ,SRC_KFC , DIV_KFC0, };
@@ -380,7 +378,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 ),MUX (0 ,"mout_kfc" , mout_kfc_p,SRC_KFC ,16 ,1 ), -MUX (0 ,"sclk_bpll" , mout_bpll_p,SRC_CDREX ,0 ,1 ), +MUX (0 ,"sclk_bpll" , mout_bpll_p,TOP_SPARE2 ,0 ,1 ),MUX_A (0 ,"mout_aclk400_mscl" , mout_group1_p, SRC_TOP0, 4, 2, "aclk400_mscl"),
Signature · 1 line
1.7.9.5
PATCH v3 12/16 clk: exynos5420: fix register offset for sclk_bpll
Hi shaik,
Quoted 4 lines · Shaik Ameer Basha
This patch fixes the wrong register offset for
sclk_bpllclock.Signed-off-by Shaik Ameer Basha <[email protected]>---
Reviwed-by Alim Akhtar <[email protected]>
Quoted 24 lines
drivers/clk/samsung/clk-exynos5420.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)drivers/clk/samsung/clk-exynos5420.c +0
-2@@ -111,7 +111,6 @@#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110 -#define SRC_CDREX 0x20200#define KPLL_LOCK 0x28000#define KPLL_CON0 0x28100#define SRC_KFC 0x28200@@ -204,7 +203,6 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_TOP_SCLK_FSYS ,GATE_TOP_SCLK_PERIC ,TOP_SPARE2 , -SRC_CDREX ,SRC_KFC , DIV_KFC0, };
drivers/clk/samsung/clk-exynos5420.c static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { · line 381
Quoted 5 lines
drivers/clk/samsung/clk-exynos5420.c +1
-1@@ -380,7 +378,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 ),MUX (0 ,"mout_kfc" , mout_kfc_p,SRC_KFC ,16 ,1 ), - MUX(0, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), + MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
Hmmm. Nice catch
Quoted 11 lines
drivers/clk/samsung/clk-exynos5420.c +0
-1MUX_A (0 ,"mout_aclk400_mscl" , mout_group1_p, SRC_TOP0, 4, 2, "aclk400_mscl"), --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 12/16 clk: exynos5420: fix register offset for sclk_bpll
In reply to Shaik Ameer BashaHi Shaik,
Quoted 1 line · Shaik Ameer Basha
This patch fixes the wrong register offset for
sclk_bpllclock.
Since this patch is a fix, it is better to send it separately so that it gets into one of
the upcoming RCs (and if needed to stable).
Quoted 42 lines
Signed-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)drivers/clk/samsung/clk-exynos5420.c +1
-4@@ -111,7 +111,6 @@#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110 -#define SRC_CDREX 0x20200#define KPLL_LOCK 0x28000#define KPLL_CON0 0x28100#define SRC_KFC 0x28200@@ -204,7 +203,6 @@ static unsigned long exynos5420_clk_regs[] __initdata = {GATE_TOP_SCLK_FSYS ,GATE_TOP_SCLK_PERIC ,TOP_SPARE2 , -SRC_CDREX ,SRC_KFC , DIV_KFC0, };@@ -380,7 +378,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_kpll" , mout_kpll_p,SRC_KFC ,0 ,1 ),MUX (0 ,"mout_kfc" , mout_kfc_p,SRC_KFC ,16 ,1 ), -MUX (0 ,"sclk_bpll" , mout_bpll_p,SRC_CDREX ,0 ,1 ), +MUX (0 ,"sclk_bpll" , mout_bpll_p,TOP_SPARE2 ,0 ,1 ),MUX_A (0 ,"mout_aclk400_mscl" , mout_group1_p, SRC_TOP0, 4, 2, "aclk400_mscl"), --1.7.9.5
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Signature · 2 lines
With warm regards, Sachin
PATCH v3 13/16 clk: exynos5420: cleanup core and misc clocks
In reply to Shaik Ameer BashaThis patch renames some of the clocks according to the datasheet. It also adds and updates some core and misc clocks.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 29 +++++++++++++++++++++++------ include/dt-bindings/clock/exynos5420.h | 3 +++ 2 files changed, 26 insertions(+), 6 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +23 -6
@@ -62,7 +62,8 @@#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288#define SRC_MASK_TOP2 0x10308 -#define SRC_MASK_DISP10 0x1032c +#define SRC_MASK_DISP10 0x1032c +#define SRC_MASK_MAU 0x10334#define SRC_MASK_FSYS 0x10340#define SRC_MASK_PERIC0 0x10350#define SRC_MASK_PERIC1 0x10354
@@ -271,6 +272,7 @@ PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};PNAME (mout_fimd1_final_p) = {"mout_fimd1" ,"mout_fimd1_opt" };PNAME (mout_sw_aclk66_p) = {"dout_aclk66" ,"mout_sclk_spll" };PNAME (mout_user_aclk66_peric_p) = {"fin_pll" ,"mout_sw_aclk66" }; +PNAME (mout_user_aclk66_gpio_p) = {"mout_sw_aclk66" ,"ffactor_sw_aclk66" };PNAME (mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys" ,"mout_sclk_spll" };PNAME (mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys" ,"mout_sclk_spll" };
@@ -351,6 +353,8 @@ PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};PNAME (mout_maudio0_p) = {"fin_pll" ,"maudio_clk" ,"mout_sclk_dpll" ,"mout_sclk_mpll" ,"mout_sclk_spll" ,"mout_sclk_ipll" ,"mout_sclk_epll" ,"mout_sclk_rpll" }; +PNAME (mout_mau_epll_clk_p) = {"mout_sclk_epll" ,"mout_sclk_dpll" , +"mout_sclk_mpll" ,"mout_sclk_spll" };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[]__initdata = {
@@ -367,7 +371,8 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = };static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[]__initdata = { -FFACTOR (0 ,"sclk_hsic_12m" ,"fin_pll" ,1 ,2 ,0 ), +FFACTOR (0 ,"ffactor_hsic_12m" ,"fin_pll" ,1 ,2 ,0 ), +FFACTOR (0 ,"ffactor_sw_aclk66" ,"mout_sw_aclk66" ,1 ,2 ,0 ), };static struct samsung_mux_clock exynos5420_mux_clks[]__initdata = {
@@ -478,7 +483,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { TOP_SPARE2, 8, 1, CLK_SET_RATE_PARENT, 0),/* MAU Block */ -MUX (0 ,"mout_maudio0" , mout_maudio0_p,SRC_MAU ,28 ,3 ), +MUX_F (CLK_MOUT_MAUDIO0 ,"mout_maudio0" , mout_maudio0_p,SRC_MAU ,28 ,3 , +CLK_SET_RATE_PARENT ,0 ),/* FSYS Block */ MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
@@ -502,6 +508,11 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (0 ,"mout_spi0" , mout_group2_p,SRC_PERIC1 ,20 ,3 ),MUX (0 ,"mout_spi1" , mout_group2_p,SRC_PERIC1 ,24 ,3 ),MUX (0 ,"mout_spi2" , mout_group2_p,SRC_PERIC1 ,28 ,3 ), + +MUX (0 ,"mout_user_aclk66_gpio" , mout_user_aclk66_gpio_p, +SRC_TOP7 ,4 ,1 ), +MUX_F (0 ,"mout_mau_epll_clk" , mout_mau_epll_clk_p,SRC_TOP7 ,20 ,2 , +CLK_SET_RATE_PARENT ,0 ),MUX (0 ,"mout_pclk200_fsys" , mout_group1_p,SRC_TOP0 ,24 ,2 ),MUX (0 ,"mout_sw_pclk200_fsys" , mout_sw_pclk200_fsys_p, SRC_TOP10, 24, 1),
@@ -552,10 +563,10 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { };static struct samsung_div_clock exynos5420_div_clks[]__initdata = { -DIV (0 ,"div_arm" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ), +DIV (0 ,"dout_armclk1" ,"mout_cpu" ,DIV_CPU0 ,0 ,3 ),DIV (0 ,"sclk_apll" ,"mout_apll" ,DIV_CPU0 ,24 ,3 ), -DIV (0 ,"armclk2" ,"div_arm" ,DIV_CPU0 ,28 ,3 ), -DIV (0 ,"div_kfc" ,"mout_cpu_kfc" ,DIV_KFC0 ,0 ,3 ), +DIV (0 ,"dout_armclk2" ,"dout_armclk1" ,DIV_CPU0 ,28 ,3 ), +DIV (0 ,"dout_kfc" ,"mout_kfc" ,DIV_KFC0 ,0 ,3 ),DIV (0 ,"sclk_kpll" ,"mout_kpll" ,DIV_KFC0 ,24 ,3 ),DIV (0 ,"dout_aclk400_mscl" ,"mout_aclk400_mscl" ,DIV_TOP0 ,4 ,3 ),
@@ -908,6 +919,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_IP_MSCL, 10, 0, 0),GATE (CLK_SMMU_MIXER ,"smmu_mixer" ,"aclk200_disp1" ,GATE_IP_DISP1 ,9 ,0 ,0 ), + +/* aclk333 gates internal MFC busses and should not be gated. */ /* aclk266 also gates other IPs in psgen. It should not be gated. */ GATE (0 ,"aclk266" ,"mout_user_aclk266" , GATE_BUS_NOC, 22, CLK_IGNORE_UNUSED, 0),
@@ -928,6 +941,10 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { "mout_user_aclk333_432_isp", GATE_BUS_TOP, 8, 0, 0),GATE (CLK_MC ,"mc" ,"aclk66_psgen" ,GATE_BUS_GEN ,12 ,0 ,0 ),GATE (CLK_TOP_RTC ,"top_rtc" ,"aclk66_psgen" ,GATE_IP_GEN ,5 ,0 ,0 ), +GATE (CLK_SCLK_HSIC_12M ,"sclk_hsic_12m" ,"ffactor_hsic_12m" , +GATE_BUS_TOP ,29 ,0 ,0 ), +GATE (CLK_SCLK_MPHY_IXTAL24 ,"sclk_mphy_ixtal24" ,"mphy_refclk_ixtal24" , +GATE_BUS_TOP ,28 ,0 ,0 ),/* G2D */ GATE(CLK_G2D, "g2d", "aclk333_g2d",
include/dt-bindings/clock/exynos5420.h +3 -0
@@ -58,6 +58,8 @@#define CLK_SCLK_GSCL_WA 156#define CLK_SCLK_GSCL_WB 157#define CLK_SCLK_HDMIPHY 158 +#define CLK_SCLK_HSIC_12M 167 +#define CLK_SCLK_MPHY_IXTAL24 168/* gate clocks */ #define CLK_ACLK66_PERIC 256
@@ -187,6 +189,7 @@/* mux clocks */ #define CLK_MOUT_HDMI 640 +#define CLK_MOUT_MAUDIO0 642/* divider clocks */ #define CLK_DOUT_PIXEL 768
Signature · 1 line
1.7.9.5
PATCH v3 14/16 clk: exynos5420: correct g3d parent clock
In reply to Shaik Ameer BashaThis patch fixes the g3d parent clock.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 7 +++---- include/dt-bindings/clock/exynos5420.h | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-)
drivers/clk/samsung/clk-exynos5420.c +3 -4
@@ -427,8 +427,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 8, 1),MUX (0 ,"mout_user_aclk266_g2d" , mout_user_aclk266_g2d_p,SRC_TOP5 ,12 ,1 ), -MUX_A (0 ,"mout_user_aclk_g3d" , mout_user_aclk_g3d_p, -SRC_TOP5 ,16 ,1 ,"aclkg3d" ), +MUX (CLK_MOUT_G3D ,"mout_user_aclk_g3d" , mout_user_aclk_g3d_p, +SRC_TOP5 ,16 ,1 ),MUX (0 ,"mout_user_aclk300_jpeg" , mout_user_aclk300_jpeg_p,SRC_TOP5 ,20 ,1 ), MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
@@ -889,8 +889,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (CLK_MFC ,"mfc" ,"aclk333" ,GATE_IP_MFC ,0 ,0 ,0 ),GATE (CLK_SMMU_MFCL ,"smmu_mfcl" ,"dout_mfc_blk" ,GATE_IP_MFC ,1 ,0 ,0 ),GATE (CLK_SMMU_MFCR ,"smmu_mfcr" ,"dout_mfc_blk" ,GATE_IP_MFC ,2 ,0 ,0 ), - -GATE (CLK_G3D ,"g3d" ,"aclkg3d" ,GATE_IP_G3D ,9 ,0 ,0 ), +GATE (CLK_G3D ,"g3d" ,"mout_user_aclk_g3d" ,GATE_IP_G3D ,9 ,0 ,0 ),GATE (CLK_ROTATOR ,"rotator" ,"mout_user_aclk266" ,GATE_IP_GEN ,1 ,0 ,0 ), GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
include/dt-bindings/clock/exynos5420.h +1 -1
@@ -176,7 +176,6 @@#define CLK_SMMU_FIMCL1 493#define CLK_SMMU_FIMCL3 494#define CLK_FIMC_LITE3 495 -#define CLK_ACLK_G3D 500#define CLK_G3D 501#define CLK_SMMU_MIXER 502#define CLK_SMMU_G2D 503
@@ -190,6 +189,7 @@/* mux clocks */ #define CLK_MOUT_HDMI 640#define CLK_MOUT_MAUDIO0 642 +#define CLK_MOUT_G3D 643/* divider clocks */ #define CLK_DOUT_PIXEL 768
Signature · 1 line
1.7.9.5
PATCH v3 15/16 clk: exynos5420: create clock ID for mout_sclk_vpll
In reply to Shaik Ameer BashaThis patch adds clock ID for mout_sclk_vpll clock
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 2 +- include/dt-bindings/clock/exynos5420.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5420.c +1 -1
@@ -437,7 +437,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { SRC_TOP5, 28, 1),MUX (0 ,"mout_sclk_mpll" , mout_mpll_p,SRC_TOP6 ,0 ,1 ), -MUX (0 ,"mout_sclk_vpll" , mout_vpll_p,SRC_TOP6 ,4 ,1 ), +MUX (CLK_MOUT_VPLL ,"mout_sclk_vpll" , mout_vpll_p,SRC_TOP6 ,4 ,1 ),MUX (0 ,"mout_sclk_spll" , mout_spll_p,SRC_TOP6 ,8 ,1 ),MUX (0 ,"mout_sclk_ipll" , mout_ipll_p,SRC_TOP6 ,12 ,1 ), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
include/dt-bindings/clock/exynos5420.h +1 -0
@@ -190,6 +190,7 @@#define CLK_MOUT_HDMI 640#define CLK_MOUT_MAUDIO0 642#define CLK_MOUT_G3D 643 +#define CLK_MOUT_VPLL 644/* divider clocks */ #define CLK_DOUT_PIXEL 768
Signature · 1 line
1.7.9.5
PATCH v3 15/16 clk: exynos5420: create clock ID for mout_sclk_vpll
Hi Shaik
Quoted 13 lines · Shaik Ameer Basha
This patch adds clock ID for
mout_sclk_vpllclockSigned-off-by Shaik Ameer Basha <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 2 +- include/dt-bindings/clock/exynos5420.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)drivers/clk/samsung/clk-exynos5420.c +0
-0
drivers/clk/samsung/clk-exynos5420.c static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { · line 440
Quoted 5 lines
drivers/clk/samsung/clk-exynos5420.c +1
-1@@ -437,7 +437,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { SRC_TOP5, 28, 1),MUX (0 ,"mout_sclk_mpll" , mout_mpll_p,SRC_TOP6 ,0 ,1 ), - MUX(0, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), + MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
Any perticular reason for just this change??
Quoted 23 lines
drivers/clk/samsung/clk-exynos5420.c +0
-0MUX (0 ,"mout_sclk_spll" , mout_spll_p,SRC_TOP6 ,8 ,1 ),MUX (0 ,"mout_sclk_ipll" , mout_ipll_p,SRC_TOP6 ,12 ,1 ), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),include/dt-bindings/clock/exynos5420.h +1
-1@@ -190,6 +190,7 @@#define CLK_MOUT_HDMI 640#define CLK_MOUT_MAUDIO0 642#define CLK_MOUT_G3D 643 +#define CLK_MOUT_VPLL 644/* divider clocks */ #define CLK_DOUT_PIXEL 768 --1.7.9.5
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Signature · 2 lines
Regards, Alim
PATCH v3 16/16 clk: exynos5420: add more registers to restore list
In reply to Shaik Ameer BashaThis patch adds more register offsets to the restore list.
Signed-off-by Shaik Ameer Basha <[email protected]>
--- drivers/clk/samsung/clk-exynos5420.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
drivers/clk/samsung/clk-exynos5420.c +12 -0
@@ -27,6 +27,7 @@#define DIV_CPU1 0x504#define GATE_BUS_CPU 0x700#define GATE_SCLK_CPU 0x800 +#define CLKOUT_CMU_CPU 0xa00#define GATE_IP_G2D 0x8800#define CPLL_LOCK 0x10020#define DPLL_LOCK 0x10030
@@ -39,7 +40,11 @@#define CPLL_CON0 0x10120#define DPLL_CON0 0x10128#define EPLL_CON0 0x10130 +#define EPLL_CON1 0x10134 +#define EPLL_CON2 0x10138#define RPLL_CON0 0x10140 +#define RPLL_CON1 0x10144 +#define RPLL_CON2 0x10148#define IPLL_CON0 0x10150#define SPLL_CON0 0x10160#define VPLL_CON0 0x10170
@@ -139,6 +144,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_CPU1 ,GATE_BUS_CPU ,GATE_SCLK_CPU , +CLKOUT_CMU_CPU , +EPLL_CON0 , +EPLL_CON1 , +EPLL_CON2 , +RPLL_CON0 , +RPLL_CON1 , +RPLL_CON2 ,SRC_TOP0 ,SRC_TOP1 , SRC_TOP2,
Signature · 1 line
1.7.9.5
PATCH v3 16/16 clk: exynos5420: add more registers to restore list
Hi Shaik
Quoted 4 lines · Shaik Ameer Basha
This patch adds more register offsets to the restore list.
Signed-off-by Shaik Ameer Basha <[email protected]>---
Reviewed-by Alim Akhtar <[email protected]>
Quoted 49 lines
drivers/clk/samsung/clk-exynos5420.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/clk/samsung/clk-exynos5420.c +12
-1@@ -27,6 +27,7 @@#define DIV_CPU1 0x504#define GATE_BUS_CPU 0x700#define GATE_SCLK_CPU 0x800 +#define CLKOUT_CMU_CPU 0xa00#define GATE_IP_G2D 0x8800#define CPLL_LOCK 0x10020#define DPLL_LOCK 0x10030@@ -39,7 +40,11 @@#define CPLL_CON0 0x10120#define DPLL_CON0 0x10128#define EPLL_CON0 0x10130 +#define EPLL_CON1 0x10134 +#define EPLL_CON2 0x10138#define RPLL_CON0 0x10140 +#define RPLL_CON1 0x10144 +#define RPLL_CON2 0x10148#define IPLL_CON0 0x10150#define SPLL_CON0 0x10160#define VPLL_CON0 0x10170@@ -139,6 +144,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {DIV_CPU1 ,GATE_BUS_CPU ,GATE_SCLK_CPU , +CLKOUT_CMU_CPU , +EPLL_CON0 , +EPLL_CON1 , +EPLL_CON2 , +RPLL_CON0 , +RPLL_CON1 , +RPLL_CON2 ,SRC_TOP0 ,SRC_TOP1 , SRC_TOP2, --1.7.9.5
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Signature · 2 lines
Regards, Alim
v3 cover exynos5420: clock file cleanup
In reply to Shaik Ameer BashaQuoted 11 lines · Shaik Ameer Basha
Many changes/fixes have been identified for clock file for exynos5420. These include correct parents, bit fields, new clocks etc. Existing files needs some correction in terms of names of the clock and indentation. These issues are addressed in this patch series. It also replaces the usage of enums with macro as clock ids.
This patch series is rebased on,
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git:masterThis patch is also dependent on the following patch.
ARM: dts: add dt node for sss module for exynos5250/5420
Sorry, it depends on SSS clock patch. Not the dts one.
clk: samsung exynos5250/5420: Add gate clock for SSS module
Quoted 39 lines
Changes since v2:
-----------------
1] Addressed review comments from Gerhard Sittig and Tomasz Figa.Changes since v1:
-----------------
1] Addressed review comments from Tomasz Figa.http://www.spinics.net/lists/devicetree/msg16759.html http://www.spinics.net/lists/devicetree/msg16760.htmlShaik Ameer Basha (16):
clk: exynos5420: rename parent clocks
clk: exynos5420: add clocks for ISP block
clk: exynos5420: update clocks for GSCL and MSCL blocks
clk: exynos5420: correct clock parents for mscl sysmmu
clk: exynos5420: update clocks for G2D block
clk: exynos5420: update clocks for DISP1 block
clk: exynos5420: update clocks for PERIC block
clk: exynos5420: update clocks for PERIS and GEN blocks
clk: exynos5420: update clocks for WCORE block
clk: exynos5420: update clocks for FSYS and FSYS2 blocks
clk: exynos5420: correct sysmmu-mfc parent clocks
clk: exynos5420: fix register offset forsclk_bpll
clk: exynos5420: cleanup core and misc clocks
clk: exynos5420: correct g3d parent clock
clk: exynos5420: create clock ID formout_sclk_vpll
clk: exynos5420: add more registers to restore listarch/arm/boot/dts/exynos5420.dtsi | 14 +- drivers/clk/samsung/clk-exynos5420.c | 808 ++++++++++++++++++++------------ include/dt-bindings/clock/exynos5420.h | 33 +- 3 files changed, 550 insertions(+), 305 deletions(-) mode change 100644 => 100755 drivers/clk/samsung/clk-exynos5420.c mode change 100644 => 100755 include/dt-bindings/clock/exynos5420.h--
1.7.9.5
v3 cover exynos5420: clock file cleanup
In reply to Shaik Ameer BashaHi Shaik,
Quoted 11 lines · Shaik Ameer Basha
Many changes/fixes have been identified for clock file for exynos5420. These include correct parents, bit fields, new clocks etc. Existing files needs some correction in terms of names of the clock and indentation. These issues are addressed in this patch series. It also replaces the usage of enums with macro as clock ids.
This patch series is rebased on,
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git:masterThis patch is also dependent on the following patch.
ARM: dts: add dt node for sss module for exynos5250/5420
I think it would be nice to mention on what hardware this series was tested and how.
Also I'd like to see contents of /sys/kernel/debug/clk/clk_summary and /sys/kernel/debug/clk/orphans/ before and after applying this series.
Best regards,
Tomasz
v3 cover exynos5420: clock file cleanup
In reply to Shaik Ameer BashaQuoted 11 lines · Shaik Ameer Basha
Many changes/fixes have been identified for clock file for exynos5420. These include correct parents, bit fields, new clocks etc. Existing files needs some correction in terms of names of the clock and indentation. These issues are addressed in this patch series. It also replaces the usage of enums with macro as clock ids.
This patch series is rebased on,
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git:masterThis patch is also dependent on the following patch.
ARM: dts: add dt node for sss module for exynos5250/5420
Also a general comment to all the patches. Please assign clock IDs for all the clocks being added. In general, all the defined clocks should have clock IDs defined to let them be accessed from Device Tree, for example in case of DT clock initialization that is being worked on right now.
Best regards,
Tomasz
v3 cover exynos5420: clock file cleanup
Hi Tomasz,
Quoted 11 lines · Tomasz Figa
Quoted 10 lines · Shaik Ameer Basha
Many changes/fixes have been identified for clock file for exynos5420. These include correct parents, bit fields, new clocks etc. Existing files needs some correction in terms of names of the clock and indentation. These issues are addressed in this patch series. It also replaces the usage of enums with macro as clock ids.
This patch series is rebased on,
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git:master
Quoted 8 lines
Quoted 2 lines
This patch is also dependent on the following patch.
ARM: dts: add dt node for sss module for exynos5250/5420Also a general comment to all the patches. Please assign clock IDs for all the clocks being added. In general, all the defined clocks should have clock IDs defined to let them be accessed from Device Tree, for example in case of DT clock initialization that is being worked on right now.
Ok. Will take care of this in next series.
Regards,
Shaik
Quoted 3 lines
Best regards,
Tomasz