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S5P: Exynos: Add GPIO numbering feature

PATCH Superseded Akshay Saraswat 3 participants 5 messages May 5, 2014 – May 6, 2014

Subsystems (3)
Arm (32-bit) GPIO Arm Samsung Exynos

v11 of 13 Superseded Latest is v13 →

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Akshay Saraswat

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#0 lore raw

v11 cover S5P: Exynos: Add GPIO numbering feature

Used a script to recheck/verify pin mapping and existing mapping appears to be fine, returning correct bank and pin values. Did ./MAKEALL -a arm and found all Exynos/S5P related boards compiled successfully.
Couldn't test booting over all of them.
Tested U-Boot bootup over SMDK5420, SMDK5250, Snow. Requesting maintaners to please test over affected SoCs/boards.

Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass
and supported same for EXYNOS5.
Changes in V3:
- New patch added to rename S5P GPIO definitions
to S5P_GPIO.
- GPIO Table added to calculate the base address
of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver.
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Rebased on latest u-boot-samsung tree.
- Removed Exynos5 specific code in gpio driver api to get bank.
- Added #define HAVE_GENERIC_GPIO in config file
to remove conditinal CPU check in gpio driver.
Changes in V6:
- Isolated config changes in a new patch.
- Updated patches with corresponding changes for Exynos 5420.
Changes in V7:
- Added changes for other SoCs like Exynos 4412, 4210 etc.
Changes in V8:
- Changed Subject of patch 2/2 to reflect affected SoCs/boards.
- Fixed arndale board compile time errors introduced due to patch-set v7.
Changes in V9:
- Fixed checkpatch errors.
- Fixed naming error in exynosxxxx_gpio_data arrays which could be the possible reason behind data abort witnessed over Exynos4 boards.
Changes in v10:
- Made arch-exynos/gpio.h -> arch/gpio.h.
- Removed dead code.
- Replaced exynos_gpio_get calls with corresponding pin number.
- Edited pin numbmers in dts files.
Changes in v11:
- Created and fixed pinmux config for Exynos 4412.
- Removed dead code.

Akshay Saraswat (2):
S5P: Exynos: Add GPIO pin numbering and rename definitions
S5P: Exynos: Config: Enable GPIO CMD config

 arch/arm/cpu/armv7/exynos/pinmux.c         |  549 +++++----
 arch/arm/dts/exynos4210-origen.dts         |    4 +-
 arch/arm/dts/exynos4210-trats.dts          |    6 +-
 arch/arm/dts/exynos4210-universal_c210.dts |    4 +-
 arch/arm/dts/exynos4412-trats2.dts         |    4 +-
 arch/arm/include/asm/arch-exynos/cpu.h     |   17 +-
 arch/arm/include/asm/arch-exynos/gpio.h    | 1761 +++++++++++++++++++++++-----
 arch/arm/include/asm/arch-s5pc1xx/gpio.h   |  945 ++++++++++++---
 board/samsung/arndale/arndale.c            |   11 +-
 board/samsung/goni/goni.c                  |   26 +-
 board/samsung/smdk5250/exynos5-dt.c        |   20 +-
 board/samsung/smdk5250/smdk5250.c          |   19 +-
 board/samsung/smdk5420/smdk5420.c          |   15 +-
 board/samsung/smdkc100/smdkc100.c          |    5 +-
 board/samsung/smdkv310/smdkv310.c          |   17 +-
 board/samsung/trats/trats.c                |   39 +-
 board/samsung/trats2/trats2.c              |   74 +-
 board/samsung/universal_c210/universal.c   |   51 +-
 drivers/gpio/s5p_gpio.c                    |  198 +++-
 include/configs/exynos5-dt.h               |    2 +
 include/configs/s5p_goni.h                 |    4 +-
 include/configs/s5pc210_universal.h        |   16 +-
 include/configs/smdkv310.h                 |    1 +
 include/configs/trats.h                    |    8 +-
 include/configs/trats2.h                   |    4 +-
 25 files changed, 2902 insertions(+), 898 deletions(-)
Signature · 1 line
1.8.3.2
author
#1 lore raw

PATCH v11 1/2 S5P: Exynos: Add GPIO pin numbering and rename definitions

This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

* Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation.

* Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
---
 arch/arm/cpu/armv7/exynos/pinmux.c         |  549 +++++----
 arch/arm/dts/exynos4210-origen.dts         |    4 +-
 arch/arm/dts/exynos4210-trats.dts          |    6 +-
 arch/arm/dts/exynos4210-universal_c210.dts |    4 +-
 arch/arm/dts/exynos4412-trats2.dts         |    4 +-
 arch/arm/include/asm/arch-exynos/cpu.h     |   17 +-
 arch/arm/include/asm/arch-exynos/gpio.h    | 1761 +++++++++++++++++++++++-----
 arch/arm/include/asm/arch-s5pc1xx/gpio.h   |  950 ++++++++++++---
 board/samsung/arndale/arndale.c            |   11 +-
 board/samsung/goni/goni.c                  |   26 +-
 board/samsung/smdk5250/exynos5-dt.c        |   20 +-
 board/samsung/smdk5250/smdk5250.c          |   19 +-
 board/samsung/smdk5420/smdk5420.c          |   15 +-
 board/samsung/smdkc100/smdkc100.c          |    5 +-
 board/samsung/smdkv310/smdkv310.c          |   17 +-
 board/samsung/trats/trats.c                |   39 +-
 board/samsung/trats2/trats2.c              |   74 +-
 board/samsung/universal_c210/universal.c   |   51 +-
 drivers/gpio/s5p_gpio.c                    |  198 +++-
 19 files changed, 2883 insertions(+), 887 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +312 -237
index 9edb475..9e26340 100644
@@ -13,30 +13,23 @@
 
 static void exynos5_uart_config(int peripheral)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->d0;
-		start = 0;
+		start = EXYNOS5_GPIO_D00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5_GPIO_A14;
 		count = 2;
 		break;
 	default:

@@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral)
 		return;
 	}
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 	}
 }
 
 static void exynos5420_uart_config(int peripheral)
 {
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5420_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->a0;
-		start = 4;
+		start = EXYNOS5420_GPIO_A04;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5420_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5420_GPIO_A14;
 		count = 2;
 		break;
 	default:

@@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral)
 	}
 
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 	}
 }
 
 static int exynos5_mmc_config(int peripheral, int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank, *bank_ext;
-	int i, start = 0, gpio_func = 0;
+	int i, start, start_ext, gpio_func = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio1->c0;
-		bank_ext = &gpio1->c1;
-		start = 0;
-		gpio_func = GPIO_FUNC(0x2);
+		start = EXYNOS5_GPIO_C00;
+		start_ext = EXYNOS5_GPIO_C10;
+		gpio_func = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c2;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C20;
+		start_ext = 0;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c3;
-		bank_ext = &gpio1->c4;
-		start = 3;
-		gpio_func = GPIO_FUNC(0x3);
+		start = EXYNOS5_GPIO_C30;
+		start_ext = EXYNOS5_GPIO_C43;
+		gpio_func = S5P_GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC3:
-		bank = &gpio1->c4;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C40;
+		start_ext = 0;
 		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
 	}
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 				peripheral);
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		for (i = start_ext; i <= (start_ext + 3); i++) {
+			gpio_cfg_pin(i, gpio_func);
+			gpio_set_pull(i, S5P_GPIO_PULL_UP);
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
 	}
-	for (i = 0; i < 2; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	for (i = start; i < (start + 2); i++) {
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
-	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	for (i = (start + 3); i <= (start + 6); i++) {
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_UP);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags)
 
 static int exynos5420_mmc_config(int peripheral, int flags)
 {
-	struct exynos5420_gpio_part3 *gpio3 =
-		(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
-	struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
-	int i, start;
+	int i, start = 0, start_ext = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio3->c0;
-		bank_ext = &gpio3->c3;
-		start = 0;
+		start = EXYNOS5420_GPIO_C00;
+		start_ext = EXYNOS5420_GPIO_C30;
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio3->c1;
-		bank_ext = &gpio3->d1;
-		start = 4;
+		start = EXYNOS5420_GPIO_C10;
+		start_ext = EXYNOS5420_GPIO_D14;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio3->c2;
-		bank_ext = NULL;
-		start = 0;
+		start = EXYNOS5420_GPIO_C20;
+		start_ext = 0;
 		break;
 	default:
 		start = 0;

@@ -175,21 +150,21 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		return -1;
 	}
 
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 		      peripheral);
 		return -1;
 	}
 
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		for (i = start_ext; i <= (start_ext + 3); i++) {
+			gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+			gpio_set_pull(i, S5P_GPIO_PULL_UP);
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
 	}
 
-	for (i = 0; i < 3; i++) {
+	for (i = start; i < (start + 3); i++) {
 		/*
 		 * MMC0 is intended to be used for eMMC. The
 		 * card detect pin is used as a VDDEN signal to

@@ -197,19 +172,19 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		 * this same assumption.
 		 */
 		if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
-			s5p_gpio_set_value(bank, i, 1);
-			s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+			gpio_set_value(i, 1);
+			gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
 		} else {
-			s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+			gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 		}
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
-	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	for (i = (start + 3); i <= (start + 6); i++) {
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_UP);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 
 static void exynos5_sromc_config(int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	int i;
 
 	/*

@@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags)
 	 * GPY1[2]	SROM_WAIT(2)
 	 * GPY1[3]	EBI_DATA_RDn(2)
 	 */
-	s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
-				GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
+		     S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
 
 	for (i = 0; i < 4; i++)
-		s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
 
 	/*
 	 * EBI: 8 Addrss Lines

@@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags)
 	 * GPY6[7]	EBI_DATA[15](2)
 	 */
 	for (i = 0; i < 8; i++) {
-		s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
 	}
 }
 
 static void exynos5_i2c_config(int peripheral, int flags)
 {
-
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
 		break;
 	}
 }
 
 static void exynos5420_i2c_config(int peripheral)
 {
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C8:
-		s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C9:
-		s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C10:
-		s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
 		break;
 	}
 }

@@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral)
 static void exynos5_i2s_config(int peripheral)
 {
 	int i;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part4 *gpio4 =
-		(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
 
 	switch (peripheral) {
 	case PERIPH_ID_I2S0:
 		for (i = 0; i < 5; i++)
-			s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
 		break;
 	case PERIPH_ID_I2S1:
 		for (i = 0; i < 5; i++)
-			s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
 		break;
 	}
 }

@@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral)
 void exynos5_spi_config(int peripheral)
 {
 	int cfg = 0, pin = 0, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part2 *gpio2 =
-		(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
-		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		cfg = S5P_GPIO_FUNC(0x2);
+		pin = EXYNOS5_GPIO_A20;
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
-		cfg = GPIO_FUNC(0x2);
-		pin = 4;
+		cfg = S5P_GPIO_FUNC(0x2);
+		pin = EXYNOS5_GPIO_A24;
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
-		cfg = GPIO_FUNC(0x5);
-		pin = 1;
+		cfg = S5P_GPIO_FUNC(0x5);
+		pin = EXYNOS5_GPIO_B11;
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio2->f1;
-		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		cfg = S5P_GPIO_FUNC(0x2);
+		pin = EXYNOS5_GPIO_F10;
 		break;
 	case PERIPH_ID_SPI4:
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
 		}
 		break;
 	}
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	}
 }
 
 void exynos5420_spi_config(int peripheral)
 {
 	int cfg, pin, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct exynos5420_gpio_part4 *gpio4 =
-		(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
-		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5420_GPIO_A20;
+		cfg = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
-		cfg = GPIO_FUNC(0x2);
-		pin = 4;
+		pin = EXYNOS5420_GPIO_A24;
+		cfg = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
-		cfg = GPIO_FUNC(0x5);
-		pin = 1;
+		pin = EXYNOS5420_GPIO_B11;
+		cfg = S5P_GPIO_FUNC(0x5);
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio4->f1;
-		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5420_GPIO_F10;
+		cfg = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SPI4:
 		cfg = 0;

@@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral)
 
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	} else {
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
+				     S5P_GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
+				     S5P_GPIO_FUNC(0x4));
 		}
 	}
 }

@@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags)
 
 static void exynos4_i2c_config(int peripheral, int flags)
 {
-	struct exynos4_gpio_part1 *gpio1 =
-		(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
 		break;
 	}
 }
 
 static int exynos4_mmc_config(int peripheral, int flags)
 {
-	struct exynos4_gpio_part2 *gpio2 =
-		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-	struct s5p_gpio_bank *bank, *bank_ext;
-	int i;
+	int i, start = 0, start_ext = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio2->k0;
-		bank_ext = &gpio2->k1;
+		start = EXYNOS4_GPIO_K00;
+		start_ext = EXYNOS4_GPIO_K13;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio2->k2;
-		bank_ext = &gpio2->k3;
+		start = EXYNOS4_GPIO_K20;
+		start_ext = EXYNOS4_GPIO_K33;
 		break;
 	default:
 		return -1;
 	}
-	for (i = 0; i < 7; i++) {
-		if (i == 2)
+	for (i = start; i < (start + 7); i++) {
+		if (i == (start + 2))
 			continue;
-		s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = 3; i < 7; i++) {
-			s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		for (i = start_ext; i < (start_ext + 4); i++) {
+			gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x3));
+			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
 	}
 

@@ -666,30 +606,23 @@ static int exynos4_mmc_config(int peripheral, int flags)
 
 static void exynos4_uart_config(int peripheral)
 {
-	struct exynos4_gpio_part1 *gpio1 =
-		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS4_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->a0;
-		start = 4;
+		start = EXYNOS4_GPIO_A04;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS4_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS4_GPIO_A14;
 		count = 2;
 		break;
 	default:

@@ -697,10 +630,114 @@ static void exynos4_uart_config(int peripheral)
 		return;
 	}
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+	}
+}
+
+static void exynos4x12_i2c_config(int peripheral, int flags)
+{
+	switch (peripheral) {
+	case PERIPH_ID_I2C0:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C1:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C2:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C3:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C4:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C5:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C6:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
+		break;
+	case PERIPH_ID_I2C7:
+		gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
+		break;
 	}
 }
+
+static int exynos4x12_mmc_config(int peripheral, int flags)
+{
+	int i, start = 0, start_ext = 0;
+
+	switch (peripheral) {
+	case PERIPH_ID_SDMMC0:
+		start = EXYNOS4X12_GPIO_K00;
+		start_ext = EXYNOS4X12_GPIO_K13;
+		break;
+	case PERIPH_ID_SDMMC2:
+		start = EXYNOS4X12_GPIO_K20;
+		start_ext = EXYNOS4X12_GPIO_K33;
+		break;
+	default:
+		return -1;
+	}
+	for (i = start; i < (start + 7); i++) {
+		if (i == (start + 2))
+			continue;
+		gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
+	}
+	if (flags & PINMUX_FLAG_8BIT_MODE) {
+		for (i = start_ext; i < (start_ext + 4); i++) {
+			gpio_cfg_pin(i,  S5P_GPIO_FUNC(0x3));
+			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
+		}
+	}
+
+	return 0;
+}
+
+static void exynos4x12_uart_config(int peripheral)
+{
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		start = EXYNOS4X12_GPIO_A00;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		start = EXYNOS4X12_GPIO_A04;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		start = EXYNOS4X12_GPIO_A10;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		start = EXYNOS4X12_GPIO_A14;
+		count = 2;
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
+	}
+	for (i = start; i < start + count; i++) {
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+	}
+}
+
 static int exynos4_pinmux_config(int peripheral, int flags)
 {
 	switch (peripheral) {

@@ -736,6 +773,41 @@ static int exynos4_pinmux_config(int peripheral, int flags)
 	return 0;
 }
 
+static int exynos4x12_pinmux_config(int peripheral, int flags)
+{
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos4x12_uart_config(peripheral);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+		exynos4x12_i2c_config(peripheral, flags);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC2:
+		return exynos4x12_mmc_config(peripheral, flags);
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC3:
+	case PERIPH_ID_SDMMC4:
+		debug("SDMMC device %d not implemented\n", peripheral);
+		return -1;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	return 0;
+}
+
 int exynos_pinmux_config(int peripheral, int flags)
 {
 	if (cpu_is_exynos5()) {

@@ -744,7 +816,10 @@ int exynos_pinmux_config(int peripheral, int flags)
 		else if (proid_is_exynos5250())
 			return exynos5_pinmux_config(peripheral, flags);
 	} else if (cpu_is_exynos4()) {
-		return exynos4_pinmux_config(peripheral, flags);
+		if (proid_is_exynos4412())
+			return exynos4x12_pinmux_config(peripheral, flags);
+		else
+			return exynos4_pinmux_config(peripheral, flags);
 	} else {
 		debug("pinmux functionality not supported\n");
 	}
arch/arm/dts/exynos4210-origen.dts +2 -2
index 5c9d2ae..15059d2 100644
@@ -36,10 +36,10 @@
 	sdhci@12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0x2008002 0>;
+		cd-gpios = <&gpio 0xA2 0>;
 	};
 
 	sdhci at 12540000 {
 		status = "disabled";
 	};
-};
\ No newline at end of file
+};
arch/arm/dts/exynos4210-trats.dts +3 -3
index 992e023..0ff6939 100644
@@ -101,7 +101,7 @@
 	sdhci at 12510000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpio 0x2008002 0>;
+		pwr-gpios = <&gpio 0xA2 0>;
 	};
 
 	sdhci at 12520000 {

@@ -111,10 +111,10 @@
 	sdhci at 12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0x20c6004 0>;
+		cd-gpios = <&gpio 0x39C 0>;
 	};
 
 	sdhci at 12540000 {
 		status = "disabled";
 	};
-};
\ No newline at end of file
+};
arch/arm/dts/exynos4210-universal_c210.dts +2 -2
index 1cdd981..6941906 100644
@@ -24,7 +24,7 @@
 	sdhci at 12510000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpio 0x2008002 0>;
+		pwr-gpios = <&gpio 0xA2 0>;
 	};
 
 	sdhci at 12520000 {

@@ -34,7 +34,7 @@
 	sdhci at 12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0x20c6004 0>;
+		cd-gpios = <&gpio 0x39C 0>;
 	};
 
 	sdhci at 12540000 {
arch/arm/dts/exynos4412-trats2.dts +2 -2
index 7d32067..1596f83 100644
@@ -415,7 +415,7 @@
 	sdhci at 12510000 {
 		samsung,bus-width = <8>;
 		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpio 0x2004002 0>;
+		pwr-gpios = <&gpio 0xB2 0>;
 	};
 
 	sdhci at 12520000 {

@@ -425,7 +425,7 @@
 	sdhci at 12530000 {
 		samsung,bus-width = <4>;
 		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpio 0x20C6004 0>;
+		cd-gpios = <&gpio 0x3BC 0>;
 	};
 
 	sdhci at 12540000 {
arch/arm/include/asm/arch-exynos/cpu.h +11 -6
index fdf73b5..ba71714 100644
@@ -98,7 +98,7 @@
 #define EXYNOS5_I2C_SPACING		0x10000
 
 #define EXYNOS5_AUDIOSS_BASE		0x03810000
-#define EXYNOS5_GPIO_PART4_BASE		0x03860000
+#define EXYNOS5_GPIO_PART8_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000

@@ -108,9 +108,13 @@
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE		0x10830000
 #define EXYNOS5_DMC_PHY_BASE		0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE		0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE		0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_GPIO_PART2_BASE		0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE		0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_USB_HOST_XHCI_BASE	0x12000000
 #define EXYNOS5_USB3PHY_BASE		0x12100000

@@ -125,7 +129,7 @@
 #define EXYNOS5_I2S_BASE		0x12D60000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE		0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE		0x13400000
+#define EXYNOS5_GPIO_PART4_BASE		0x13400000
 #define EXYNOS5_FIMD_BASE		0x14400000
 #define EXYNOS5_DP_BASE			0x145B0000
 

@@ -135,7 +139,7 @@
 
 /* EXYNOS5420 */
 #define EXYNOS5420_AUDIOSS_BASE		0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE	0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE	0x03860000
 #define EXYNOS5420_PRO_ID		0x10000000
 #define EXYNOS5420_CLOCK_BASE		0x10010000
 #define EXYNOS5420_POWER_BASE		0x10040000

@@ -158,8 +162,9 @@
 #define EXYNOS5420_PWMTIMER_BASE	0x12DD0000
 #define EXYNOS5420_SPI_ISP_BASE		0x131A0000
 #define EXYNOS5420_GPIO_PART2_BASE	0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE	0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE	0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE	0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE	0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE	0x14000000
 #define EXYNOS5420_GPIO_PART1_BASE	0x14010000
 #define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
 #define EXYNOS5420_DP_BASE		0x145B0000
arch/arm/include/asm/arch-exynos/gpio.h +1474 -287

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arch/arm/include/asm/arch-s5pc1xx/gpio.h +805 -145

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board/samsung/arndale/arndale.c +4 -7
index 9efc355..ef88314 100644

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board/samsung/goni/goni.c +11 -15
index 61b9ece..60bb998 100644

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board/samsung/smdk5250/exynos5-dt.c +7 -13
index 379a45c..58821c4 100644

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board/samsung/smdk5250/smdk5250.c +7 -12
index 28a6d9e..014b7bd 100644

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board/samsung/smdk5420/smdk5420.c +6 -9
index e4606ec..fa3aa2c 100644

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board/samsung/smdkc100/smdkc100.c +1 -4
index 860c851..e009564 100644

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board/samsung/smdkv310/smdkv310.c +6 -11
index 81a3060..416d0ea 100644

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board/samsung/trats/trats.c +13 -26
index 7c79e7b..f8b2908 100644

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board/samsung/trats2/trats2.c +30 -44

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board/samsung/universal_c210/universal.c +23 -28

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drivers/gpio/s5p_gpio.c +164 -34

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Signature · 1 line
1.8.3.2

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#2 lore raw

PATCH v11 1/2 S5P: Exynos: Add GPIO pin numbering and rename definitions

Dear Akshay Saraswat,

Quoted 15 lines · Akshay Saraswat

This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

* Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation.

* Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00

Quoted 4 lines
Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>

---

please add changes log.

Quoted 26 lines
 arch/arm/cpu/armv7/exynos/pinmux.c         |  549 +++++----
 arch/arm/dts/exynos4210-origen.dts         |    4 +-
 arch/arm/dts/exynos4210-trats.dts          |    6 +-
 arch/arm/dts/exynos4210-universal_c210.dts |    4 +-
 arch/arm/dts/exynos4412-trats2.dts         |    4 +-
 arch/arm/include/asm/arch-exynos/cpu.h     |   17 +-
 arch/arm/include/asm/arch-exynos/gpio.h    | 1761 +++++++++++++++++++++++-----
 arch/arm/include/asm/arch-s5pc1xx/gpio.h   |  950 ++++++++++++---
 board/samsung/arndale/arndale.c            |   11 +-
 board/samsung/goni/goni.c                  |   26 +-
 board/samsung/smdk5250/exynos5-dt.c        |   20 +-
 board/samsung/smdk5250/smdk5250.c          |   19 +-
 board/samsung/smdk5420/smdk5420.c          |   15 +-
 board/samsung/smdkc100/smdkc100.c          |    5 +-
 board/samsung/smdkv310/smdkv310.c          |   17 +-
 board/samsung/trats/trats.c                |   39 +-
 board/samsung/trats2/trats2.c              |   74 +-
 board/samsung/universal_c210/universal.c   |   51 +-
 drivers/gpio/s5p_gpio.c                    |  198 +++-
 19 files changed, 2883 insertions(+), 887 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +0 -0
index 9edb475..9e26340 100644

arch/arm/cpu/armv7/exynos/pinmux.c static int exynos5420_mmc_config(int peripheral, int flags) · line 174

Quoted 3 lines
arch/arm/cpu/armv7/exynos/pinmux.c +0 -0
@@ -197,19 +172,19 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		 * this same assumption.
 		 */
 		if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {

Should be.. (i == start + 2)??

Quoted 43 lines
arch/arm/cpu/armv7/exynos/pinmux.c +9 -9
-			s5p_gpio_set_value(bank, i, 1);
-			s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+			gpio_set_value(i, 1);
+			gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
 		} else {
-			s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+			gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 		}
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
-	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	for (i = (start + 3); i <= (start + 6); i++) {
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_UP);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
 	return 0;
arch/arm/include/asm/arch-exynos/gpio.h +5 -9
index d6868fa..c49be8b 100644
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+static inline struct gpio_info *get_gpio_data(void)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_gpio_data;

arch/arm/include/asm/arch-exynos/gpio.h struct s5p_gpio_bank { · line 1393

Quoted 10 lines
arch/arm/include/asm/arch-exynos/gpio.h +10 -0
+		else
+			return exynos5_gpio_data;
+	} else if (cpu_is_exynos4()) {
+		if (proid_is_exynos4412())
+			return exynos4x12_gpio_data;
+		else
+			return exynos4_gpio_data;
+	} else {
+		return NULL;
+	}

else does not needed.
just return NULL;

Quoted 81 lines
arch/arm/include/asm/arch-exynos/gpio.h +5 -74
+}
 
-/* GPIO pins per bank  */
-#define GPIO_PER_BANK 8
-#define S5P_GPIO_PART_SHIFT	(24)
-#define S5P_GPIO_PART_MASK	(0xff)
-#define S5P_GPIO_BANK_SHIFT	(8)
-#define S5P_GPIO_BANK_MASK	(0xffff)
-#define S5P_GPIO_PIN_MASK	(0xff)
-
-#define S5P_GPIO_SET_PART(x) \
-			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
-
-#define S5P_GPIO_GET_PART(x) \
-			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
-
-#define S5P_GPIO_SET_PIN(x) \
-			((x) & S5P_GPIO_PIN_MASK)
-
-#define EXYNOS4_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos4_gpio_part##part *) \
-			EXYNOS4_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS4_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
-			EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS4X12_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS5_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
-			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS5_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
-			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS5420_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define exynos4_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS4_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-#define exynos4x12_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-#define exynos5420_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS5420_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-#define exynos5_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS5_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-static inline unsigned int s5p_gpio_base(int gpio)
+static inline unsigned int get_bank_num(void)
 {
-	unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
-
-	switch (gpio_part) {
-	case 1:
-		return samsung_get_base_gpio_part1();
-	case 2:
-		return samsung_get_base_gpio_part2();
-	case 3:
-		return samsung_get_base_gpio_part3();
-	case 4:
-		return samsung_get_base_gpio_part4();
-	default:
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return EXYNOS5420_GPIO_NUM_PARTS;

arch/arm/include/asm/arch-exynos/gpio.h struct s5p_gpio_bank { · line 1410

Quoted 10 lines
arch/arm/include/asm/arch-exynos/gpio.h +8 -0
+		else
+			return EXYNOS5_GPIO_NUM_PARTS;
+	} else if (cpu_is_exynos4()) {
+		if (proid_is_exynos4412())
+			return EXYNOS4X12_GPIO_NUM_PARTS;
+		else
+			return EXYNOS4_GPIO_NUM_PARTS;
+	} else {
 		return 0;
 	}

ditto.
return 0;

Quoted 5 lines

}

arch/arm/include/asm/arch-s5pc1xx/gpio.h +0 -0
index da8df74..74e9b5a 100644

arch/arm/include/asm/arch-s5pc1xx/gpio.h struct s5p_gpio_bank { · line 744

Quoted 10 lines
arch/arm/include/asm/arch-s5pc1xx/gpio.h +8 -2
-#define S5P_GPIO_SET_PIN(x) \
-			((x) & S5P_GPIO_PIN_MASK)
+static inline struct gpio_info *get_gpio_data(void)
+{
+	if (cpu_is_s5pc100())
+		return s5pc100_gpio_data;
+	else if (cpu_is_s5pc110())
+		return s5pc110_gpio_data;
+	else
+		return NULL;

ditto.

Quoted 4 lines
arch/arm/include/asm/arch-s5pc1xx/gpio.h +1 -2
+}
 
-#define S5PC100_SET_BANK(bank) \
-			(((unsigned)&(((struct s5pc100_gpio *) \

arch/arm/include/asm/arch-s5pc1xx/gpio.h struct s5p_gpio_bank { · line 754

Quoted 10 lines
arch/arm/include/asm/arch-s5pc1xx/gpio.h +8 -2
-			S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+static inline unsigned int get_bank_num(void)
+{
+	if (cpu_is_s5pc100())
+		return S5PC100_GPIO_NUM_PARTS;
+	else if (cpu_is_s5pc110())
+		return S5PC110_GPIO_NUM_PARTS;
+	else
+		return 0;

ditto.

Quoted 38 lines
arch/arm/include/asm/arch-s5pc1xx/gpio.h +1 -4
+}
 
-#define S5PC110_SET_BANK(bank) \
-			((((unsigned)&(((struct s5pc110_gpio *) \
-			S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
board/samsung/goni/goni.c +1 -5
index 61b9ece..60bb998 100644
@@ -17,8 +17,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct s5pc110_gpio *s5pc110_gpio;
-
 u32 get_board_rev(void)
 {
 	return 0;

@@ -27,8 +25,6 @@ u32 get_board_rev(void)
 int board_init(void)
 {
 	/* Set Initial global variables */
-	s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
-
 	gd->bd->bi_arch_number = MACH_TYPE_GONI;
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 

@@ -82,7 +78,7 @@ int board_mmc_init(bd_t *bis)
 	int i, ret, ret_sd = 0;
 
 	/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
-	s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
+	gpio_direction_output(S5PC110_GPIO_J27, 1);
 
 	/*
 	 * MMC0 GPIO

board/samsung/goni/goni.c int board_mmc_init(bd_t *bis) · line 91

Quoted 6 lines
board/samsung/goni/goni.c +1 -1
@@ -91,15 +87,15 @@ int board_mmc_init(bd_t *bis)
 	 * GPG0[2]	SD_0_CDn	-> Not used
 	 * GPG0[3:6]	SD_0_DATA[0:3]
 	 */
-	for (i = 0; i < 7; i++) {
+	for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) {
 		if (i == 2)

if (i == S5PC110_GPIO_G02)

Quoted 15 lines
board/samsung/goni/goni.c +3 -3
 			continue;
 		/* GPG0[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
+		gpio_cfg_pin(i, 0x2);
 		/* GPG0[0:6] pull disable */
-		s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 		/* GPG0[0:6] drv 4x */
-		s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
 	ret = s5p_mmc_init(0, 4);

@@ -110,20 +106,20 @@ int board_mmc_init(bd_t *bis)
 	 * SD card (T_FLASH) detect and init

board/samsung/goni/goni.c int board_mmc_init(bd_t *bis) · line 113

Quoted 10 lines
board/samsung/goni/goni.c +3 -3
 	 * T_FLASH_DETECT: EINT28: GPH3[4] input mode
 	 */
-	s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
-	s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
+	gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT);
+	gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP);
 
-	if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
+	if (!gpio_get_value(S5PC110_GPIO_H34)) {
 		for (i = 0; i < 7; i++) {

for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++)

board/samsung/goni/goni.c int board_mmc_init(bd_t *bis) · line 114

Quoted 1 line
board/samsung/goni/goni.c +0 -0
 			if (i == 2)

i == S5PC110_GPIO_G22

Quoted 51 lines
board/samsung/goni/goni.c +3 -3
 				continue;
 
 			/* GPG2[0:6] special function 2 */
-			s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
+			gpio_cfg_pin(S5PC110_GPIO_G20 + i, 0x2);
 			/* GPG2[0:6] pull disable */
-			s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
+			gpio_set_pull(S5PC110_GPIO_G20 + i, S5P_GPIO_PULL_NONE);
 			/* GPG2[0:6] drv 4x */
-			s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
+			gpio_set_drv(S5PC110_GPIO_G20 + i, S5P_GPIO_DRV_4X);
 		}
 
 		ret_sd = s5p_mmc_init(2, 4);
board/samsung/smdkv310/smdkv310.c +2 -7
index 81a3060..416d0ea 100644
@@ -15,15 +15,13 @@
 #include <asm/arch/sromc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
 
 static void smc9115_pre_init(void)
 {
 	u32 smc_bw_conf, smc_bc_conf;
 
 	/* gpio configuration GPK0CON */
-	s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
 
 	/* Ethernet needs bus width of 16 bits */
 	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);

@@ -38,9 +36,6 @@ static void smc9115_pre_init(void)
 
 int board_init(void)
 {
-	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
-	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
 	smc9115_pre_init();
 
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);

@@ -103,21 +98,21 @@ int board_mmc_init(bd_t *bis)
 	 * GPK2[2]	SD_2_CDn
 	 * GPK2[3:6]	SD_2_DATA[0:3](2)
 	 */
-	for (i = 0; i < 7; i++) {
+	for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {

board/samsung/smdkv310/smdkv310.c int board_mmc_init(bd_t *bis) · line 109

Quoted 10 lines
board/samsung/smdkv310/smdkv310.c +2 -2
 		/* GPK2[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 
 		/* GPK2[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 
 		/* GPK2[0:1] pull disable */
 		if (i == 0 || i == 1) {

(i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21)

Quoted 59 lines
board/samsung/smdkv310/smdkv310.c +2 -2
-			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 			continue;
 		}
 
 		/* GPK2[2:6] pull up */
-		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+		gpio_set_pull(i, S5P_GPIO_PULL_UP);
 	}
 	err = s5p_mmc_init(2, 4);
 	return err;
board/samsung/universal_c210/universal.c +13 -15
index f9d71b6..9a2bd45 100644
@@ -27,8 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
 unsigned int board_rev;
 
 u32 get_board_rev(void)

@@ -312,35 +310,35 @@ void exynos_cfg_lcd_gpio(void)
 
 	for (i = 0; i < 8; i++) {
 		/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
-		s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
-		s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
-		s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
 		/* pull-up/down disable */
-		s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
-		s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
-		s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+		gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
+		gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
+		gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
 
 		/* drive strength to max (24bit) */
-		s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
-		s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
-		s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+		gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
+		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
+		gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
+		gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
+		gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
+		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
 	}
 
-	for (i = 0; i < f3_end; i++) {
+	for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {

board/samsung/universal_c210/universal.c void exynos_cfg_lcd_gpio(void) · line 336

Quoted 10 lines
board/samsung/universal_c210/universal.c +3 -4
 		/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
-		s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
 		/* pull-up/down disable */
-		s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
 		/* drive strength to max (24bit) */
-		s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+

missing set the drv?

Quoted 34 lines
board/samsung/universal_c210/universal.c +2 -1
+		gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
 	}
 
 	/* gpio pad configuration for LCD reset. */
-	s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+	gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
 
 	spi_init();
 }
drivers/gpio/s5p_gpio.c +4 -5
index 11a0472..49e99cb 100644
@@ -8,11 +8,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <asm/arch/gpio.h>
 
-#define S5P_GPIO_GET_BANK(x)	((x >> S5P_GPIO_BANK_SHIFT) \
-				& S5P_GPIO_BANK_MASK)
-
-#define S5P_GPIO_GET_PIN(x)	(x & S5P_GPIO_PIN_MASK)
+#define S5P_GPIO_GET_PIN(x)	(x % GPIO_PER_BANK)
 
 #define CON_MASK(x)		(0xf << ((x) << 2))
 #define CON_SFR(x, v)		((v) << ((x) << 2))

@@ -28,7 +26,100 @@
 #define RATE_MASK(x)		(0x1 << (x + 16))
 #define RATE_SET(x)		(0x1 << (x + 16))
 
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
+#define name_to_gpio(n) s5p_name_to_gpio(n)
+static inline int s5p_name_to_gpio(const char *name)

drivers/gpio/s5p_gpio.c line 40

Quoted 10 lines
drivers/gpio/s5p_gpio.c +10 -0
+{
+	unsigned num, irregular_set_number, irregular_bank_base;
+	const struct gpio_name_num_table *tabp;
+	char this_bank, bank_name, irregular_bank_name;
+	char *endp;
+
+	/*
+	 * The gpio name starts with either 'g' ot 'gp' followed by the bank
+	 * name character. Skip one or two characters depending on the prefix.
+	 */

so, why don't you check name[0]?

drivers/gpio/s5p_gpio.c line 45

Quoted 5 lines
drivers/gpio/s5p_gpio.c +5 -0
+	if (name[1] == 'p')
+		name += 2;
+	else
+		name++;
+	bank_name = *name++;

I think you should check the address (the name) before you access.

Quoted 194 lines
drivers/gpio/s5p_gpio.c +103 -27
+	if (!*name)
+		return -1; /* At least one digit is required/expected. */
+
+	/*
+	 * On both exynos5 and exynos5420 architectures there is a bank of
+	 * GPIOs which does not fall into the regular address pattern. Those
+	 * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
+	 * assignments help to handle these irregularities.
+	 */
+#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420()) {
+			tabp = exynos5420_gpio_table;
+			irregular_bank_name = 'y';
+			irregular_set_number = '7';
+			irregular_bank_base = EXYNOS5420_GPIO_Y70;
+		} else {
+			tabp = exynos5_gpio_table;
+			irregular_bank_name = 'c';
+			irregular_set_number = '4';
+			irregular_bank_base = EXYNOS5_GPIO_C40;
+		}
+	} else {
+		if (proid_is_exynos4412())
+			tabp = exynos4x12_gpio_table;
+		else
+			tabp = exynos4_gpio_table;
+		irregular_bank_name = 0;
+		irregular_set_number = 0;
+		irregular_bank_base = 0;
+	}
+#else
+	if (cpu_is_s5pc110())
+		tabp = s5pc110_gpio_table;
+	else
+		tabp = s5pc100_gpio_table;
+	irregular_bank_name = 0;
+	irregular_set_number = 0;
+	irregular_bank_base = 0;
+#endif
+
+	this_bank = tabp->bank;
+	do {
+		if (bank_name == this_bank) {
+			unsigned pin_index; /* pin number within the bank */
+			if ((bank_name == irregular_bank_name) &&
+			    (name[0] == irregular_set_number)) {
+				pin_index = name[1] - '0';
+				/* Irregular sets have 8 pins. */
+				if (pin_index >= GPIO_PER_BANK)
+					return -1;
+				num = irregular_bank_base + pin_index;
+			} else {
+				pin_index = simple_strtoul(name, &endp, 8);
+				pin_index -= tabp->bank_offset;
+				/*
+				 * Sanity check: bunk 'z' has no set number,
+				 * for all other banks there must be exactly
+				 * two octal digits, and the resulting number
+				 * should not exceed the number of pins in the
+				 * bank.
+				 */
+				if (((bank_name != 'z') && !name[1]) ||
+				    *endp ||
+				    (pin_index >= tabp->bank_size))
+					return -1;
+				num = tabp->base + pin_index;
+			}
+			return num;
+		}
+		this_bank = (++tabp)->bank;
+	} while (this_bank);
+
+	return -1;
+}
+
+static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 {
 	unsigned int value;
 

@@ -38,18 +129,7 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 	writel(value, &bank->con);
 }
 
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
-{
-	s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
-	s5p_gpio_set_value(bank, gpio, en);
-}
-
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
-{
-	s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT);
-}
-
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
+static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
 {
 	unsigned int value;
 

@@ -60,7 +140,19 @@ void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
 	writel(value, &bank->dat);
 }
 
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
+static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
+				      int gpio, int en)
+{
+	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
+	s5p_gpio_set_value(bank, gpio, en);
+}
+
+static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
+{
+	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
+}
+
+static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
 {
 	unsigned int value;
 

@@ -68,7 +160,7 @@ unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
 	return !!(value & DAT_MASK(gpio));
 }
 
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
+static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 {
 	unsigned int value;
 

@@ -76,8 +168,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~PULL_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_PULL_DOWN:
-	case GPIO_PULL_UP:
+	case S5P_GPIO_PULL_DOWN:
+	case S5P_GPIO_PULL_UP:
 		value |= PULL_MODE(gpio, mode);
 		break;
 	default:

@@ -87,7 +179,7 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 	writel(value, &bank->pull);
 }
 
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
+static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
 {
 	unsigned int value;
 

@@ -95,10 +187,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~DRV_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_DRV_1X:
-	case GPIO_DRV_2X:
-	case GPIO_DRV_3X:
-	case GPIO_DRV_4X:
+	case S5P_GPIO_DRV_1X:
+	case S5P_GPIO_DRV_2X:
+	case S5P_GPIO_DRV_3X:
+	case S5P_GPIO_DRV_4X:
 		value |= DRV_SET(gpio, mode);
 		break;
 	default:

@@ -108,7 +200,7 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
 	writel(value, &bank->drv);
 }
 
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
+static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 {
 	unsigned int value;
 

@@ -116,8 +208,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~RATE_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_DRV_FAST:
-	case GPIO_DRV_SLOW:
+	case S5P_GPIO_DRV_FAST:
+	case S5P_GPIO_DRV_SLOW:
 		value |= RATE_SET(gpio);
 		break;
 	default:

@@ -127,12 +219,26 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 	writel(value, &bank->drv);
 }
 
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
 {
-	unsigned bank = S5P_GPIO_GET_BANK(gpio);
-	unsigned base = s5p_gpio_base(gpio);

drivers/gpio/s5p_gpio.c void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) · line 231

Quoted 10 lines
drivers/gpio/s5p_gpio.c +8 -2
-
-	return (struct s5p_gpio_bank *)(base + bank);
+	const struct gpio_info *data;
+	unsigned int upto;
+	int i, count;
+
+	data = get_gpio_data();
+	count = get_bank_num();
+	for (i = upto = 0; i < count;
+			i++, upto = data->max_gpio, data++) {

Could you please move upto = 0, upto = data->max_gpio, data++ to somewhere for code readability? please make simple for statement.
for (i = upto; i <count; i++)

Quoted 32 lines
drivers/gpio/s5p_gpio.c +24 -0
+		debug("i=%d, upto=%d\n", i, upto);
+		if (gpio < data->max_gpio) {
+			struct s5p_gpio_bank *bank;
+			bank = (struct s5p_gpio_bank *)data->reg_addr;
+			bank += (gpio - upto) / GPIO_PER_BANK;
+			debug("gpio=%d, bank=%p\n", gpio, bank);
+			return bank;
+		}
+	}
+	return NULL;
 }
 
 int s5p_gpio_get_pin(unsigned gpio)

@@ -179,3 +285,27 @@ int gpio_set_value(unsigned gpio, int value)
 
 	return 0;
 }
+
+void gpio_set_pull(int gpio, int mode)
+{
+	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+			  s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)
+{
+	s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+			 s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)

drivers/gpio/s5p_gpio.c int gpio_set_value(unsigned gpio, int value) · line 311

Quoted 10 lines
drivers/gpio/s5p_gpio.c +10 -0
+{
+	s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+			 s5p_gpio_get_pin(gpio), cfg);
+}
+
+void gpio_set_rate(int gpio, int mode)
+{
+	s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
+			  s5p_gpio_get_pin(gpio), mode);
+}

Thanks,
Minkyu Kang.

author
#3 lore raw

PATCH v11 2/2 S5P: Exynos: Config: Enable GPIO CMD config

In reply to Akshay Saraswat

Enabling configs for GPIO CMD, EXYNOS4 family and replacing exynos_gpio_get with new linear GPIO pin number required because of the new function asking only 2 arguments (pin and value) instead of 3 (bank, pin and value).

Signed-off-by Akshay Saraswat <[email protected]>
---
 include/configs/exynos5-dt.h        |  2 ++
 include/configs/s5p_goni.h          |  4 ++--
 include/configs/s5pc210_universal.h | 16 ++++++++--------
 include/configs/smdkv310.h          |  1 +
 include/configs/trats.h             |  8 ++++----
 include/configs/trats2.h            |  4 ++--
 6 files changed, 19 insertions(+), 16 deletions(-)
include/configs/exynos5-dt.h +2 -0
index 414db42..5a9b1b4 100644
@@ -288,4 +288,6 @@
 
 #define CONFIG_CMD_BOOTZ
 
+#define CONFIG_CMD_GPIO
+
 #endif	/* __CONFIG_H */
include/configs/s5p_goni.h +2 -2
index 991c43e..799d4fe 100644
@@ -214,8 +214,8 @@
 /*
  * I2C Settings
  */
-#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3)
-#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL S5PC110_GPIO_J43
+#define CONFIG_SOFT_I2C_GPIO_SDA S5PC110_GPIO_J40
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
include/configs/s5pc210_universal.h +8 -8
index 2da8871..b368266 100644
@@ -170,8 +170,8 @@
 /*
  * I2C Settings
  */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
+#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7
+#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6
 
 #define CONFIG_CMD_I2C
 

@@ -196,10 +196,10 @@
  */
 #define CONFIG_SOFT_SPI
 #define CONFIG_SOFT_SPI_MODE SPI_MODE_3
-#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1)
-#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3)
-#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0)
-#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3)
+#define CONFIG_SOFT_SPI_GPIO_SCLK EXYNOS4_GPIO_Y31
+#define CONFIG_SOFT_SPI_GPIO_MOSI EXYNOS4_GPIO_Y33
+#define CONFIG_SOFT_SPI_GPIO_MISO EXYNOS4_GPIO_Y30
+#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43
 
 #define SPI_DELAY udelay(1)
 #undef SPI_INIT

@@ -231,8 +231,8 @@ int universal_spi_read(void);
 #define KEY_PWR_INTERRUPT_REG		MAX8998_REG_IRQ1
 #define KEY_PWR_INTERRUPT_MASK		(1 << 7)
 
-#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
-#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
+#define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
 #endif /* __ASSEMBLY__ */
 
 /* LCD console */
include/configs/smdkv310.h +1 -0
index 1388f49..34adfaf 100644
@@ -12,6 +12,7 @@
 /* High Level Configuration Options */
 #define CONFIG_SAMSUNG			1	/* in a SAMSUNG core */
 #define CONFIG_S5P			1	/* S5P Family */
+#define CONFIG_EXYNOS4				/* EXYNOS4 Family */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
 #define CONFIG_SMDKV310			1	/* working with SMDKV310*/
include/configs/trats.h +4 -4
index 5d8bd60..6cade07 100644
@@ -207,8 +207,8 @@
 #define CONFIG_SYS_I2C_INIT_BOARD
 
 /* I2C FG */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
+#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
+#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40
 
 /* POWER */
 #define CONFIG_POWER

@@ -245,8 +245,8 @@
 #define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
 #define KEY_PWR_INTERRUPT_MASK		(1 << 0)
 
-#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
-#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
+#define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
 #endif /* __ASSEMBLY__ */
 
 /* LCD console */
include/configs/trats2.h +2 -2
index 53d449c..856c03b 100644
@@ -227,8 +227,8 @@ int get_soft_i2c_sda_pin(void);
 #define KEY_PWR_INTERRUPT_REG		MAX77686_REG_PMIC_INT1
 #define KEY_PWR_INTERRUPT_MASK		(1 << 1)
 
-#define KEY_VOL_UP_GPIO			exynos4x12_gpio_get(2, x2, 2)
-#define KEY_VOL_DOWN_GPIO		exynos4x12_gpio_get(2, x3, 3)
+#define KEY_VOL_UP_GPIO			EXYNOS4X12_GPIO_X22
+#define KEY_VOL_DOWN_GPIO		EXYNOS4X12_GPIO_X33
 #endif /* __ASSEMBLY__ */
 
 /* LCD console */
Signature · 1 line
1.8.3.2
#4 lore raw

v11 cover S5P: Exynos: Add GPIO numbering feature

In reply to Akshay Saraswat

Hello Akshay,

Quoted 74 lines · Akshay Saraswat

Used a script to recheck/verify pin mapping and existing mapping appears to be fine, returning correct bank and pin values. Did ./MAKEALL -a arm and found all Exynos/S5P related boards compiled successfully.
Couldn't test booting over all of them.
Tested U-Boot bootup over SMDK5420, SMDK5250, Snow. Requesting maintaners to please test over affected SoCs/boards.

Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass
and supported same for EXYNOS5.
Changes in V3:
- New patch added to rename S5P GPIO definitions
to S5P_GPIO.
- GPIO Table added to calculate the base address
of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver.
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Rebased on latest u-boot-samsung tree.
- Removed Exynos5 specific code in gpio driver api to get bank.
- Added #define HAVE_GENERIC_GPIO in config file
to remove conditinal CPU check in gpio driver.
Changes in V6:
- Isolated config changes in a new patch.
- Updated patches with corresponding changes for Exynos 5420.
Changes in V7:
- Added changes for other SoCs like Exynos 4412, 4210 etc.
Changes in V8:
- Changed Subject of patch 2/2 to reflect affected SoCs/boards.
- Fixed arndale board compile time errors introduced due to patch-set v7.
Changes in V9:
- Fixed checkpatch errors.
- Fixed naming error in exynosxxxx_gpio_data arrays which could be the possible reason behind data abort witnessed over Exynos4 boards.
Changes in v10:
- Made arch-exynos/gpio.h -> arch/gpio.h.
- Removed dead code.
- Replaced exynos_gpio_get calls with corresponding pin number.
- Edited pin numbmers in dts files.
Changes in v11:
- Created and fixed pinmux config for Exynos 4412.
- Removed dead code.

Akshay Saraswat (2):
S5P: Exynos: Add GPIO pin numbering and rename definitions
S5P: Exynos: Config: Enable GPIO CMD config

  arch/arm/cpu/armv7/exynos/pinmux.c         |  549 +++++----
  arch/arm/dts/exynos4210-origen.dts         |    4 +-
  arch/arm/dts/exynos4210-trats.dts          |    6 +-
  arch/arm/dts/exynos4210-universal_c210.dts |    4 +-
  arch/arm/dts/exynos4412-trats2.dts         |    4 +-
  arch/arm/include/asm/arch-exynos/cpu.h     |   17 +-
  arch/arm/include/asm/arch-exynos/gpio.h    | 1761 +++++++++++++++++++++++-----
  arch/arm/include/asm/arch-s5pc1xx/gpio.h   |  945 ++++++++++++---
  board/samsung/arndale/arndale.c            |   11 +-
  board/samsung/goni/goni.c                  |   26 +-
  board/samsung/smdk5250/exynos5-dt.c        |   20 +-
  board/samsung/smdk5250/smdk5250.c          |   19 +-
  board/samsung/smdk5420/smdk5420.c          |   15 +-
  board/samsung/smdkc100/smdkc100.c          |    5 +-
  board/samsung/smdkv310/smdkv310.c          |   17 +-
  board/samsung/trats/trats.c                |   39 +-
  board/samsung/trats2/trats2.c              |   74 +-
  board/samsung/universal_c210/universal.c   |   51 +-
Quoted 9 lines
  drivers/gpio/s5p_gpio.c                    |  198 +++-
  include/configs/exynos5-dt.h               |    2 +
  include/configs/s5p_goni.h                 |    4 +-
  include/configs/s5pc210_universal.h        |   16 +-
  include/configs/smdkv310.h                 |    1 +
  include/configs/trats.h                    |    8 +-
  include/configs/trats2.h                   |    4 +-
  25 files changed, 2902 insertions(+), 898 deletions(-)

This patch set was tested on: goni, universal, trats and trats2 - works fine.

Acked-by Przemyslaw Marczak <[email protected]>

Thanks you

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com