USB support for DRA7-evm

PATCH In review Roger Quadros 10 participants 24 messages May 5, 2014 – Jul 3, 2014 7 messages not in the archive

Subsystems (6)

Device tree bindings Arm (32-bit) Arm sub-architectures OMAP2+ support +2 more subsystems

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Roger Quadros

author

2014-05-05 09:54 UTC #0 lore raw

v3 cover USB support for DRA7-evm

Hi,

This series enables the 2 USB ports on the DRA7-evm.

NOTE: USB1 port is hard coded to work in peripheral mode and USB2 port in host mode. This is due to missing ID pin interrupt in pre ver.E boards.

USB1 port doesn't in peripheral mode out of the box due to missing VBUS detection and mailbox write. To test this I had to do a manual write to enable VBUSVALID in the USB_UTMI_OTG_STATUS register.

	omapconf set bit 0x48880084 1

USB2 port works well in host mode.

Patches are based on 3.15-rc3.

cheers,
-roger

Changelog:

v3:
-Rearraged patches. PHY related stuff first. -Addressed backward compatibility issue for phy-omap-usb2.

v2:
-Rebased on v3.15-rc3

---
Roger Quadros (7):
phy: omap-usb2: Use generic clock names "wkupclk" and "refclk"
phy: omap-usb2: Add clock names to Documentation binding
ARM: dts: omap4+: Add clocks to USB2 PHY node
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
ARM: dts: dra7: Add USB related nodes
dts: dra7-evm: add USB support

 Documentation/devicetree/bindings/phy/ti-phy.txt |   7 ++
 arch/arm/boot/dts/dra7-evm.dts                   |  24 ++++
 arch/arm/boot/dts/dra7.dtsi                      | 149 +++++++++++++++++++++++
 arch/arm/boot/dts/dra7xx-clocks.dtsi             |  12 +-
 arch/arm/boot/dts/omap4.dtsi                     |   2 +
 arch/arm/boot/dts/omap5.dtsi                     |   2 +
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c        |  22 ++--
 drivers/phy/phy-omap-usb2.c                      |  30 +++--
 8 files changed, 229 insertions(+), 19 deletions(-)

Signature · 6 lines

1.8.3.2

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Roger Quadros

author

2014-05-05 09:54 UTC #2 lore raw

PATCH v3 1/7 phy: omap-usb2: Use generic clock names "wkupclk" and "refclk"

As clocks might be named differently on multiple platforms, use a generic name in the driver and allow device tree node to specify the platform specific clock name.

Signed-off-by Roger Quadros <[email protected]>

---
 drivers/phy/phy-omap-usb2.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

drivers/phy/phy-omap-usb2.c +23 -7

index a2205a8..7007c11 100644
@@ -275,18 +275,34 @@ static int omap_usb2_probe(struct platform_device *pdev)
 	if (IS_ERR(phy_provider))
 		return PTR_ERR(phy_provider);
 
-	phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
+	phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
 	if (IS_ERR(phy->wkupclk)) {
-		dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
-		return PTR_ERR(phy->wkupclk);
+		dev_warn(&pdev->dev, "unable to get wkupclk, trying old name\n");
+		phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
+		if (IS_ERR(phy->wkupclk)) {
+			dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
+			return PTR_ERR(phy->wkupclk);
+		} else {
+			dev_warn(&pdev->dev,
+				 "found usb_phy_cm_clk32k, please fix DTS\n");
+		}
 	}
 	clk_prepare(phy->wkupclk);
 
-	phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
-	if (IS_ERR(phy->optclk))
-		dev_vdbg(&pdev->dev, "unable to get refclk960m\n");
-	else
+	phy->optclk = devm_clk_get(phy->dev, "refclk");
+	if (IS_ERR(phy->optclk)) {
+		dev_dbg(&pdev->dev, "unable to get refclk, trying old name\n");
+		phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
+		if (IS_ERR(phy->optclk)) {
+			dev_dbg(&pdev->dev,
+				"unable to get usb_otg_ss_refclk960m\n");
+		} else {
+			dev_warn(&pdev->dev,
+				 "found usb_otg_ss_refclk960m, please fix DTS\n");
+		}
+	} else {
 		clk_prepare(phy->optclk);
+	}
 
 	usb_add_phy_dev(&phy->phy);

Signature · 6 lines

1.8.3.2

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Felipe Balbi

Reviewed-by

2014-05-05 18:14 UTC #4 lore raw

Re: [PATCH v3 1/7] phy: omap-usb2: Use generic clock names "wkupclk" and "refclk"

Quoted 5 lines · Roger Quadros

As clocks might be named differently on multiple platforms, use a generic name in the driver and allow device tree node to specify the platform specific clock name.
Signed-off-by Roger Quadros <[email protected]>

Reviewed-by Felipe Balbi <[email protected]>

Quoted 53 lines

---
 drivers/phy/phy-omap-usb2.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

drivers/phy/phy-omap-usb2.c +23 -7

index a2205a8..7007c11 100644
@@ -275,18 +275,34 @@ static int omap_usb2_probe(struct platform_device *pdev)
 	if (IS_ERR(phy_provider))
 		return PTR_ERR(phy_provider);
 
-	phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
+	phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
 	if (IS_ERR(phy->wkupclk)) {
-		dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
-		return PTR_ERR(phy->wkupclk);
+		dev_warn(&pdev->dev, "unable to get wkupclk, trying old name\n");
+		phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
+		if (IS_ERR(phy->wkupclk)) {
+			dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
+			return PTR_ERR(phy->wkupclk);
+		} else {
+			dev_warn(&pdev->dev,
+				 "found usb_phy_cm_clk32k, please fix DTS\n");
+		}
 	}
 	clk_prepare(phy->wkupclk);
 
-	phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
-	if (IS_ERR(phy->optclk))
-		dev_vdbg(&pdev->dev, "unable to get refclk960m\n");
-	else
+	phy->optclk = devm_clk_get(phy->dev, "refclk");
+	if (IS_ERR(phy->optclk)) {
+		dev_dbg(&pdev->dev, "unable to get refclk, trying old name\n");
+		phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
+		if (IS_ERR(phy->optclk)) {
+			dev_dbg(&pdev->dev,
+				"unable to get usb_otg_ss_refclk960m\n");
+		} else {
+			dev_warn(&pdev->dev,
+				 "found usb_otg_ss_refclk960m, please fix DTS\n");
+		}
+	} else {
 		clk_prepare(phy->optclk);
+	}
 
 	usb_add_phy_dev(&phy->phy);

Signature · 1 line

1.8.3.2

Signature · 1 line

balbi

Roger Quadros

author

2014-05-05 09:54 UTC #5 lore raw

PATCH v3 3/7 ARM: dts: omap4+: Add clocks to USB2 PHY node

In reply to a message not in the archive

The USB2 PHY driver expects named clocks for wakeup clock and reference clock. Provide this information for USB2 PHY nodes in OMAP4 and OMAP5 SoC DTS.

CC Benoît Cousson <bcousson-rdvid1DuHRBWk0Htik3J/[email protected]>

Reviewed-by Felipe Balbi <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi | 2 ++
 arch/arm/boot/dts/omap5.dtsi | 2 ++
 2 files changed, 4 insertions(+)

arch/arm/boot/dts/omap4.dtsi +2 -0

index 649b5cd..f866de9 100644
@@ -642,6 +642,8 @@
 				compatible = "ti,omap-usb2";
 				reg = <0x4a0ad080 0x58>;
 				ctrl-module = <&omap_control_usb2phy>;
+				clocks = <&usb_phy_cm_clk32k>;
+				clock-names = "wkupclk";
 				#phy-cells = <0>;
 			};
 		};

arch/arm/boot/dts/omap5.dtsi +2 -0

index f8c9855..47b714c 100644
@@ -803,6 +803,8 @@
 				compatible = "ti,omap-usb2";
 				reg = <0x4a084000 0x7c>;
 				ctrl-module = <&omap_control_usb2phy>;
+				clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
+				clock-names = "wkupclk", "refclk";
 				#phy-cells = <0>;
 			};

Signature · 6 lines

1.8.3.2

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Roger Quadros

author

2014-05-05 09:54 UTC #6 lore raw

PATCH v3 5/7 ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

In reply to a message not in the archive

Add the sysconfig class bits for the Super Speed USB controllers

CC Paul Walmsley <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +12 -0

index 810c205..067d322 100644
@@ -1731,8 +1731,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
 	.name	= "usb_otg_ss",
+	.sysc	= &dra7xx_usb_otg_ss_sysc,
 };
 
 /* usb_otg_ss1 */

Signature · 6 lines

1.8.3.2

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Paul Walmsley

maintainer

2014-06-13 19:08 UTC #7 lore raw

Re: [PATCH v3 5/7] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

Hi Roger,

Quoted 5 lines · Roger Quadros

Add the sysconfig class bits for the Super Speed USB controllers
CC Paul Walmsley <[email protected]>
Signed-off-by Roger Quadros <[email protected]>

As with the previous DRA7 hwmod patch, I'd like to get a Reviewed-by: and a Tested-by: before merging this one.

- Paul

Roger Quadros

2014-06-18 11:10 UTC #8 lore raw

Re: [PATCH v3 5/7] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

In reply to Roger Quadros

+ Nishant and Rajendra for review.

Quoted 35 lines · Roger Quadros

Add the sysconfig class bits for the Super Speed USB controllers

CC Paul Walmsley <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +12 -0

index 810c205..067d322 100644
@@ -1731,8 +1731,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
 	.name	= "usb_otg_ss",
+	.sysc	= &dra7xx_usb_otg_ss_sysc,
 };
 
 /* usb_otg_ss1 */

Rajendra Nayak

Reviewed-by

2014-06-18 11:19 UTC #9 lore raw

Re: [PATCH v3 5/7] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

Quoted 8 lines · Roger Quadros

+ Nishant and Rajendra for review.
Quoted 5 lines · Roger Quadros
Add the sysconfig class bits for the Super Speed USB controllers
CC Paul Walmsley <[email protected]>
Signed-off-by Roger Quadros <[email protected]>

verified against TRM version vP, looks good to me.

Reviewed-by Rajendra Nayak <[email protected]>

Quoted 31 lines

Quoted 30 lines

---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +12 -0

index 810c205..067d322 100644
@@ -1731,8 +1731,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
 	.name	= "usb_otg_ss",
+	.sysc	= &dra7xx_usb_otg_ss_sysc,
 };
 
 /* usb_otg_ss1 */

A message that is not in the archive (sent off-list or not yet received): [email protected]

Roger Quadros

author Tested-by

2014-06-18 11:24 UTC #11 lore raw

Re: [PATCH v3 5/7] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

Quoted 4 lines · Rajendra Nayak

Quoted 3 lines · Roger Quadros
+ Nishant and Rajendra for review.
On 05/05/2014 12:54 PM, Roger Quadros wrote:

Quoted 8 lines

Quoted 5 lines
Quoted 5 lines
Add the sysconfig class bits for the Super Speed USB controllers
CC Paul Walmsley <[email protected]>
Signed-off-by Roger Quadros <[email protected]>
verified against TRM version vP, looks good to me.
Reviewed-by Rajendra Nayak <[email protected]>

Tested-by Roger Quadros <[email protected]>

against 3.16-rc1. no dependency patches.

cheers,
-roger

Quoted 29 lines

---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +12 -0

index 810c205..067d322 100644
@@ -1731,8 +1731,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
 	.name	= "usb_otg_ss",
+	.sysc	= &dra7xx_usb_otg_ss_sysc,
 };

Quoted 4 lines

Quoted 3 lines
arch/arm/mach-omap2/omap_hwmod_7xx_data.c static struct omap_hwmod dra7xx_uart6_hwmod = { · line 1750
Quoted 2 lines
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +0 -0
 /* usb_otg_ss1 */

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Roger Quadros

2014-07-02 11:26 UTC #12 lore raw

Re: [PATCH v3 5/7] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

In reply to Rajendra Nayak

Sekhar,

Quoted 4 lines · Rajendra Nayak

Quoted 3 lines · Roger Quadros
+ Nishant and Rajendra for review.
On 05/05/2014 12:54 PM, Roger Quadros wrote:

Quoted 8 lines

Quoted 5 lines
Quoted 5 lines
Add the sysconfig class bits for the Super Speed USB controllers
CC Paul Walmsley <[email protected]>
Signed-off-by Roger Quadros <[email protected]>
verified against TRM version vP, looks good to me.
Reviewed-by Rajendra Nayak <[email protected]>

Could you please give your Tested-by tag for this? Then we can take this into 3.16-rc. Thanks.

cheers,
-roger

Quoted 33 lines

Quoted 32 lines

Quoted 31 lines

---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +12 -0

index 810c205..067d322 100644
@@ -1731,8 +1731,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
  *
  */
 
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+			   SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
 	.name	= "usb_otg_ss",
+	.sysc	= &dra7xx_usb_otg_ss_sysc,
 };
 
 /* usb_otg_ss1 */

Sekhar Nori

Tested-by

2014-07-03 10:42 UTC #13 lore raw

Re: [PATCH v3 5/7] ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss

Quoted 10 lines · Roger Quadros

Sekhar,
Quoted 7 lines · Rajendra Nayak
Quoted 6 lines · Roger Quadros
+ Nishant and Rajendra for review.
Quoted 3 lines · Roger Quadros
Add the sysconfig class bits for the Super Speed USB controllers

Quoted 7 lines

Quoted 5 lines
Quoted 2 lines
Quoted 2 lines
CC Paul Walmsley <[email protected]>
Signed-off-by Roger Quadros <[email protected]>
verified against TRM version vP, looks good to me.
Reviewed-by Rajendra Nayak <[email protected]>
Could you please give your Tested-by tag for this? Then we can take this into 3.16-rc.

Boot tested on my DRA7x EVM.

Boot log here: http://paste.ubuntu.com/7741337/

Tested-by Sekhar Nori <[email protected]>

Thanks,
Sekhar

Roger Quadros

author

2014-05-05 09:54 UTC #14 lore raw

PATCH v3 6/7 ARM: dts: dra7: Add USB related nodes

In reply to a message not in the archive

Add nodes for the Super Speed USB controllers, omap-control-usb, USB2 PHY and USB3 PHY devices.

Remove ocp2scp1 address space from hwmod data as it is now provided via device tree.

CC Benoît Cousson <bcousson-rdvid1DuHRBWk0Htik3J/[email protected]>

Reviewed-by Felipe Balbi <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi               | 149 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 --
 2 files changed, 149 insertions(+), 10 deletions(-)

arch/arm/boot/dts/dra7.dtsi +149 -0

index 149b550..4535e54 100644
@@ -789,6 +789,155 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		omap_control_usb2phy1: control-phy@4a002300 {
+			compatible = "ti,control-phy-usb2";
+			reg = <0x4a002300 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb3phy1: control-phy@4a002370 {
+			compatible = "ti,control-phy-pipe3";
+			reg = <0x4a002370 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb2phy2: control-phy@0x4a002e74 {
+			compatible = "ti,control-phy-usb2-dra7";
+			reg = <0x4a002e74 0x4>;
+			reg-names = "power";
+		};
+
+		/* OCP2SCP1 */
+		ocp2scp@4a080000 {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = <0x4a080000 0x20>;
+			ti,hwmods = "ocp2scp1";
+
+			usb2_phy1: phy@4a084000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a084000 0x400>;
+				ctrl-module = <&omap_control_usb2phy1>;
+				clocks = <&usb_phy1_always_on_clk32k>,
+					 <&usb_otg_ss1_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb2_phy2: phy@4a085000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a085000 0x400>;
+				ctrl-module = <&omap_control_usb2phy2>;
+				clocks = <&usb_phy2_always_on_clk32k>,
+					 <&usb_otg_ss2_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb3_phy1: phy@4a084400 {
+				compatible = "ti,omap-usb3";
+				reg = <0x4a084400 0x80>,
+				      <0x4a084800 0x64>,
+				      <0x4a084c00 0x40>;
+				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+				ctrl-module = <&omap_control_usb3phy1>;
+				clocks = <&usb_phy3_always_on_clk32k>,
+					 <&sys_clkin1>,
+					 <&usb_otg_ss1_refclk960m>;
+				clock-names =	"wkupclk",
+						"sysclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+		};
+
+		omap_dwc3_1@48880000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss1";
+			reg = <0x48880000 0x10000>;
+			interrupts = <0 77 4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb1: usb@48890000 {
+				compatible = "snps,dwc3";
+				reg = <0x48890000 0x17000>;
+				interrupts = <0 76 4>;
+				phys = <&usb2_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				maximum-speed = "super-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_2@488c0000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss2";
+			reg = <0x488c0000 0x10000>;
+			interrupts = <0 92 4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb2: usb@488d0000 {
+				compatible = "snps,dwc3";
+				reg = <0x488d0000 0x17000>;
+				interrupts = <0 78 4>;
+				phys = <&usb2_phy2>;
+				phy-names = "usb2-phy";
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
+		omap_dwc3_3@48900000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss3";
+			reg = <0x48900000 0x10000>;
+		/*	interrupts = <0 TBD 4>; */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			status = "disabled";
+			usb3: usb@48910000 {
+				compatible = "snps,dwc3";
+				reg = <0x48910000 0x17000>;
+		/*		interrupts = <0 93 4>; */
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_4@48940000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss4";
+			reg = <0x48940000 0x10000>;
+		/*	interrupts = <0 TBD 4>; */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			status = "disabled";
+			usb4: usb@48950000 {
+				compatible = "snps,dwc3";
+				reg = <0x48950000 0x17000>;
+		/*		interrupts = <0 TBD 4>; */
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
 	};
 };

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +0 ~~-10~~

index 067d322..d6f9709 100644
@@ -2330,21 +2330,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
-	{
-		.pa_start	= 0x4a080000,
-		.pa_end		= 0x4a08001f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};
-
 /* l4_cfg -> ocp2scp1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
 	.master		= &dra7xx_l4_cfg_hwmod,
 	.slave		= &dra7xx_ocp2scp1_hwmod,
 	.clk		= "l4_root_clk_div",
-	.addr		= dra7xx_ocp2scp1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };

Signature · 6 lines

1.8.3.2

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A message that is not in the archive (sent off-list or not yet received): 1399283686-6127-7-git-send-email-rogerq-l0cyMroinI0@public.gmane.org

Roger Quadros

author

2014-05-07 08:45 UTC #16 lore raw

Re: [PATCH v3 6/7] ARM: dts: dra7: Add USB related nodes

Tony,

This patch will need to be updated for IRQ crossbar changes.

I will send a revised version of just this patch based on crossbar changes [1]

[1] - http://article.gmane.org/gmane.linux.documentation/23293

cheers,
-roger

Quoted 191 lines · Roger Quadros

Add nodes for the Super Speed USB controllers, omap-control-usb, USB2 PHY and USB3 PHY devices.

Remove ocp2scp1 address space from hwmod data as it is now provided via device tree.

CC Benoît Cousson <bcousson-rdvid1DuHRBWk0Htik3J/[email protected]>

Reviewed-by Felipe Balbi <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi               | 149 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 --
 2 files changed, 149 insertions(+), 10 deletions(-)

arch/arm/boot/dts/dra7.dtsi +149 -0

index 149b550..4535e54 100644
@@ -789,6 +789,155 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		omap_control_usb2phy1: control-phy@4a002300 {
+			compatible = "ti,control-phy-usb2";
+			reg = <0x4a002300 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb3phy1: control-phy@4a002370 {
+			compatible = "ti,control-phy-pipe3";
+			reg = <0x4a002370 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb2phy2: control-phy@0x4a002e74 {
+			compatible = "ti,control-phy-usb2-dra7";
+			reg = <0x4a002e74 0x4>;
+			reg-names = "power";
+		};
+
+		/* OCP2SCP1 */
+		ocp2scp@4a080000 {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = <0x4a080000 0x20>;
+			ti,hwmods = "ocp2scp1";
+
+			usb2_phy1: phy@4a084000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a084000 0x400>;
+				ctrl-module = <&omap_control_usb2phy1>;
+				clocks = <&usb_phy1_always_on_clk32k>,
+					 <&usb_otg_ss1_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb2_phy2: phy@4a085000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a085000 0x400>;
+				ctrl-module = <&omap_control_usb2phy2>;
+				clocks = <&usb_phy2_always_on_clk32k>,
+					 <&usb_otg_ss2_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb3_phy1: phy@4a084400 {
+				compatible = "ti,omap-usb3";
+				reg = <0x4a084400 0x80>,
+				      <0x4a084800 0x64>,
+				      <0x4a084c00 0x40>;
+				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+				ctrl-module = <&omap_control_usb3phy1>;
+				clocks = <&usb_phy3_always_on_clk32k>,
+					 <&sys_clkin1>,
+					 <&usb_otg_ss1_refclk960m>;
+				clock-names =	"wkupclk",
+						"sysclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+		};
+
+		omap_dwc3_1@48880000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss1";
+			reg = <0x48880000 0x10000>;
+			interrupts = <0 77 4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb1: usb@48890000 {
+				compatible = "snps,dwc3";
+				reg = <0x48890000 0x17000>;
+				interrupts = <0 76 4>;
+				phys = <&usb2_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				maximum-speed = "super-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_2@488c0000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss2";
+			reg = <0x488c0000 0x10000>;
+			interrupts = <0 92 4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb2: usb@488d0000 {
+				compatible = "snps,dwc3";
+				reg = <0x488d0000 0x17000>;
+				interrupts = <0 78 4>;
+				phys = <&usb2_phy2>;
+				phy-names = "usb2-phy";
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
+		omap_dwc3_3@48900000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss3";
+			reg = <0x48900000 0x10000>;
+		/*	interrupts = <0 TBD 4>; */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			status = "disabled";
+			usb3: usb@48910000 {
+				compatible = "snps,dwc3";
+				reg = <0x48910000 0x17000>;
+		/*		interrupts = <0 93 4>; */
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_4@48940000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss4";
+			reg = <0x48940000 0x10000>;
+		/*	interrupts = <0 TBD 4>; */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			status = "disabled";
+			usb4: usb@48950000 {
+				compatible = "snps,dwc3";
+				reg = <0x48950000 0x17000>;
+		/*		interrupts = <0 TBD 4>; */
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
 	};
 };

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +0 -8

index 067d322..d6f9709 100644
@@ -2330,21 +2330,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
-	{
-		.pa_start	= 0x4a080000,
-		.pa_end		= 0x4a08001f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};

arch/arm/mach-omap2/omap_hwmod_7xx_data.c static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { · line 2340

Quoted 10 lines

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +0 -2

-
 /* l4_cfg -> ocp2scp1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
 	.master		= &dra7xx_l4_cfg_hwmod,
 	.slave		= &dra7xx_ocp2scp1_hwmod,
 	.clk		= "l4_root_clk_div",
-	.addr		= dra7xx_ocp2scp1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };

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Roger Quadros

author

2014-05-07 11:55 UTC #17 lore raw

PATCH v4 6/7 ARM: dts: dra7: Add USB related nodes

In reply to a message not in the archive

Add nodes for the Super Speed USB controllers, omap-control-usb, USB2 PHY and USB3 PHY devices.

Use IRQ crossbar for interrupts.

Remove ocp2scp1 address space from hwmod data as it is now provided via device tree.

CC Benoît Cousson <bcousson-rdvid1DuHRBWk0Htik3J/[email protected]>

Reviewed-by Felipe Balbi <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi               | 148 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  10 --
 2 files changed, 148 insertions(+), 10 deletions(-)

arch/arm/boot/dts/dra7.dtsi +148 -0

index cec826f..8bc48bd 100644
@@ -798,6 +798,154 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		omap_control_usb2phy1: control-phy@4a002300 {
+			compatible = "ti,control-phy-usb2";
+			reg = <0x4a002300 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb3phy1: control-phy@4a002370 {
+			compatible = "ti,control-phy-pipe3";
+			reg = <0x4a002370 0x4>;
+			reg-names = "power";
+		};
+
+		omap_control_usb2phy2: control-phy@0x4a002e74 {
+			compatible = "ti,control-phy-usb2-dra7";
+			reg = <0x4a002e74 0x4>;
+			reg-names = "power";
+		};
+
+		/* OCP2SCP1 */
+		ocp2scp@4a080000 {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = <0x4a080000 0x20>;
+			ti,hwmods = "ocp2scp1";
+
+			usb2_phy1: phy@4a084000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a084000 0x400>;
+				ctrl-module = <&omap_control_usb2phy1>;
+				clocks = <&usb_phy1_always_on_clk32k>,
+					 <&usb_otg_ss1_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb2_phy2: phy@4a085000 {
+				compatible = "ti,omap-usb2";
+				reg = <0x4a085000 0x400>;
+				ctrl-module = <&omap_control_usb2phy2>;
+				clocks = <&usb_phy2_always_on_clk32k>,
+					 <&usb_otg_ss2_refclk960m>;
+				clock-names =	"wkupclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+
+			usb3_phy1: phy@4a084400 {
+				compatible = "ti,omap-usb3";
+				reg = <0x4a084400 0x80>,
+				      <0x4a084800 0x64>,
+				      <0x4a084c00 0x40>;
+				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+				ctrl-module = <&omap_control_usb3phy1>;
+				clocks = <&usb_phy3_always_on_clk32k>,
+					 <&sys_clkin1>,
+					 <&usb_otg_ss1_refclk960m>;
+				clock-names =	"wkupclk",
+						"sysclk",
+						"refclk";
+				#phy-cells = <0>;
+			};
+		};
+
+		omap_dwc3_1@48880000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss1";
+			reg = <0x48880000 0x10000>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb1: usb@48890000 {
+				compatible = "snps,dwc3";
+				reg = <0x48890000 0x17000>;
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				maximum-speed = "super-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_2@488c0000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss2";
+			reg = <0x488c0000 0x10000>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			usb2: usb@488d0000 {
+				compatible = "snps,dwc3";
+				reg = <0x488d0000 0x17000>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb2_phy2>;
+				phy-names = "usb2-phy";
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_3@48900000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss3";
+			reg = <0x48900000 0x10000>;
+			interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			status = "disabled";
+			usb3: usb@48910000 {
+				compatible = "snps,dwc3";
+				reg = <0x48910000 0x17000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
+
+		omap_dwc3_4@48940000 {
+			compatible = "ti,dwc3";
+			ti,hwmods = "usb_otg_ss4";
+			reg = <0x48940000 0x10000>;
+			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			utmi-mode = <2>;
+			ranges;
+			status = "disabled";
+			usb4: usb@48950000 {
+				compatible = "snps,dwc3";
+				reg = <0x48950000 0x17000>;
+				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+				tx-fifo-resize;
+				maximum-speed = "high-speed";
+				dr_mode = "otg";
+			};
+		};
 	};
 
 	crossbar_mpu: crossbar@4a020000 {

arch/arm/mach-omap2/omap_hwmod_7xx_data.c +0 -8

index 067d322..d6f9709 100644
@@ -2330,21 +2330,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
-	{
-		.pa_start	= 0x4a080000,
-		.pa_end		= 0x4a08001f,
-		.flags		= ADDR_TYPE_RT
-	},
-	{ }
-};

Roger Quadros

author

2014-05-06 07:19 UTC #18 lore raw

In reply to a message not in the archive

Hi Kishon,

Could you please pick the first 2 patches in this series for phy-next? They are independent of the rest. Thanks.

cheers,
-roger

Quoted 38 lines · Roger Quadros

Hi,
This series enables the 2 USB ports on the DRA7-evm.
NOTE: USB1 port is hard coded to work in peripheral mode and USB2 port in host mode. This is due to missing ID pin interrupt in pre ver.E boards.
USB1 port doesn't in peripheral mode out of the box due to missing VBUS detection and mailbox write. To test this I had to do a manual write to enable VBUSVALID in the USB_UTMI_OTG_STATUS register.
	omapconf set bit 0x48880084 1
USB2 port works well in host mode.
Patches are based on 3.15-rc3.
cheers,
-roger
Changelog:
v3:
(quoted diff) +0 -2
-Rearraged patches. PHY related stuff first.
-Addressed backward compatibility issue for phy-omap-usb2.
v2:
-Rebased on v3.15-rc3
---
Roger Quadros (7):
phy: omap-usb2: Use generic clock names "wkupclk" and "refclk"
phy: omap-usb2: Add clock names to Documentation binding
ARM: dts: omap4+: Add clocks to USB2 PHY node
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
ARM: dts: dra7: Add USB related nodes
dts: dra7-evm: add USB support

Quoted 10 lines

 Documentation/devicetree/bindings/phy/ti-phy.txt |   7 ++
 arch/arm/boot/dts/dra7-evm.dts                   |  24 ++++
 arch/arm/boot/dts/dra7.dtsi                      | 149 +++++++++++++++++++++++
 arch/arm/boot/dts/dra7xx-clocks.dtsi             |  12 +-
 arch/arm/boot/dts/omap4.dtsi                     |   2 +
 arch/arm/boot/dts/omap5.dtsi                     |   2 +
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c        |  22 ++--
 drivers/phy/phy-omap-usb2.c                      |  30 +++--
 8 files changed, 229 insertions(+), 19 deletions(-)

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Kishon Vijay Abraham I

2014-05-06 08:19 UTC #19 lore raw

Quoted 4 lines · Roger Quadros

Hi Kishon,
Could you please pick the first 2 patches in this series for phy-next? They are independent of the rest. Thanks.

sure.. will be queuing it shortly.

Thanks
Kishon

Quoted 54 lines

cheers,
-roger
Quoted 48 lines · Roger Quadros
Hi,
This series enables the 2 USB ports on the DRA7-evm.
NOTE: USB1 port is hard coded to work in peripheral mode and USB2 port in host mode. This is due to missing ID pin interrupt in pre ver.E boards.
USB1 port doesn't in peripheral mode out of the box due to missing VBUS detection and mailbox write. To test this I had to do a manual write to enable VBUSVALID in the USB_UTMI_OTG_STATUS register.
	omapconf set bit 0x48880084 1
USB2 port works well in host mode.
Patches are based on 3.15-rc3.
cheers,
-roger
Changelog:
v3:
(quoted diff) +0 -2
-Rearraged patches. PHY related stuff first.
-Addressed backward compatibility issue for phy-omap-usb2.
v2:
-Rebased on v3.15-rc3
---
Roger Quadros (7):
phy: omap-usb2: Use generic clock names "wkupclk" and "refclk"
phy: omap-usb2: Add clock names to Documentation binding
ARM: dts: omap4+: Add clocks to USB2 PHY node
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
ARM: dts: dra7: Add USB related nodes
dts: dra7-evm: add USB support
 Documentation/devicetree/bindings/phy/ti-phy.txt |   7 ++
 arch/arm/boot/dts/dra7-evm.dts                   |  24 ++++
 arch/arm/boot/dts/dra7.dtsi                      | 149 +++++++++++++++++++++++
 arch/arm/boot/dts/dra7xx-clocks.dtsi             |  12 +-
 arch/arm/boot/dts/omap4.dtsi                     |   2 +
 arch/arm/boot/dts/omap5.dtsi                     |   2 +
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c        |  22 ++--
 drivers/phy/phy-omap-usb2.c                      |  30 +++--
 8 files changed, 229 insertions(+), 19 deletions(-)

Roger Quadros

2014-05-05 09:54 UTC #20 lore raw

PATCH v3 2/7 phy: omap-usb2: Add clock names to Documentation binding

In reply to Roger Quadros

Add "wkupclk" and "refclk" information to DT binding information.

Reviewed-by Felipe Balbi <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 Documentation/devicetree/bindings/phy/ti-phy.txt | 7 +++++++
 1 file changed, 7 insertions(+)

Documentation/devicetree/bindings/phy/ti-phy.txt +7 -0

index 788fb0f..9ce458f 100644
@@ -32,6 +32,11 @@ Required properties:
  - reg : Address and length of the register set for the device.
  - #phy-cells: determine the number of cells that should be given in the
    phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+   clock-names.
+ - clock-names: should include:
+   * "wkupclk" - wakeup clock.
+   * "refclk" - reference clock (optional).
 
 Optional properties:
  - ctrl-module : phandle of the control module used by PHY driver to power on

@@ -44,6 +49,8 @@ usb2phy@4a0ad080 {
 	reg = <0x4a0ad080 0x58>;
 	ctrl-module = <&omap_control_usb>;
 	#phy-cells = <0>;
+	clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
+	clock-names = "wkupclk", "refclk";
 };
 
 TI PIPE3 PHY

Signature · 1 line

1.8.3.2

Roger Quadros

2014-05-05 09:54 UTC #21 lore raw

PATCH v3 4/7 ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate

In reply to Roger Quadros

This clock gate description is missing in the older Reference manuals. It is present on the SoC to provide 960MHz reference clock to the internal USB PHYs.

Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900, Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL

Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and usb_otg_ss2_refclk960m.

CC Benoît Cousson <[email protected]>

CC Tero Kristo <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

arch/arm/boot/dts/dra7xx-clocks.dtsi +10 -2

index cfb8fc7..c767687 100644
@@ -1386,6 +1386,14 @@
 		ti,dividers = <1>, <8>;
 	};
 
+	l3init_960m_gfclk: l3init_960m_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_clkdcoldo>;
+		ti,bit-shift = <8>;
+		reg = <0x06c0>;
+	};
+
 	dss_32khz_clk: dss_32khz_clk {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";

@@ -1533,7 +1541,7 @@
 	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_usb_clkdcoldo>;
+		clocks = <&l3init_960m_gfclk>;
 		ti,bit-shift = <8>;
 		reg = <0x13f0>;
 	};

@@ -1541,7 +1549,7 @@
 	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-		clocks = <&dpll_usb_clkdcoldo>;
+		clocks = <&l3init_960m_gfclk>;
 		ti,bit-shift = <8>;
 		reg = <0x1340>;
 	};

Signature · 6 lines

1.8.3.2

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Tero Kristo

Acked-by on v3 4/7

2014-05-06 10:10 UTC #22 lore raw

Re: [PATCH v3 4/7] ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate

Quoted 7 lines · Roger Quadros

This clock gate description is missing in the older Reference manuals. It is present on the SoC to provide 960MHz reference clock to the internal USB PHYs.
Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900, Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL

Quoted 6 lines

Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and usb_otg_ss2_refclk960m.
CC Benoît Cousson <[email protected]>
CC Tero Kristo <[email protected]>
Signed-off-by Roger Quadros <[email protected]>

Got myself to download the latest copy of the TRM, so this patch looks valid.

Acked-by Tero Kristo <[email protected]>

Quoted 34 lines

---
  arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++++++++++--
  1 file changed, 10 insertions(+), 2 deletions(-)

arch/arm/boot/dts/dra7xx-clocks.dtsi +9 -1

index cfb8fc7..c767687 100644
@@ -1386,6 +1386,14 @@
  		ti,dividers = <1>, <8>;
  	};
 
+	l3init_960m_gfclk: l3init_960m_gfclk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&dpll_usb_clkdcoldo>;
+		ti,bit-shift = <8>;
+		reg = <0x06c0>;
+	};
+
  	dss_32khz_clk: dss_32khz_clk {
  		#clock-cells = <0>;
  		compatible = "ti,gate-clock";

@@ -1533,7 +1541,7 @@
  	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
  		#clock-cells = <0>;
  		compatible = "ti,gate-clock";
-		clocks = <&dpll_usb_clkdcoldo>;
+		clocks = <&l3init_960m_gfclk>;
  		ti,bit-shift = <8>;
  		reg = <0x13f0>;
  	};

arch/arm/boot/dts/dra7xx-clocks.dtsi line 1555

Quoted 8 lines

arch/arm/boot/dts/dra7xx-clocks.dtsi +1 -1

@@ -1541,7 +1549,7 @@
  	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
  		#clock-cells = <0>;
  		compatible = "ti,gate-clock";
-		clocks = <&dpll_usb_clkdcoldo>;
+		clocks = <&l3init_960m_gfclk>;
  		ti,bit-shift = <8>;
  		reg = <0x1340>;
  	};

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Roger Quadros

2014-05-05 09:54 UTC #23 lore raw

PATCH v3 7/7 dts: dra7-evm: add USB support

In reply to Roger Quadros

Add USB pinmux information and USB modes
for the USB controllers.

CC Benoît Cousson <[email protected]>

Reviewed-by Felipe Balbi <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra7-evm.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm/boot/dts/dra7-evm.dts +24 -0

index 5babba0..1d77815 100644
@@ -93,6 +93,18 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+			0x280	0xc0000	/* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
+
+	usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+			0x284	0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
 };
 
 &i2c1 {

@@ -273,3 +285,15 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&usb1 {
+	dr_mode = "peripheral";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb2_pins>;
+};

Signature · 6 lines

1.8.3.2

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Tony Lindgren

maintainer

2014-05-13 17:18 UTC #24 lore raw

Re: [PATCH v3 7/7] dts: dra7-evm: add USB support

Quoted 21 lines · Roger Quadros

Add USB pinmux information and USB modes for the USB controllers.
CC Benoît Cousson <[email protected]>
Reviewed-by Felipe Balbi <[email protected]>
Signed-off-by Roger Quadros <[email protected]>
---
 arch/arm/boot/dts/dra7-evm.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
arch/arm/boot/dts/dra7-evm.dts +3 -0
index 5babba0..1d77815 100644
@@ -93,6 +93,18 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <

arch/arm/boot/dts/dra7-evm.dts line 108

Quoted 10 lines

arch/arm/boot/dts/dra7-evm.dts +9 -0

+			0x280	0xc0000	/* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
+
+	usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+			0x284	0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
 };

Looks like these should use the existing defins PIN_INPUT_SLEW etc?

Regards,

Tony
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Roger Quadros

author

2014-05-14 07:53 UTC #26 lore raw

Re: [PATCH v3 7/7] dts: dra7-evm: add USB support

Quoted 26 lines · Tony Lindgren

Quoted 25 lines · Roger Quadros
Add USB pinmux information and USB modes
for the USB controllers.
CC Benoît Cousson <bcousson-rdvid1DuHRBWk0Htik3J/[email protected]>
Reviewed-by Felipe Balbi <[email protected]>
Signed-off-by Roger Quadros <[email protected]>
---
 arch/arm/boot/dts/dra7-evm.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
arch/arm/boot/dts/dra7-evm.dts +7 -0
index 5babba0..1d77815 100644
@@ -93,6 +93,18 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+			0x280	0xc0000	/* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
+

Quoted 8 lines

arch/arm/boot/dts/dra7-evm.dts line 108
Quoted 6 lines
arch/arm/boot/dts/dra7-evm.dts +5 -0
+	usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+			0x284	0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+                >;
+        };
 };
Looks like these should use the existing defins PIN_INPUT_SLEW etc?

Yes, I'll fix them up.

cheers,
-roger
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Roger Quadros

author

2014-05-14 07:58 UTC #28 lore raw

PATCH v4 7/7 dts: dra7-evm: add USB support

From: Roger Quadros <[email protected]>

Add USB pinmux information and USB modes
for the USB controllers.

CC Benoît Cousson <bcousson-rdvid1DuHRBWk0Htik3J/[email protected]>

Reviewed-by Felipe Balbi <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/boot/dts/dra7-evm.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

arch/arm/boot/dts/dra7-evm.dts +24 -0

index 5babba0..222a7fa 100644
@@ -93,6 +93,18 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+			0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+                >;
+        };
+
+	usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+			0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+                >;
+        };
 };
 
 &i2c1 {

@@ -273,3 +285,15 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&usb1 {
+	dr_mode = "peripheral";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb2_pins>;
+};

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Tony Lindgren

2014-05-14 21:27 UTC #30 lore raw

Re: [PATCH v4 7/7] dts: dra7-evm: add USB support

Quoted 4 lines · Roger Quadros

From: Roger Quadros <[email protected]>
Add USB pinmux information and USB modes
for the USB controllers.

Thanks, applying all the .dts changes in this series into omap-for-v3.16/dt. Using the non-irqbar versions.

Tony
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