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iomux-v3: Add support for mx6sl LVE bit

PATCH New Fabio Estevam 3 participants 3 messages Apr 29, 2014 – May 9, 2014

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Arm (32-bit) Arm i.MX and Layerscape
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Fabio Estevam

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#0 lore raw

PATCH v2 1/1 iomux-v3: Add support for mx6sl LVE bit

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Use bit 1, which is unused.

 arch/arm/imx-common/iomux-v3.c             | 8 ++++++++
 arch/arm/include/asm/imx-common/iomux-v3.h | 5 +++++
 2 files changed, 13 insertions(+)
arch/arm/imx-common/iomux-v3.c +8 -0
index b59b802..6e46ea8 100644
@@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
 	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
+#if defined CONFIG_MX6SL
+	/* Check whether LVE bit needs to be set */
+	if (pad_ctrl & PAD_CTL_LVE) {
+		pad_ctrl &= ~PAD_CTL_LVE;
+		pad_ctrl |= PAD_CTL_LVE_BIT;
+	}
+#endif
+
 	if (mux_ctrl_ofs)
 		__raw_writel(mux_mode, base + mux_ctrl_ofs);
arch/arm/include/asm/imx-common/iomux-v3.h +5 -0
index dec11a1..cca920b 100644
@@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_DSE_40ohm	(6 << 3)
 #define PAD_CTL_DSE_34ohm	(7 << 3)
 
+#if defined CONFIG_MX6SL
+#define PAD_CTL_LVE		(1 << 1)
+#define PAD_CTL_LVE_BIT		(1 << 22)
+#endif
+
 #elif defined(CONFIG_VF610)
 
 #define PAD_MUX_MODE_SHIFT	20
Signature · 1 line
1.8.3.2
#1 lore raw

PATCH v2 1/1 iomux-v3: Add support for mx6sl LVE bit

Quoted 9 lines · Fabio Estevam

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by Fabio Estevam <[email protected]>
Tested-by Otavio Salvador <[email protected]>
Signature · 3 lines
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750
#2 lore raw

PATCH v2 1/1 iomux-v3: Add support for mx6sl LVE bit

In reply to Fabio Estevam
Quoted 10 lines · Fabio Estevam

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by Fabio Estevam <[email protected]>

---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines
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