ARM: EXYNOS5: Add Suspend-to-RAM support for 5420
PATCH v3 2/3 ARM: EXYNOS5: Add Suspend-to-RAM support for 5420
Adds Suspend-to-RAM support for EXYNOS5420
Signed-off-by Abhilash Kesavan <[email protected]>
Signed-off-by Vikas Sajjan <[email protected]>
--- arch/arm/mach-exynos/pm.c | 163 ++++++++++++++++++++++++++++++++++----- arch/arm/mach-exynos/regs-pmu.h | 2 + 2 files changed, 146 insertions(+), 19 deletions(-)
arch/arm/mach-exynos/pm.c +144 -19
@@ -40,6 +40,9 @@#include "regs-sys.h" #include "exynos-pmu.h" +#define EXYNOS5420_VA_CPU_STATE (S5P_VA_SYSRAM + 0x28) +#define EXYNOS5420_VA_CPU_ADDR (S5P_VA_SYSRAM_NS + 0x1C) +static struct regmap *pmu_regmap;/**
@@ -65,6 +68,19 @@ static struct sleep_save exynos_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; +static struct sleep_save exynos5420_cpustate_save[] = { +SAVE_ITEM (EXYNOS5420_VA_CPU_STATE ), +SAVE_ITEM (EXYNOS5420_VA_CPU_ADDR ), +}; + +static struct sleep_save exynos5420_pmu_reg_save[] = { +SAVE_ITEM (S5P_PMU_SPARE3 ), +}; + +static struct sleep_save exynos5420_reg_save[] = { +SAVE_ITEM (EXYNOS5_SYS_DISP1_BLK_CFG ), +}; +/* * GIC wake-up support */
@@ -87,7 +103,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) {const struct exynos_wkup_irq *wkup_irq; -if (soc_is_exynos5250 ()) +if (soc_is_exynos5250 () ||soc_is_exynos5420 ()) wkup_irq = exynos5250_wkup_irq;else wkup_irq = exynos4_wkup_irq;
@@ -188,7 +204,15 @@ static int exynos_cpu_suspend(unsigned long arg)outer_flush_all ();#endif -if (soc_is_exynos5250 ()) +/* +* Clear IRAM register for cpu state so that primary CPU does +* not enter low power start in U-Boot. +* This is specific to exynos5420 SoC only. +*/ +if (soc_is_exynos5420 ()) +__raw_writel (0x0 ,EXYNOS5420_VA_CPU_STATE ); + +if (soc_is_exynos5250 () ||soc_is_exynos5420 ())flush_cache_all ();/* issue the standby signal into the pm unit. */
@@ -216,6 +240,26 @@ static void exynos_pm_prepare(void)regmap_read (pmu_regmap,EXYNOS5_JPEG_MEM_OPTION , &tmp); tmp &= ~EXYNOS5_OPTION_USE_RETENTION ;regmap_write (pmu_regmap,EXYNOS5_JPEG_MEM_OPTION , tmp); + }else if (soc_is_exynos5420 ()) { + +unsigned i; + +s3c_pm_do_save (exynos5420_reg_save, +ARRAY_SIZE (exynos5420_reg_save)); + +for (i =0 ; i <ARRAY_SIZE (exynos5420_pmu_reg_save); i++) +regmap_read (pmu_regmap, + (unsigned int )exynos5420_pmu_reg_save[i].reg, + (unsigned int *)&exynos5420_pmu_reg_save[i].val); +/* +* The cpu state needs to be saved and restored so that the +* secondary CPUs will enter low power start. Though the U-Boot +* is setting the cpu state with low power flag, the kernel +* needs to restore it back in case, the primary cpu fails to +* suspend for any reason +*/ +s3c_pm_do_save (exynos5420_cpustate_save, +ARRAY_SIZE (exynos5420_cpustate_save)); }/* Set value of power down register for sleep mode */
@@ -226,6 +270,26 @@ static void exynos_pm_prepare(void)/* ensure@least INFORM0 has the resume address */ regmap_write (pmu_regmap,S5P_INFORM0 ,virt_to_phys (exynos_cpu_resume)); + +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,EXYNOS5_ARM_L2_OPTION , &tmp); + tmp &= ~EXYNOS5_USE_RETENTION ; +regmap_write (pmu_regmap,EXYNOS5_ARM_L2_OPTION , tmp); + +regmap_read (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , &tmp); + tmp |=EXYNOS5420_UFS ; +regmap_write (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , tmp); + +regmap_read (pmu_regmap,EXYNOS5420_ARM_COMMON_OPTION , &tmp); + tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE ; +regmap_write (pmu_regmap,EXYNOS5420_ARM_COMMON_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_FSYS2_OPTION , &tmp); + tmp |=EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_FSYS2_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_PSGEN_OPTION , &tmp); + tmp |=EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_PSGEN_OPTION , tmp); + } }static void exynos_pm_central_suspend (void )
@@ -242,12 +306,20 @@ static int exynos_pm_suspend(void) {unsigned int tmp; +unsigned int this_cluster;exynos_pm_central_suspend ();/* Setting SEQ_OPTION register */ - - tmp = (S5P_USE_STANDBY_WFI0 |S5P_USE_STANDBY_WFE0 ); -regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , tmp); +if (soc_is_exynos5420 ()) { + this_cluster =MPIDR_AFFINITY_LEVEL (read_cpuid_mpidr (),1 ); +if (!this_cluster) +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION ,EXYNOS5420_ARM_USE_STANDBY_WFI0 ); +else +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION ,EXYNOS5420_KFC_USE_STANDBY_WFI0 ); + }else { + tmp = (S5P_USE_STANDBY_WFI0 |S5P_USE_STANDBY_WFE0 ); +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , tmp); + }if (!soc_is_exynos5250 ())exynos_cpu_save_register ();
@@ -280,33 +352,80 @@ static int exynos_pm_central_resume(void)static void exynos_pm_resume (void ) { +unsigned int tmp; +if (soc_is_exynos5420 ()) { +/* Restore the IRAM register cpu state */ +s3c_pm_do_restore (exynos5420_cpustate_save, +ARRAY_SIZE (exynos5420_cpustate_save)); + +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , +EXYNOS5420_USE_STANDBY_WFI_ALL ); + } +if (exynos_pm_central_resume ()) goto early_wakeup; -if (!soc_is_exynos5250 ()) +if (!(soc_is_exynos5250 () ||soc_is_exynos5420 ()))exynos_cpu_restore_register ();/* For release retention */ -regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); +if (soc_is_exynos5250 ()) { +regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); + }else if (soc_is_exynos5420 ()) { +regmap_write (pmu_regmap,EXYNOS_PAD_RET_DRAM_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_MAUDIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_JTAG_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_GPIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_UART_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCC_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_HSI_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_SPI_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION , (1 <<28 )); + } -if (soc_is_exynos5250 ()) +if (soc_is_exynos5250 ()) {s3c_pm_do_restore (exynos5_sys_save,ARRAY_SIZE (exynos5_sys_save)); + }else if (soc_is_exynos5420 ()) { +unsigned int i; +s3c_pm_do_restore (exynos5420_reg_save, +ARRAY_SIZE (exynos5420_reg_save)); +for (i =0 ; i <ARRAY_SIZE (exynos5420_pmu_reg_save); i++) +regmap_write (pmu_regmap, + (unsigned int )exynos5420_pmu_reg_save[i].reg, + (unsigned int )exynos5420_pmu_reg_save[i].val); + }s3c_pm_do_restore_core (exynos_core_save,ARRAY_SIZE (exynos_core_save)); -if (!soc_is_exynos5250 ()) +if (!soc_is_exynos5250 () && !soc_is_exynos5420 ())scu_enable (S5P_VA_SCU ); early_wakeup: +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , &tmp); + tmp &= ~EXYNOS5420_UFS ; +regmap_write (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , tmp); +regmap_read (pmu_regmap,EXYNOS5420_FSYS2_OPTION , &tmp); + tmp &= ~EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_FSYS2_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_PSGEN_OPTION , &tmp); + tmp &= ~EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_PSGEN_OPTION , tmp); + } +/* Clear SLEEP mode set in INFORM1 */ regmap_write (pmu_regmap,S5P_INFORM1 ,0x0 );
@@ -395,7 +514,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self,case CPU_PM_EXIT :if (cpu ==0 ) { -if (!soc_is_exynos5250 ()) +if (!(soc_is_exynos5250 () ||soc_is_exynos5420 ()))scu_enable (S5P_VA_SCU );exynos_cpu_restore_register ();exynos_pm_central_resume ();
@@ -421,9 +540,15 @@ void __init exynos_pm_init(void) gic_arch_extn.irq_set_wake = exynos_irq_set_wake;/* All wakeup disable */ -regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); - tmp |= ((0xFF <<8 ) | (0x1F <<1 )); -regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); + tmp |= ((0x7F <<7 ) | (0x1F <<1 )); +regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); + }else { +regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); + tmp |= ((0xFF <<8 ) | (0x1F <<1 )); +regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); + }register_syscore_ops (&exynos_pm_syscore_ops);suspend_set_ops (&exynos_suspend_ops);
arch/arm/mach-exynos/regs-pmu.h +2 -0
@@ -35,6 +35,7 @@#define S5P_INFORM5 (0x0814)#define S5P_INFORM6 (0x0818)#define S5P_INFORM7 (0x081C) +#define S5P_PMU_SPARE3 (0x090c)#define EXYNOS_IROM_DATA2 (0x0988)#define S5P_ARM_CORE0_LOWPWR (0x1000)
@@ -211,6 +212,7 @@/* For EXYNOS5 */ +#define EXYNOS5_SYS_DISP1_BLK_CFG S5P_SYSREG(0x0214)#define EXYNOS5_AUTO_WDTRESET_DISABLE (0x0408)#define EXYNOS5_MASK_WDTRESET_REQUEST (0x040C)
Signature · 1 line
1.7.9.5
PATCH v3 2/3 ARM: EXYNOS5: Add Suspend-to-RAM support for 5420
Hi,
Quoted 13 lines · Vikas Sajjan
Adds Suspend-to-RAM support for EXYNOS5420
Signed-off-by Abhilash Kesavan <[email protected]>Signed-off-by Vikas Sajjan <[email protected]>--- arch/arm/mach-exynos/pm.c | 163 ++++++++++++++++++++++++++++++++++----- arch/arm/mach-exynos/regs-pmu.h | 2 + 2 files changed, 146 insertions(+), 19 deletions(-)arch/arm/mach-exynos/pm.c +0
-0
[...]
Quoted 21 lines
arch/arm/mach-exynos/pm.c +11
-1@@ -280,33 +352,80 @@ static int exynos_pm_central_resume(void)static void exynos_pm_resume (void ) { +unsigned int tmp; +if (soc_is_exynos5420 ()) { +/* Restore the IRAM register cpu state */ +s3c_pm_do_restore (exynos5420_cpustate_save, +ARRAY_SIZE (exynos5420_cpustate_save)); + +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , +EXYNOS5420_USE_STANDBY_WFI_ALL ); + } +if (exynos_pm_central_resume ()) goto early_wakeup; -if (!soc_is_exynos5250 ()) +if (!(soc_is_exynos5250 () ||soc_is_exynos5420 ()))exynos_cpu_restore_register ();
arch/arm/mach-exynos/pm.c static int exynos_pm_central_resume(void) · line 373
Quoted 10 lines
arch/arm/mach-exynos/pm.c +1
-7/* For release retention */ -regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); +if (soc_is_exynos5250 ()) {
Adding a check here for EXYNOS5250 doesn't look correct (the old code behavior for older EXYNOS SoCs should be preserved).
Quoted 12 lines
arch/arm/mach-exynos/pm.c +12
-0+regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); + }else if (soc_is_exynos5420 ()) { +regmap_write (pmu_regmap,EXYNOS_PAD_RET_DRAM_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_MAUDIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_JTAG_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_GPIO_OPTION , (1 <<28 ));
arch/arm/mach-exynos/pm.c static int exynos_pm_central_resume(void) · line 395
Quoted 10 lines
arch/arm/mach-exynos/pm.c +10
-0+regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_UART_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCC_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_HSI_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_SPI_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION , (1 <<28 )); + }
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
PATCH v3 2/3 ARM: EXYNOS5: Add Suspend-to-RAM support for 5420
Hi Bartlomiej,
[...]
Quoted 10 lines
arch/arm/mach-exynos/pm.c static int exynos_pm_central_resume(void) · line 373
Quoted 9 lines
arch/arm/mach-exynos/pm.c +1
-7-regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); +if (soc_is_exynos5250 ()) {
Quoted 2 lines
Adding a check here for EXYNOS5250 doesn't look correct (the old code behavior for older EXYNOS SoCs should be preserved).
Will fix this in the next version.
Regards,
Abhilash
PATCH v3 2/3 ARM: EXYNOS5: Add Suspend-to-RAM support for 5420
In reply to Vikas SajjanHi Vikas,
Quoted 14 lines · Vikas Sajjan
Adds Suspend-to-RAM support for EXYNOS5420
Signed-off-by Abhilash Kesavan <[email protected]>Signed-off-by Vikas Sajjan <[email protected]>--- arch/arm/mach-exynos/pm.c | 163 ++++++++++++++++++++++++++++++++++----- arch/arm/mach-exynos/regs-pmu.h | 2 + 2 files changed, 146 insertions(+), 19 deletions(-)arch/arm/mach-exynos/pm.c +0
-0
arch/arm/mach-exynos/pm.c line 45
Quoted 6 lines
arch/arm/mach-exynos/pm.c +3
-0@@ -40,6 +40,9 @@#include "regs-sys.h" #include "exynos-pmu.h" +#define EXYNOS5420_VA_CPU_STATE (S5P_VA_SYSRAM + 0x28) +#define EXYNOS5420_VA_CPU_ADDR (S5P_VA_SYSRAM_NS + 0x1C) +
It will be good if we can rebase this change on top of Sachin's SYSRAM patches [1]
Quoted 50 lines
arch/arm/mach-exynos/pm.c +23
-2static struct regmap *pmu_regmap;/** @@ -65,6 +68,19 @@ static struct sleep_save exynos_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; +static struct sleep_save exynos5420_cpustate_save[] = { +SAVE_ITEM (EXYNOS5420_VA_CPU_STATE ), +SAVE_ITEM (EXYNOS5420_VA_CPU_ADDR ), +}; + +static struct sleep_save exynos5420_pmu_reg_save[] = { +SAVE_ITEM (S5P_PMU_SPARE3 ), +}; + +static struct sleep_save exynos5420_reg_save[] = { +SAVE_ITEM (EXYNOS5_SYS_DISP1_BLK_CFG ), +}; +/* * GIC wake-up support */ @@ -87,7 +103,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) {const struct exynos_wkup_irq *wkup_irq; -if (soc_is_exynos5250 ()) +if (soc_is_exynos5250 () ||soc_is_exynos5420 ()) wkup_irq = exynos5250_wkup_irq;else wkup_irq = exynos4_wkup_irq;@@ -188,7 +204,15 @@ static int exynos_cpu_suspend(unsigned long arg)outer_flush_all ();#endif -if (soc_is_exynos5250 ()) +/* +* Clear IRAM register for cpu state so that primary CPU does +* not enter low power start in U-Boot. +* This is specific to exynos5420 SoC only. +*/ +if (soc_is_exynos5420 ()) +__raw_writel (0x0 ,EXYNOS5420_VA_CPU_STATE ); + +if (soc_is_exynos5250 () ||soc_is_exynos5420 ())flush_cache_all ();/* issue the standby signal into the pm unit. */
arch/arm/mach-exynos/pm.c static void exynos_pm_prepare(void) · line 249
Quoted 10 lines
arch/arm/mach-exynos/pm.c +7
-0@@ -216,6 +240,26 @@ static void exynos_pm_prepare(void)regmap_read (pmu_regmap,EXYNOS5_JPEG_MEM_OPTION , &tmp); tmp &= ~EXYNOS5_OPTION_USE_RETENTION ;regmap_write (pmu_regmap,EXYNOS5_JPEG_MEM_OPTION , tmp); + }else if (soc_is_exynos5420 ()) { + +unsigned i; + +s3c_pm_do_save (exynos5420_reg_save, +ARRAY_SIZE (exynos5420_reg_save)); +
Is it possible to move this code in DISP driver somewhere?
As if you see I have already posted some patches [1] to remove i2c SYS CFG register configuration during S2R from pm.c to i2c driver itself for Exynos5250 as suggested by Arnd.
This way we can reduce dependency of regs-sys.h in pm.c also we do not need to statically map sysreg register in exynos.c, and in general it will us in cleaning up exynos code from such things as it is being discussed here [2]
[1]: https://lkml.org/lkml/2014/5/6/104
[2]: https://lkml.org/lkml/2014/5/6/71
Quoted 199 lines
arch/arm/mach-exynos/pm.c +111
-17+for (i =0 ; i <ARRAY_SIZE (exynos5420_pmu_reg_save); i++) +regmap_read (pmu_regmap, + (unsigned int )exynos5420_pmu_reg_save[i].reg, + (unsigned int *)&exynos5420_pmu_reg_save[i].val); +/* +* The cpu state needs to be saved and restored so that the +* secondary CPUs will enter low power start. Though the U-Boot +* is setting the cpu state with low power flag, the kernel +* needs to restore it back in case, the primary cpu fails to +* suspend for any reason +*/ +s3c_pm_do_save (exynos5420_cpustate_save, +ARRAY_SIZE (exynos5420_cpustate_save)); }/* Set value of power down register for sleep mode */ @@ -226,6 +270,26 @@ static void exynos_pm_prepare(void)/* ensure at least INFORM0 has the resume address */ regmap_write (pmu_regmap,S5P_INFORM0 ,virt_to_phys (exynos_cpu_resume)); + +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,EXYNOS5_ARM_L2_OPTION , &tmp); + tmp &= ~EXYNOS5_USE_RETENTION ; +regmap_write (pmu_regmap,EXYNOS5_ARM_L2_OPTION , tmp); + +regmap_read (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , &tmp); + tmp |=EXYNOS5420_UFS ; +regmap_write (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , tmp); + +regmap_read (pmu_regmap,EXYNOS5420_ARM_COMMON_OPTION , &tmp); + tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE ; +regmap_write (pmu_regmap,EXYNOS5420_ARM_COMMON_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_FSYS2_OPTION , &tmp); + tmp |=EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_FSYS2_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_PSGEN_OPTION , &tmp); + tmp |=EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_PSGEN_OPTION , tmp); + } }static void exynos_pm_central_suspend (void )@@ -242,12 +306,20 @@ static int exynos_pm_suspend(void) {unsigned int tmp; +unsigned int this_cluster;exynos_pm_central_suspend ();/* Setting SEQ_OPTION register */ - - tmp = (S5P_USE_STANDBY_WFI0 |S5P_USE_STANDBY_WFE0 ); -regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , tmp); +if (soc_is_exynos5420 ()) { + this_cluster =MPIDR_AFFINITY_LEVEL (read_cpuid_mpidr (),1 ); +if (!this_cluster) +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION ,EXYNOS5420_ARM_USE_STANDBY_WFI0 ); +else +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION ,EXYNOS5420_KFC_USE_STANDBY_WFI0 ); + }else { + tmp = (S5P_USE_STANDBY_WFI0 |S5P_USE_STANDBY_WFE0 ); +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , tmp); + }if (!soc_is_exynos5250 ())exynos_cpu_save_register ();@@ -280,33 +352,80 @@ static int exynos_pm_central_resume(void)static void exynos_pm_resume (void ) { +unsigned int tmp; +if (soc_is_exynos5420 ()) { +/* Restore the IRAM register cpu state */ +s3c_pm_do_restore (exynos5420_cpustate_save, +ARRAY_SIZE (exynos5420_cpustate_save)); + +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , +EXYNOS5420_USE_STANDBY_WFI_ALL ); + } +if (exynos_pm_central_resume ()) goto early_wakeup; -if (!soc_is_exynos5250 ()) +if (!(soc_is_exynos5250 () ||soc_is_exynos5420 ()))exynos_cpu_restore_register ();/* For release retention */ -regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); +if (soc_is_exynos5250 ()) { +regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); + }else if (soc_is_exynos5420 ()) { +regmap_write (pmu_regmap,EXYNOS_PAD_RET_DRAM_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_MAUDIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_JTAG_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_GPIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_UART_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCC_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_HSI_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_SPI_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION , (1 <<28 )); + } -if (soc_is_exynos5250 ()) +if (soc_is_exynos5250 ()) {s3c_pm_do_restore (exynos5_sys_save,ARRAY_SIZE (exynos5_sys_save)); + }else if (soc_is_exynos5420 ()) { +unsigned int i; +s3c_pm_do_restore (exynos5420_reg_save, +ARRAY_SIZE (exynos5420_reg_save)); +for (i =0 ; i <ARRAY_SIZE (exynos5420_pmu_reg_save); i++) +regmap_write (pmu_regmap, + (unsigned int )exynos5420_pmu_reg_save[i].reg, + (unsigned int )exynos5420_pmu_reg_save[i].val); + }s3c_pm_do_restore_core (exynos_core_save,ARRAY_SIZE (exynos_core_save)); -if (!soc_is_exynos5250 ()) +if (!soc_is_exynos5250 () && !soc_is_exynos5420 ())scu_enable (S5P_VA_SCU ); early_wakeup: +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , &tmp); + tmp &= ~EXYNOS5420_UFS ; +regmap_write (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , tmp); +regmap_read (pmu_regmap,EXYNOS5420_FSYS2_OPTION , &tmp); + tmp &= ~EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_FSYS2_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_PSGEN_OPTION , &tmp); + tmp &= ~EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_PSGEN_OPTION , tmp); + } +/* Clear SLEEP mode set in INFORM1 */ regmap_write (pmu_regmap,S5P_INFORM1 ,0x0 );@@ -395,7 +514,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self,case CPU_PM_EXIT :if (cpu ==0 ) { -if (!soc_is_exynos5250 ()) +if (!(soc_is_exynos5250 () ||soc_is_exynos5420 ()))scu_enable (S5P_VA_SCU );exynos_cpu_restore_register ();exynos_pm_central_resume ();@@ -421,9 +540,15 @@ void __init exynos_pm_init(void) gic_arch_extn.irq_set_wake = exynos_irq_set_wake;/* All wakeup disable */ -regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); - tmp |= ((0xFF <<8 ) | (0x1F <<1 )); -regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); + tmp |= ((0x7F <<7 ) | (0x1F <<1 )); +regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); + }else { +regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); + tmp |= ((0xFF <<8 ) | (0x1F <<1 )); +regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); + }register_syscore_ops (&exynos_pm_syscore_ops);suspend_set_ops (&exynos_suspend_ops);arch/arm/mach-exynos/regs-pmu.h +1
-0@@ -35,6 +35,7 @@#define S5P_INFORM5 (0x0814)#define S5P_INFORM6 (0x0818)#define S5P_INFORM7 (0x081C) +#define S5P_PMU_SPARE3 (0x090c)#define EXYNOS_IROM_DATA2 (0x0988)#define S5P_ARM_CORE0_LOWPWR (0x1000)
arch/arm/mach-exynos/regs-pmu.h line 215
Quoted 4 lines
arch/arm/mach-exynos/regs-pmu.h +1
-0@@ -211,6 +212,7 @@/* For EXYNOS5 */ +#define EXYNOS5_SYS_DISP1_BLK_CFG S5P_SYSREG(0x0214)
I think this offset should not be added here as it does not belong with PMU. Moreover IIRC if you have rebased these patches on my Exynos PMU patch series [1], this change should fail to compile as "regs-pmu.h" does not have anymore "mach/map.h" and definition for S5P_SYSREG has been moved to a new file "regs-sys.h". Please check here [2]
[1]: https://lkml.org/lkml/2014/5/2/612
[2]: https://lkml.org/lkml/2014/4/30/8
Quoted 3 lines
arch/arm/mach-exynos/regs-pmu.h +0
-0#define EXYNOS5_AUTO_WDTRESET_DISABLE (0x0408)#define EXYNOS5_MASK_WDTRESET_REQUEST (0x040C)
Signature · 2 lines
Best Regards, Pankaj Dubey
PATCH v3 2/3 ARM: EXYNOS5: Add Suspend-to-RAM support for 5420
Hi Pankaj,
[...]
Quoted 9 lines
arch/arm/mach-exynos/pm.c line 45
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+#define
EXYNOS5420_VA_CPU_STATE(S5P_VA_SYSRAM+0x28)arch/arm/mach-exynos/pm.c +2
-0+#define EXYNOS5420_VA_CPU_ADDR (S5P_VA_SYSRAM_NS + 0x1C) +It will be good if we can rebase this change on top of Sachin's SYSRAM patches [1]
This is now merged in Kukjin's for-next. Have rebased my patches on top of it.
[...]
Quoted 15 lines
arch/arm/mach-exynos/pm.c static void exynos_pm_prepare(void) · line 249
Quoted 6 lines
arch/arm/mach-exynos/pm.c +6
-0+ +unsigned i; + +s3c_pm_do_save (exynos5420_reg_save, +ARRAY_SIZE (exynos5420_reg_save)); +Is it possible to move this code in DISP driver somewhere?
As if you see I have already posted some patches [1] to remove i2c SYS CFG register
configuration during S2R frompm.cto i2c driver itself for Exynos5250 as suggested
by Arnd.
Quoted 8 lines
This way we can reduce dependency of
regs-sys.hinpm.calso we do not need to
statically map sysreg register inexynos.c, and in general it will us in cleaning up
exynos code from such things as it is being discussed here [2][1]: https://lkml.org/lkml/2014/5/6/104
[2]: https://lkml.org/lkml/2014/5/6/71
Will remove.
[...]
Quoted 12 lines
Quoted 3 lines
/* For EXYNOS5 */+#define
EXYNOS5_SYS_DISP1_BLK_CFGS5P_SYSREG(0x0214)I think this offset should not be added here as it does not belong with PMU. Moreover IIRC if you have rebased these patches on my Exynos PMU patch series [1],
this change should fail to compile as "regs-pmu.h" does not have anymore "mach/map.h" and definition forS5P_SYSREGhas been moved to a new file "regs-sys.h". Please check here [2]
Quoted 2 lines
[1]: https://lkml.org/lkml/2014/5/2/612
[2]: https://lkml.org/lkml/2014/4/30/8
Will remove.
Quoted 18 lines
Quoted 5 lines
#define EXYNOS5_AUTO_WDTRESET_DISABLE (0x0408) #define EXYNOS5_MASK_WDTRESET_REQUEST (0x040C)--
Best Regards,
Pankaj Dubey_______________________________________________
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