ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs

From: David Lanzend?rfer <[email protected]>

The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices.

HdG: Various cleanups and fixes.

Signed-off-by David Lanzend?rfer <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

drivers/mmc/host/sunxi-mmc.c new file +47 -0

+       int ret;
+
+       rate = clk_round_rate(host->clk_mmc, ios->clock);
+       dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
+               ios->clock, rate);
+
+       /* setting clock rate */
+       ret = clk_set_rate(host->clk_mmc, rate);
+       if (ret) {
+               dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
+                       rate, ret);
+               return ret;
+       }
+
+       ret = sunxi_mmc_oclk_onoff(host, 0);
+       if (ret)
+               return ret;
+
+       /* clear internal divider */
+       rval = mmc_readl(host, REG_CLKCR);
+       rval &= ~0xff;
+       mmc_writel(host, REG_CLKCR, rval);
+
+       /* determine delays */
+       if (rate <= 400000) {
+               oclk_dly = 0;
+               sclk_dly = 7;
+       } else if (rate <= 25000000) {
+               oclk_dly = 0;
+               sclk_dly = 5;
+       } else if (rate <= 50000000) {
+               if (ios->timing == MMC_TIMING_UHS_DDR50) {
+                       oclk_dly = 2;
+                       sclk_dly = 4;
+               } else {
+                       oclk_dly = 3;
+                       sclk_dly = 5;
+               }
+       } else {
+               /* rate > 50000000 */
+               oclk_dly = 2;
+               sclk_dly = 4;
+       }
+
+       src_clk = clk_get_rate(clk_get_parent(host->clk_mmc));
+       if (src_clk >= 300000000 && src_clk <= 400000000) {
+               if (oclk_dly)

Quoted 12 lines · Hans de Goede

From: David Lanzend?rfer <[email protected]>

The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices.

HdG: Various cleanups and fixes.

Signed-off-by David Lanzend?rfer <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

[snip]

drivers/mmc/host/sunxi-mmc.c line 621

Quoted 6 lines

drivers/mmc/host/sunxi-mmc.c new file +6 -0

+
+static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
+                                 struct mmc_ios *ios)
+{
+       u32 rate, oclk_dly, rval, sclk_dly, src_clk;
+       struct clk_hw *hw = __clk_get_hw(host->clk_mmc);

Hi Hans,

This seems like the wrong approach. But I guess it's related to the "clock phase control" API you have been discussing with the clk maintainer, Mike Turquette!?

__clk_get_hw is supposed to be used by clk providers, not clk consumers.

Quoted 57 lines

drivers/mmc/host/sunxi-mmc.c new file +57 -0

+       int ret;
+
+       rate = clk_round_rate(host->clk_mmc, ios->clock);
+       dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
+               ios->clock, rate);
+
+       /* setting clock rate */
+       ret = clk_set_rate(host->clk_mmc, rate);
+       if (ret) {
+               dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
+                       rate, ret);
+               return ret;
+       }
+
+       ret = sunxi_mmc_oclk_onoff(host, 0);
+       if (ret)
+               return ret;
+
+       /* clear internal divider */
+       rval = mmc_readl(host, REG_CLKCR);
+       rval &= ~0xff;
+       mmc_writel(host, REG_CLKCR, rval);
+
+       /* determine delays */
+       if (rate <= 400000) {
+               oclk_dly = 0;
+               sclk_dly = 7;
+       } else if (rate <= 25000000) {
+               oclk_dly = 0;
+               sclk_dly = 5;
+       } else if (rate <= 50000000) {
+               if (ios->timing == MMC_TIMING_UHS_DDR50) {
+                       oclk_dly = 2;
+                       sclk_dly = 4;
+               } else {
+                       oclk_dly = 3;
+                       sclk_dly = 5;
+               }
+       } else {
+               /* rate > 50000000 */
+               oclk_dly = 2;
+               sclk_dly = 4;
+       }
+
+       src_clk = clk_get_rate(clk_get_parent(host->clk_mmc));
+       if (src_clk >= 300000000 && src_clk <= 400000000) {
+               if (oclk_dly)
+                       oclk_dly--;
+               if (sclk_dly)
+                       sclk_dly--;
+       }
+
+       clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
+
+       return sunxi_mmc_oclk_onoff(host, 1);
+}
+

[snip]

Besides the above, I think this looks good!

Hi,

Quoted 25 lines · Ulf Hansson

Quoted 12 lines · Hans de Goede

From: David Lanzend?rfer <[email protected]>

The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices.

HdG: Various cleanups and fixes.

Signed-off-by David Lanzend?rfer <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

[snip]

drivers/mmc/host/sunxi-mmc.c line 621

Quoted 6 lines

drivers/mmc/host/sunxi-mmc.c new file +6 -0

+
+static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
+                                 struct mmc_ios *ios)
+{
+       u32 rate, oclk_dly, rval, sclk_dly, src_clk;
+       struct clk_hw *hw = __clk_get_hw(host->clk_mmc);

Hi Hans,

Quoted 3 lines

This seems like the wrong approach. But I guess it's related to the "clock phase control" API you have been discussing with the clk maintainer, Mike Turquette!?

Yes, this is meant as a temporary solution until we get a proper "clock phase control" API.

Quoted 63 lines

__clk_get_hw is supposed to be used by clk providers, not clk consumers.

Quoted 57 lines

drivers/mmc/host/sunxi-mmc.c new file +57 -0

+       int ret;
+
+       rate = clk_round_rate(host->clk_mmc, ios->clock);
+       dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
+               ios->clock, rate);
+
+       /* setting clock rate */
+       ret = clk_set_rate(host->clk_mmc, rate);
+       if (ret) {
+               dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
+                       rate, ret);
+               return ret;
+       }
+
+       ret = sunxi_mmc_oclk_onoff(host, 0);
+       if (ret)
+               return ret;
+
+       /* clear internal divider */
+       rval = mmc_readl(host, REG_CLKCR);
+       rval &= ~0xff;
+       mmc_writel(host, REG_CLKCR, rval);
+
+       /* determine delays */
+       if (rate <= 400000) {
+               oclk_dly = 0;
+               sclk_dly = 7;
+       } else if (rate <= 25000000) {
+               oclk_dly = 0;
+               sclk_dly = 5;
+       } else if (rate <= 50000000) {
+               if (ios->timing == MMC_TIMING_UHS_DDR50) {
+                       oclk_dly = 2;
+                       sclk_dly = 4;
+               } else {
+                       oclk_dly = 3;
+                       sclk_dly = 5;
+               }
+       } else {
+               /* rate > 50000000 */
+               oclk_dly = 2;
+               sclk_dly = 4;
+       }
+
+       src_clk = clk_get_rate(clk_get_parent(host->clk_mmc));
+       if (src_clk >= 300000000 && src_clk <= 400000000) {
+               if (oclk_dly)
+                       oclk_dly--;
+               if (sclk_dly)
+                       sclk_dly--;
+       }
+
+       clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
+
+       return sunxi_mmc_oclk_onoff(host, 1);
+}
+

[snip]

Quoted 1 line

Besides the above, I think this looks good!

Thanks!

Since Mike Turquette has already merged clk_sunxi_mmc_phase_control I would like to keep this as is, as I already promised Mike, I can safely promise you too: I promise clean this up as soon as the "clock phase control" API has been worked out.

Regards,

Hans

Quoted 98 lines · Hans de Goede

Hi,

Quoted 25 lines · Ulf Hansson

Quoted 12 lines · Hans de Goede

From: David Lanzend?rfer <[email protected]>

The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in designware idmac controller, which is identical to the one found in the mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it deals with sending stop commands in hardware which makes it significantly different from the mmc-dw devices.

HdG: Various cleanups and fixes.

Signed-off-by David Lanzend?rfer <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

[snip]

drivers/mmc/host/sunxi-mmc.c line 621

Quoted 6 lines

drivers/mmc/host/sunxi-mmc.c new file +6 -0

+
+static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
+                                 struct mmc_ios *ios)
+{
+       u32 rate, oclk_dly, rval, sclk_dly, src_clk;
+       struct clk_hw *hw = __clk_get_hw(host->clk_mmc);

Hi Hans,

Quoted 3 lines

This seems like the wrong approach. But I guess it's related to the "clock phase control" API you have been discussing with the clk maintainer, Mike Turquette!?

Yes, this is meant as a temporary solution until we get a proper "clock phase control" API.

Quoted 63 lines

__clk_get_hw is supposed to be used by clk providers, not clk consumers.

Quoted 57 lines

drivers/mmc/host/sunxi-mmc.c new file +57 -0

+       int ret;
+
+       rate = clk_round_rate(host->clk_mmc, ios->clock);
+       dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
+               ios->clock, rate);
+
+       /* setting clock rate */
+       ret = clk_set_rate(host->clk_mmc, rate);
+       if (ret) {
+               dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
+                       rate, ret);
+               return ret;
+       }
+
+       ret = sunxi_mmc_oclk_onoff(host, 0);
+       if (ret)
+               return ret;
+
+       /* clear internal divider */
+       rval = mmc_readl(host, REG_CLKCR);
+       rval &= ~0xff;
+       mmc_writel(host, REG_CLKCR, rval);
+
+       /* determine delays */
+       if (rate <= 400000) {
+               oclk_dly = 0;
+               sclk_dly = 7;
+       } else if (rate <= 25000000) {
+               oclk_dly = 0;
+               sclk_dly = 5;
+       } else if (rate <= 50000000) {
+               if (ios->timing == MMC_TIMING_UHS_DDR50) {
+                       oclk_dly = 2;
+                       sclk_dly = 4;
+               } else {
+                       oclk_dly = 3;
+                       sclk_dly = 5;
+               }
+       } else {
+               /* rate > 50000000 */
+               oclk_dly = 2;
+               sclk_dly = 4;
+       }
+
+       src_clk = clk_get_rate(clk_get_parent(host->clk_mmc));
+       if (src_clk >= 300000000 && src_clk <= 400000000) {
+               if (oclk_dly)
+                       oclk_dly--;
+               if (sclk_dly)
+                       sclk_dly--;
+       }
+
+       clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
+
+       return sunxi_mmc_oclk_onoff(host, 1);
+}
+

[snip]

Quoted 8 lines

Quoted 1 line

Besides the above, I think this looks good!

Thanks!

Since Mike Turquette has already merged clk_sunxi_mmc_phase_control I would like to keep this as is, as I already promised Mike, I can safely promise you too: I promise clean this up as soon as the "clock phase control" API has been worked out.

Thanks for promise. :-)

Anyway, I think I would like Mike to confirm this violation is accepted as a temporary solution. Additionally I would like it to be commented in the code here, that it's a temporary solution and that it violates the clk API.

Hi All,

Here is v12 of the sunxi-mmc patch-set David Lanzend?rfer and I have been working on, the mmc driver itself is unchanged from v11. New this version are some dts patch changes, see below.

The first patch in this series is the patch adding the actual mmc driver and should go in through the mmc tree.

All the other patches are devicetree patches adding / using the new fixed reg_vcc3v3 supply to all sunxi board files, and should go upstream through Maxime's sunxi-dts tree.