powerpc/mpc85xx: 32bit DDR changes for P1020/P1011
PATCH 1/1 powerpc/mpc85xx: 32bit DDR changes for P1020/P1011
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit.
Add dynamic DDR size adjustment in second stage boot loader execution.
--- arch/powerpc/cpu/mpc85xx/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
arch/powerpc/cpu/mpc85xx/cpu.c +6 -1
@@ -347,7 +347,12 @@ phys_size_t initdram(int board_type)defined (CONFIG_QEMU_E500) return fsl_ddr_sdram_size();#else -return (phys_size_t )CONFIG_SYS_SDRAM_SIZE *1024 *1024 ; +struct cpu_type *cpu = gd->arch.cpu; +/* P1020 and it's derivatives support max 32bit DDR width */ +if (cpu->soc_ver ==SVR_P1020 || cpu->soc_ver ==SVR_P1011 ) +return CONFIG_SYS_SDRAM_SIZE *1024 *1024 /2 ; +else +return CONFIG_SYS_SDRAM_SIZE *1024 *1024 ;#endif }#else /* CONFIG_SYS_RAMBOOT */
Signature · 1 line
1.7.9.5
PATCH 1/1 powerpc/mpc85xx: 32bit DDR changes for P1020/P1011
Quoted 19 lines · Prabhakar Kushwaha
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit.
Add dynamic DDR size adjustment in second stage boot loader execution.
Signed-off-by Prabhakar Kushwaha <[email protected]>--- arch/powerpc/cpu/mpc85xx/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)arch/powerpc/cpu/mpc85xx/cpu.c +0
-0@@ -347,7 +347,12 @@ phys_size_t initdram(int board_type)defined (CONFIG_QEMU_E500) return fsl_ddr_sdram_size();#else
arch/powerpc/cpu/mpc85xx/cpu.c phys_size_t initdram(int board_type) · line 358
Quoted 10 lines
arch/powerpc/cpu/mpc85xx/cpu.c +6
-1-return (phys_size_t )CONFIG_SYS_SDRAM_SIZE *1024 *1024 ; +struct cpu_type *cpu = gd->arch.cpu; +/* P1020 and it's derivatives support max 32bit DDR width */ +if (cpu->soc_ver ==SVR_P1020 || cpu->soc_ver ==SVR_P1011 ) +return CONFIG_SYS_SDRAM_SIZE *1024 *1024 /2 ; +else +return CONFIG_SYS_SDRAM_SIZE *1024 *1024 ;#endif }#else /* CONFIG_SYS_RAMBOOT */
Prabhakar,
The second stage boot loader doesn't re-initialize DDR, right? The size should come from either fsl_ddr_sdram_size() or the predefined macro CONFIG_SYS_SDRAM_SIZE. It looks like you are modifying the predefiend one. Is this what you want? If so, why don't you defined the macro with correct value?
York