enable Hisilicon HIX5HD2 SoC

Changelog:
v5:
* Use CPU_OF_DECLARE_METHOD().
* State "hisilicon,cpuctrl" in documents.
* Set PL310 L2 aux value in machine descriptor.
* Use enable-method property for smp in dts file.
* Move reset code from machine platform driver into power reset driver.
* Move HIP04 debug uart into another patch series.

v4:
* Move CONFIG_ARCH_HISI from HiP04 SoC patch series to here.
* Rename x5hd2. Always use HIX5HD2 or hix5hd2 instead.
* Move HIP04 debug uart into this patch series.

v3:
* Clean in headsmp.S.
* Remove CONFIG_ARCH_HIX5HD2 in Makefile for headsmp.o. Use CONFIG_SMP instead.

v2:
* Add document on DT binding.
* Clean DTS file.
* Avoid to parse DT binding in restart function.
* Fix the hotplug issue.
* Remove hardcoding in platsmp.

Haifeng Yan (3):
ARM: debug: Rename Hi3716 to HI5XHD2
ARM: hisi: enable hix5hd2 SoC
ARM: dts: Add hix5hd2-dkb dts file.

Haojian Zhuang (5):
ARM: hisi: add ARCH_HISI
power: reset: move hisilicon reboot code
ARM: config: enable ARCH_HIX5HD2
ARM: hisi: set l2 aux for pl310
ARM: hisi: remove smp from machine descriptor

 .../bindings/arm/hisilicon/hisilicon.txt           |  11 ++
 arch/arm/Kconfig.debug                             |  12 +-
 arch/arm/Makefile                                  |   2 +-
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/hi3620.dtsi                      |   1 +
 arch/arm/boot/dts/hix5hd2-dkb.dts                  |  53 +++++++
 arch/arm/boot/dts/hix5hd2.dtsi                     | 170 +++++++++++++++++++++
 arch/arm/configs/hi3xxx_defconfig                  |   2 +
 arch/arm/configs/multi_v7_defconfig                |   1 +
 arch/arm/mach-hisi/Kconfig                         |  30 +++-
 arch/arm/mach-hisi/Makefile                        |   2 +-
 arch/arm/mach-hisi/core.h                          |   5 +
 arch/arm/mach-hisi/headsmp.S                       |  16 ++
 arch/arm/mach-hisi/hisilicon.c                     |  47 ++----
 arch/arm/mach-hisi/hotplug.c                       |  58 +++++++
 arch/arm/mach-hisi/platsmp.c                       |  53 ++++++-
 drivers/power/reset/Kconfig                        |   6 +
 drivers/power/reset/Makefile                       |   1 +
 drivers/power/reset/hisi-reboot.c                  |  67 ++++++++
 19 files changed, 494 insertions(+), 44 deletions(-)
 create mode 100644 arch/arm/boot/dts/hix5hd2-dkb.dts
 create mode 100644 arch/arm/boot/dts/hix5hd2.dtsi
 create mode 100644 arch/arm/mach-hisi/headsmp.S
 create mode 100644 drivers/power/reset/hisi-reboot.c

1.9.1

From: Haifeng Yan <[email protected]>

Rename Hisilicon HI3716 to HI5XHD2. And it relies on ARCH_HI5XHD2 instead.

Hi5XHD2 is a SoC with dual Cortex A9 cores.

---
 arch/arm/Kconfig.debug | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

index 8f90595..d061de0 100644
@@ -223,6 +223,14 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on HI3716 UART.
 
+	config DEBUG_HIX5HD2_UART
+		bool "Hisilicon Hix5hd2 Debug UART"
+		depends on ARCH_HIX5HD2
+		select DEBUG_UART_PL01X
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on Hix5hd2 UART.
+
 	config DEBUG_HIGHBANK_UART
 		bool "Kernel low-level debugging messages via Highbank UART"
 		depends on ARCH_HIGHBANK

@@ -1092,7 +1100,7 @@ config DEBUG_UART_PHYS
 	default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
 				ARCH_ORION5X
 	default 0xf7fc9000 if DEBUG_BERLIN_UART
-	default 0xf8b00000 if DEBUG_HI3716_UART
+	default 0xf8b00000 if DEBUG_HIX5HD2_UART
 	default 0xf991e000 if DEBUG_QCOM_UARTDM
 	default 0xfcb00000 if DEBUG_HI3620_UART
 	default 0xfe800000 if ARCH_IOP32X

@@ -1144,7 +1152,7 @@ config DEBUG_UART_VIRT
 	default 0xfe230000 if DEBUG_PICOXCELL_UART
 	default 0xfe300000 if DEBUG_BCM_KONA_UART
 	default 0xfe800000 if ARCH_IOP32X
-	default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART
+	default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
 	default 0xfeb24000 if DEBUG_RK3X_UART0
 	default 0xfeb26000 if DEBUG_RK3X_UART1
 	default 0xfeb30c00 if DEBUG_KEYSTONE_UART0

1.9.1

Since multiple ARCH configuration will be appended into mach-hisi directory, add ARCH_HISI as common configuration for different ARCH in mach-hisi.

---
 arch/arm/Makefile          |  2 +-
 arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++--
 2 files changed, 15 insertions(+), 3 deletions(-)

index 6721fab..2024f5e 100644
@@ -156,7 +156,7 @@ machine-$(CONFIG_ARCH_EP93XX)		+= ep93xx
 machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
 machine-$(CONFIG_ARCH_GEMINI)		+= gemini
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
-machine-$(CONFIG_ARCH_HI3xxx)		+= hisi
+machine-$(CONFIG_ARCH_HISI)		+= hisi
 machine-$(CONFIG_ARCH_INTEGRATOR)	+= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		+= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)		+= iop32x

index feee4db..da16efd 100644
@@ -1,8 +1,16 @@
-config ARCH_HI3xxx
-	bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+config ARCH_HISI
+	bool "Hisilicon SoC Support"
+	depends on ARCH_MULTIPLATFORM
 	select ARM_AMBA
 	select ARM_GIC
 	select ARM_TIMER_SP804
+
+if ARCH_HISI
+
+menu "Hisilicon platform type"
+
+config ARCH_HI3xxx
+	bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
 	select CACHE_L2X0
 	select HAVE_ARM_SCU if SMP
 	select HAVE_ARM_TWD if SMP

@@ -10,3 +18,7 @@ config ARCH_HI3xxx
 	select PINCTRL_SINGLE
 	help
 	  Support for Hisilicon Hi36xx/Hi37xx processor family
+
+endmenu
+
+endif

1.9.1

From: Haifeng Yan <[email protected]>

Enable Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series support both one core or dual cores. The core is Cortex A9.

---
 .../bindings/arm/hisilicon/hisilicon.txt           | 11 ++++
 arch/arm/mach-hisi/Kconfig                         | 13 ++++-
 arch/arm/mach-hisi/Makefile                        |  2 +-
 arch/arm/mach-hisi/core.h                          |  5 ++
 arch/arm/mach-hisi/headsmp.S                       | 16 ++++++
 arch/arm/mach-hisi/hisilicon.c                     | 12 +++++
 arch/arm/mach-hisi/hotplug.c                       | 58 ++++++++++++++++++++++
 arch/arm/mach-hisi/platsmp.c                       | 50 +++++++++++++++++--
 8 files changed, 161 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/mach-hisi/headsmp.S

index df0a452..934f000 100644
@@ -31,6 +31,17 @@ Example:
 		reboot-offset = <0x4>;
 	};
 
+-----------------------------------------------------------------------
+Hisilicon CPU controller
+
+Required properties:
+- compatible : "hisilicon,cpuctrl"
+- reg : Register address and size
+
+The clock registers and power registers of secondary cores are defined
+in CPU controller, especially in HIX5HD2 SoC.
+
+-----------------------------------------------------------------------
 PCTRL: Peripheral misc control register
 
 Required Properties:

index da16efd..90fdbb4 100644
@@ -10,15 +10,24 @@ if ARCH_HISI
 menu "Hisilicon platform type"
 
 config ARCH_HI3xxx
-	bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+	bool "Hisilicon Hi36xx family" if ARCH_MULTI_V7
 	select CACHE_L2X0
 	select HAVE_ARM_SCU if SMP
 	select HAVE_ARM_TWD if SMP
 	select PINCTRL
 	select PINCTRL_SINGLE
 	help
-	  Support for Hisilicon Hi36xx/Hi37xx processor family
+	  Support for Hisilicon Hi36xx SoC family
 
+config ARCH_HIX5HD2
+	bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
+	select CACHE_L2X0
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select PINCTRL
+	select PINCTRL_SINGLE
+	help
+	  Support for Hisilicon HIX5HD2 SoC family
 endmenu
 
 endif

index 2ae1b59..ee2506b 100644
@@ -3,4 +3,4 @@
 #
 
 obj-y	+= hisilicon.o
-obj-$(CONFIG_SMP)		+= platsmp.o hotplug.o
+obj-$(CONFIG_SMP)		+= platsmp.o hotplug.o headsmp.o

index af23ec2..88b1f48 100644
@@ -12,4 +12,9 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
 extern int hi3xxx_cpu_kill(unsigned int cpu);
 extern void hi3xxx_set_cpu(int cpu, bool enable);
 
+extern void hix5hd2_secondary_startup(void);
+extern struct smp_operations hix5hd2_smp_ops;
+extern void hix5hd2_set_cpu(int cpu, bool enable);
+extern void hix5hd2_cpu_die(unsigned int cpu);
+
 #endif

new file mode 100644
index 0000000..278889c
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (c) 2014 Hisilicon Limited.
+ *  Copyright (c) 2014 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__CPUINIT
+
+ENTRY(hix5hd2_secondary_startup)
+	bl	v7_invalidate_l1
+	b	secondary_startup

index 741faf3..2bfbe3f 100644
@@ -88,3 +88,15 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.smp		= smp_ops(hi3xxx_smp_ops),
 	.restart	= hi3xxx_restart,
 MACHINE_END
+
+static const char *hix5hd2_compat[] __initconst = {
+	"hisilicon,hix5hd2",
+	NULL,
+};
+
+DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
+	.dt_compat	= hix5hd2_compat,
+	.init_late	= hi3xxx_init_late,
+	.smp		= smp_ops(hix5hd2_smp_ops),
+	.restart	= hi3xxx_restart,
+MACHINE_END

1.9.1

From: Haifeng Yan <[email protected]>

Add dts file for Hisilicon x5hd2 development kit board.

---
 arch/arm/boot/dts/Makefile        |   1 +
 arch/arm/boot/dts/hix5hd2-dkb.dts |  52 ++++++++++++
 arch/arm/boot/dts/hix5hd2.dtsi    | 170 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 223 insertions(+)
 create mode 100644 arch/arm/boot/dts/hix5hd2-dkb.dts
 create mode 100644 arch/arm/boot/dts/hix5hd2.dtsi

index 5986ff6..721525e 100644
@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
 	exynos5440-ssdk5440.dtb \
 	exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
+dtb-$(CONFIG_ARCH_HIX5HD2) += hix5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
 	ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \

1.9.1

Move reboot code from hisilicon platform driver into reset driver.

---
 arch/arm/mach-hisi/Kconfig        |  3 ++
 arch/arm/mach-hisi/hisilicon.c    | 33 -------------------
 drivers/power/reset/Kconfig       |  6 ++++
 drivers/power/reset/Makefile      |  1 +
 drivers/power/reset/hisi-reboot.c | 67 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 77 insertions(+), 33 deletions(-)
 create mode 100644 drivers/power/reset/hisi-reboot.c

index 90fdbb4..9848829 100644
@@ -4,6 +4,9 @@ config ARCH_HISI
 	select ARM_AMBA
 	select ARM_GIC
 	select ARM_TIMER_SP804
+	select POWER_RESET
+	select POWER_RESET_HISI
+	select POWER_SUPPLY
 
 if ARCH_HISI
 

index 2bfbe3f..7996c6b 100644
@@ -14,10 +14,6 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-
-#include <asm/proc-fns.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

@@ -51,32 +47,6 @@ static void __init hi3620_map_io(void)
 	iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
 }
 
-static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
-{
-	struct device_node *np;
-	void __iomem *base;
-	int offset;
-
-	np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
-	if (!np) {
-		pr_err("failed to find hisilicon,sysctrl node\n");
-		return;
-	}
-	base = of_iomap(np, 0);
-	if (!base) {
-		pr_err("failed to map address in hisilicon,sysctrl node\n");
-		return;
-	}
-	if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
-		pr_err("failed to find reboot-offset property\n");
-		return;
-	}
-	writel_relaxed(0xdeadbeef, base + offset);
-
-	while (1)
-		cpu_do_idle();
-}
-
 static const char *hi3xxx_compat[] __initconst = {
 	"hisilicon,hi3620-hi4511",
 	NULL,

@@ -86,7 +56,6 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.map_io		= hi3620_map_io,
 	.dt_compat	= hi3xxx_compat,
 	.smp		= smp_ops(hi3xxx_smp_ops),
-	.restart	= hi3xxx_restart,
 MACHINE_END
 
 static const char *hix5hd2_compat[] __initconst = {

@@ -96,7 +65,5 @@ static const char *hix5hd2_compat[] __initconst = {
 
 DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
 	.dt_compat	= hix5hd2_compat,
-	.init_late	= hi3xxx_init_late,
 	.smp		= smp_ops(hix5hd2_smp_ops),
-	.restart	= hi3xxx_restart,
 MACHINE_END

index bdcf517..4127f49 100644
@@ -28,6 +28,12 @@ config POWER_RESET_GPIO
 	  If your board needs a GPIO high/low to power down, say Y and
 	  create a binding in your devicetree.
 
+config POWER_RESET_HISI
+	bool "Hisilicon power-off driver"
+	depends on POWER_RESET && ARCH_HISI
+	help
+	  Reboot support for Hisilicon boards.
+
 config POWER_RESET_MSM
 	bool "Qualcomm MSM power-off driver"
 	depends on POWER_RESET && ARCH_QCOM

index dde2e8b..fe0f228 100644
@@ -1,6 +1,7 @@
 obj-$(CONFIG_POWER_RESET_AS3722) += as3722-poweroff.o
 obj-$(CONFIG_POWER_RESET_AXXIA) += axxia-reset.o
 obj-$(CONFIG_POWER_RESET_GPIO) += gpio-poweroff.o
+obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
 obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
 obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o

1.9.1

Hi,

Since both ARCH_HI3xxx and ARCH_HIX5HD2 are based on Cortex A9 & they're using similiar kernel features, make them share the hi3xxx_config.

And add it into multi_v7_defconfig too.

---
 arch/arm/configs/hi3xxx_defconfig   | 2 ++
 arch/arm/configs/multi_v7_defconfig | 1 +
 2 files changed, 3 insertions(+)

index f186bdf..9630687 100644
@@ -3,7 +3,9 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_RD_LZMA=y
+CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
+CONFIG_ARCH_HIX5HD2=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y

index e2d6204..d34ab30 100644
@@ -25,6 +25,7 @@ CONFIG_MACH_BERLIN_BG2CD=y
 CONFIG_MACH_BERLIN_BG2Q=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HI3xxx=y
+CONFIG_ARCH_HIX5HD2=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_IMX51_DT=y

1.9.1

Enable L2 aux value for both HI3xxx and HIX5HD2.

---
 arch/arm/mach-hisi/hisilicon.c | 4 ++++
 1 file changed, 4 insertions(+)

index 7996c6b..284f9a1 100644
@@ -55,6 +55,8 @@ static const char *hi3xxx_compat[] __initconst = {
 DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.map_io		= hi3620_map_io,
 	.dt_compat	= hi3xxx_compat,
+	.l2c_aux_val	= 0x0,
+	.l2c_aux_mask	= 0xffffffff,
 	.smp		= smp_ops(hi3xxx_smp_ops),
 MACHINE_END
 

@@ -65,5 +67,7 @@ static const char *hix5hd2_compat[] __initconst = {
 
 DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
 	.dt_compat	= hix5hd2_compat,
+	.l2c_aux_val	= 0x00050000,
+	.l2c_aux_mask	= 0xfff0ffff,
 	.smp		= smp_ops(hix5hd2_smp_ops),
 MACHINE_END

1.9.1

Enable L2 aux value for Hi3620.

Changelog:
v6:
* Remove L2 aux value of hix5hd2 since we still need some discussion.

---
 arch/arm/mach-hisi/hisilicon.c | 2 ++
 1 file changed, 2 insertions(+)

index 7996c6b..5c295ee 100644
@@ -55,6 +55,8 @@ static const char *hi3xxx_compat[] __initconst = {
 DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.map_io		= hi3620_map_io,
 	.dt_compat	= hi3xxx_compat,
+	.l2c_aux_val	= 0x0,
+	.l2c_aux_mask	= 0xffffffff,
 	.smp		= smp_ops(hi3xxx_smp_ops),
 MACHINE_END
 

1.9.1

Use CPU_METHOD_OF_DECLARE() instead. And declare smp method in dts file.

---
 arch/arm/boot/dts/hi3620.dtsi     | 1 +
 arch/arm/boot/dts/hix5hd2-dkb.dts | 1 +
 arch/arm/mach-hisi/hisilicon.c    | 4 ----
 arch/arm/mach-hisi/platsmp.c      | 3 +++
 4 files changed, 5 insertions(+), 4 deletions(-)

index ab1116d..ea6b0c1 100644
@@ -33,6 +33,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "hisilicon,hi3xxx-smp";
 
 		cpu at 0 {
 			device_type = "cpu";

index 32c7fd1..556c98a 100644
@@ -21,6 +21,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "hisilicon,hix5hd2-smp";
 
 		cpu at 0 {
 			compatible = "arm,cortex-a9";

index 284f9a1..2544d84 100644
@@ -18,8 +18,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "core.h"
-
 #define HI3620_SYSCTRL_PHYS_BASE		0xfc802000
 #define HI3620_SYSCTRL_VIRT_BASE		0xfe802000
 

@@ -57,7 +55,6 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.dt_compat	= hi3xxx_compat,
 	.l2c_aux_val	= 0x0,
 	.l2c_aux_mask	= 0xffffffff,
-	.smp		= smp_ops(hi3xxx_smp_ops),
 MACHINE_END
 
 static const char *hix5hd2_compat[] __initconst = {

@@ -69,5 +66,4 @@ DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
 	.dt_compat	= hix5hd2_compat,
 	.l2c_aux_val	= 0x00050000,
 	.l2c_aux_mask	= 0xfff0ffff,
-	.smp		= smp_ops(hix5hd2_smp_ops),
 MACHINE_END

index ecf7058..cc377b6 100644
@@ -131,3 +131,6 @@ struct smp_operations hix5hd2_smp_ops __initdata = {
 	.cpu_die		= hix5hd2_cpu_die,
 #endif
 };
+
+CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3xxx-smp", &hi3xxx_smp_ops);
+CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);

1.9.1

Please always use a specific chip identification in strings like this, e.g. "hisilicon,hi3620-smp". Other machines using the same code are supposed to keep that string as well even if they have a different ID.

Arnd

Use CPU_METHOD_OF_DECLARE() instead. And declare smp method in dts file.

Changelog:
v6:
* Use hisilicon,hi3620-smp as enable-method property in Hi3620 dts.

---
 arch/arm/boot/dts/hi3620.dtsi     | 1 +
 arch/arm/boot/dts/hix5hd2-dkb.dts | 1 +
 arch/arm/mach-hisi/hisilicon.c    | 4 ----
 arch/arm/mach-hisi/platsmp.c      | 3 +++
 4 files changed, 5 insertions(+), 4 deletions(-)

index ab1116d..a7b0d3d 100644
@@ -33,6 +33,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "hisilicon,hi3620-smp";
 
 		cpu at 0 {
 			device_type = "cpu";

index 32c7fd1..556c98a 100644
@@ -21,6 +21,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "hisilicon,hix5hd2-smp";
 
 		cpu at 0 {
 			compatible = "arm,cortex-a9";

index 5c295ee..f37fb65 100644
@@ -18,8 +18,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "core.h"
-
 #define HI3620_SYSCTRL_PHYS_BASE		0xfc802000
 #define HI3620_SYSCTRL_VIRT_BASE		0xfe802000
 

@@ -57,7 +55,6 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.dt_compat	= hi3xxx_compat,
 	.l2c_aux_val	= 0x0,
 	.l2c_aux_mask	= 0xffffffff,
-	.smp		= smp_ops(hi3xxx_smp_ops),
 MACHINE_END
 
 static const char *hix5hd2_compat[] __initconst = {

@@ -67,5 +64,4 @@ static const char *hix5hd2_compat[] __initconst = {
 
 DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
 	.dt_compat	= hix5hd2_compat,
-	.smp		= smp_ops(hix5hd2_smp_ops),
 MACHINE_END

index ecf7058..575dd82 100644
@@ -131,3 +131,6 @@ struct smp_operations hix5hd2_smp_ops __initdata = {
 	.cpu_die		= hix5hd2_cpu_die,
 #endif
 };
+
+CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
+CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);

1.9.1

Looks ok for the most part. I have a trivial comment on patch 8/8, please correct that.

The comment on patch 7/8 is more severe. Depending on the hardware requirements, this may end up being much harder to fix, but it needs some discussion. Adding the values only for hi3620 in the meantime should be ok.

Arnd

OK. I'll remove the l2c aux value of hix5hd2 on patch 7/8. And I'll use hi3620-smp in patch 8/8.

Regards
Haojian

Usually there's some more description in the cover letter than just the changelog.

Anyway, my question is this: what's the plan for upstreaming of this SoC? Is it a mobile-only SoC, or has it been used (or will it be used) in other embedded use cases, public development boards and the like?

If it is a mobile-targeted product, what is the plan and rough timeline for upstreaming things such as display/graphics and power management components?

Thanks!

-Olof

Hi Olof,

HiX5HD2 is for the STB market.
Hisilicon has already made some public development boards for Linaro and hope it could be used in Linaro Home Group.
And if you are interesting about it, we could send one to you.

There are several phases for upstreaming of this SoC.
At the first phase, it includes the basic SoC(earlycon, gic, timer, L2 cache, SMP and reboot), net, emc, USB and clock.

About the display/graphics/video/audio, we are still discussing how to upstream. There are two limitations. One is the code we have now does not adapt with kernel. The other is the policy of company which part is allowed to upstream.

But anyway, we hope we could do upstreaming.

Best Regards,
Wei

Hi,

I am mostly asking because I want to get a feel for whether you will complete upstreaming, or just upstream the minimal set of platform support that won't actually be useful for anyone (like with what's already in the tree).

For a STB chip, display is critical. Do you have a DRM driver planned?

This sounds odd. Are they shipping this chip in products today? If so, they already have to publish GPL sources, so "allowed" to upstream is a very odd limitation.

Ok. I would very much like to see successful upstreaming of hisilicon platforms to happen, but the track record so far hasn't been very promising. If you think you'll get all the way and make the platform useful, then that's a great sign. I am very concerned about lack of graphics plans though.

Thanks,

-Olof

Now Android is deployed on this platform. They're also investigating DRM driver. I think that Android on DRM driver should be resolved first. Maybe Linaro LHG is investigating it.

At first we want to upstream all the components. But we have to be step by step.

https://github.com/hisilicon/linaro-kernel/commits/xjc/hix5hd2-lsk-3.10-msp

Display, Irda, i2c, mmc, sata, and some other drivers are already contained in this public git repository. If HIX5HD2 SoC could be upstream, all these driver should also be upstream. Some drivers are not mature, we still need to modify them in the process of upstream.

Best Regards
Haojian

Hi Olof,

I know what you are concerned.
We indeed want to complete upstreaming.
Because we also could not get any profit from the minimal set. We have already set up a team for upstreaming.

About the DRM driver, we are still changing the source code. Once it is done, we will start upstreaming it.

Yes. There are already some companies use this SoC on their product. We follow the GPL licenses and the sources are open for our clients. And the "allowed" here means it depend on the strategy of our company how many parts to upstream.

And as the info in Haojian's reply, we are pushing the usptreaming.

Best Regards,
Wei