Adds PMU and S2R support for exynos5420
Subsystems (6)
v4 cover Adds PMU and S2R support for exynos5420
Rebased on
1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch) merged.
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v4 PMU patchset
https://lkml.org/lkml/2014/5/10/29
Pankaj's patches have the following dependencies:
[1] mfd: syscon: Support early initialization https://lkml.org/lkml/2014/4/8/239 [2] Daniel Lezcano's Exynos cpuidle refactor patches http://thread.gmane.org/gmane.linux.kernel.samsung-soc/29085 [3] Allow NULL property in syscon_early_regmap_lookup_by_phandle https://lkml.org/lkml/2014/5/10/10 and https://lkml.org/lkml/2014/4/29/661
Note: Some of the above patches did not apply cleanly on Kgene's for-next branch.
changes since v3:
Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz, Tomasz Figa and Alim Akhtar:
- Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h.
- Merged exynos5420_set_core_flag function into powerdown_conf.
- Removed XXTI_DURATION3 register setting.
- Updated the commit message and ordered the clock registers in clock patch.
- Removed the code for SYS_DISP1_BLK_CFG handling.
- Modified SoC checks to A9 specific checks in PM code.
- Updated some comments in the code and added macros for register offsets.
- Fixed code which was changing pad retention code for older SoCs.
changes since v2:
- Addressed comments from Tomasz figa
- rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612
- dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420", will be sent separately.
changes since v1:
- Addressed comments from Tomasz figa.
- restructured/consolidated as per Tomasz figa's PM consolidations for exynos
Tested on Exynos5420 and Exynos5250 based chromebooks (peach-pit and snow).
Abhilash Kesavan (4):
arm: exynos5: Add PMU support for 5420
arm: exynos: Modify code to check for cortex A9 rather than the SoC
arm: exynos5: Add Suspend-to-RAM support for 5420
clk: samsung: exynos5420: Setup clocks before system suspend
arch/arm/mach-exynos/exynos.c | 1 + arch/arm/mach-exynos/pm.c | 216 ++++++++++++++++++++--- arch/arm/mach-exynos/pmu.c | 310 ++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/regs-pmu.h | 239 ++++++++++++++++++++++++++ drivers/clk/samsung/clk-exynos5420.c | 25 +++ 5 files changed, 769 insertions(+), 22 deletions(-)
Signature · 1 line
1.7.9.5
PATCH v4 1/4 arm: exynos5: Add PMU support for 5420
Add intial PMU settings for exynos5420. This is required for future S2R and Switching support.
--- arch/arm/mach-exynos/exynos.c | 1 + arch/arm/mach-exynos/pmu.c | 310 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/regs-pmu.h | 238 ++++++++++++++++++++++++++++++ 3 files changed, 549 insertions(+)
arch/arm/mach-exynos/exynos.c +1 -0
@@ -207,6 +207,7 @@ static const struct of_device_id exynos_dt_pmu_match[] = { { .compatible = "samsung,exynos4212-pmu" }, { .compatible = "samsung,exynos4412-pmu" }, { .compatible = "samsung,exynos5250-pmu" }, + { .compatible = "samsung,exynos5420-pmu" }, {}, };
arch/arm/mach-exynos/pmu.c +310 -0
352 lines not on this page · raw message
arch/arm/mach-exynos/regs-pmu.h +238 -0
260 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH v4 2/4 arm: exynos: Modify code to check for cortex A9 rather than the SoC
In reply to Abhilash KesavanWe have an soc check to ensure that the scu and certain A9 specific registers are not accessed on Exynos5250 (which is A15 based).
Rather than adding another soc specific check for 5420 let us test for the Cortex A9 primary part number.
--- arch/arm/mach-exynos/pm.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-)
arch/arm/mach-exynos/pm.c +9 -6
@@ -248,7 +248,7 @@ static int exynos_pm_suspend(void) tmp = (S5P_USE_STANDBY_WFI0 |S5P_USE_STANDBY_WFE0 );regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , tmp); -if (!soc_is_exynos5250 ()) +if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 )exynos_cpu_save_register ();return 0 ;
@@ -282,7 +282,7 @@ static void exynos_pm_resume(void)if (exynos_pm_central_resume ()) goto early_wakeup; -if (!soc_is_exynos5250 ()) +if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 )exynos_cpu_restore_register ();/* For release retention */
@@ -301,7 +301,7 @@ static void exynos_pm_resume(void)s3c_pm_do_restore_core (exynos_core_save,ARRAY_SIZE (exynos_core_save)); -if (!soc_is_exynos5250 ()) +if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 )scu_enable (S5P_VA_SCU ); early_wakeup:
@@ -388,15 +388,18 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self,case CPU_PM_ENTER :if (cpu ==0 ) {exynos_pm_central_suspend (); -exynos_cpu_save_register (); +if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 ) +exynos_cpu_save_register (); }break ;case CPU_PM_EXIT :if (cpu ==0 ) { -if (!soc_is_exynos5250 ()) +if (read_cpuid_part_number () == +ARM_CPU_PART_CORTEX_A9 ) {scu_enable (S5P_VA_SCU ); -exynos_cpu_restore_register (); +exynos_cpu_restore_register (); + }exynos_pm_central_resume (); }break ;
Signature · 1 line
1.7.9.5
PATCH v4 3/4 arm: exynos5: Add Suspend-to-RAM support for 5420
In reply to Abhilash KesavanAdds Suspend-to-RAM support for EXYNOS5420
--- arch/arm/mach-exynos/pm.c | 201 +++++++++++++++++++++++++++++++++++---- arch/arm/mach-exynos/regs-pmu.h | 1 + 2 files changed, 186 insertions(+), 16 deletions(-)
arch/arm/mach-exynos/pm.c +185 -16
@@ -22,6 +22,7 @@#include <linux/err.h> #include <linux/clk.h> #include <linux/regmap.h> +#include <linux/of_address.h> #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h>
@@ -39,7 +40,13 @@#include "regs-sys.h" #include "exynos-pmu.h" +#define EXYNOS5420_CPU_ADDR 0x1c +#define EXYNOS5420_CPU_STATE 0x28 +static struct regmap *pmu_regmap; +static int exynos5420_cpu_state[2 ]; +static void __iomem *exynos5420_sysram_base; +static void __iomem *exynos5420_ns_sysram_base;/** * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
@@ -64,6 +71,10 @@ static struct sleep_save exynos_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; +static struct sleep_save exynos5420_pmu_reg_save[] = { +SAVE_ITEM ((void __iomem *)S5P_PMU_SPARE3 ), +}; +/* * GIC wake-up support */
@@ -86,7 +97,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) {const struct exynos_wkup_irq *wkup_irq; -if (soc_is_exynos5250 ()) +if (soc_is_exynos5250 () ||soc_is_exynos5420 ()) wkup_irq = exynos5250_wkup_irq;else wkup_irq = exynos4_wkup_irq;
@@ -187,7 +198,16 @@ static int exynos_cpu_suspend(unsigned long arg)outer_flush_all ();#endif -if (soc_is_exynos5250 ()) +/* +* Clear sysram register for cpu state so that primary CPU does +* not enter low power start in U-Boot. +* This is specific to exynos5420 SoC only. +*/ +if (soc_is_exynos5420 ()) +__raw_writel (0x0 , + exynos5420_sysram_base +EXYNOS5420_CPU_STATE ); + +if (soc_is_exynos5250 () ||soc_is_exynos5420 ())flush_cache_all ();/* issue the standby signal into the pm unit. */
@@ -215,6 +235,24 @@ static void exynos_pm_prepare(void)regmap_read (pmu_regmap,EXYNOS5_JPEG_MEM_OPTION , &tmp); tmp &= ~EXYNOS5_OPTION_USE_RETENTION ;regmap_write (pmu_regmap,EXYNOS5_JPEG_MEM_OPTION , tmp); + }else if (soc_is_exynos5420 ()) { +unsigned int i; + +for (i =0 ; i <ARRAY_SIZE (exynos5420_pmu_reg_save); i++) +regmap_read (pmu_regmap, + (unsigned int )exynos5420_pmu_reg_save[i].reg, + (unsigned int *)&exynos5420_pmu_reg_save[i].val); +/* +* The cpu state needs to be saved and restored so that the +* secondary CPUs will enter low power start. Though the U-Boot +* is setting the cpu state with low power flag, the kernel +* needs to restore it back in case, the primary cpu fails to +* suspend for any reason. +*/ + exynos5420_cpu_state[0 ] = +__raw_readl (exynos5420_sysram_base +EXYNOS5420_CPU_STATE ); + exynos5420_cpu_state[1 ] = +__raw_readl (exynos5420_ns_sysram_base +EXYNOS5420_CPU_ADDR ); }/* Set value of power down register for sleep mode */
@@ -225,6 +263,26 @@ static void exynos_pm_prepare(void)/* ensure at least INFORM0 has the resume address */ regmap_write (pmu_regmap,S5P_INFORM0 ,virt_to_phys (exynos_cpu_resume)); + +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,EXYNOS5_ARM_L2_OPTION , &tmp); + tmp &= ~EXYNOS5_USE_RETENTION ; +regmap_write (pmu_regmap,EXYNOS5_ARM_L2_OPTION , tmp); + +regmap_read (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , &tmp); + tmp |=EXYNOS5420_UFS ; +regmap_write (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , tmp); + +regmap_read (pmu_regmap,EXYNOS5420_ARM_COMMON_OPTION , &tmp); + tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE ; +regmap_write (pmu_regmap,EXYNOS5420_ARM_COMMON_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_FSYS2_OPTION , &tmp); + tmp |=EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_FSYS2_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_PSGEN_OPTION , &tmp); + tmp |=EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_PSGEN_OPTION , tmp); + } }static void exynos_pm_central_suspend (void )
@@ -241,12 +299,22 @@ static int exynos_pm_suspend(void) {unsigned int tmp; +unsigned int this_cluster;exynos_pm_central_suspend ();/* Setting SEQ_OPTION register */ - - tmp = (S5P_USE_STANDBY_WFI0 |S5P_USE_STANDBY_WFE0 ); -regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , tmp); +if (soc_is_exynos5420 ()) { + this_cluster =MPIDR_AFFINITY_LEVEL (read_cpuid_mpidr (),1 ); +if (!this_cluster) +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , +EXYNOS5420_ARM_USE_STANDBY_WFI0 ); +else +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , +EXYNOS5420_KFC_USE_STANDBY_WFI0 ); + }else { + tmp = (S5P_USE_STANDBY_WFI0 |S5P_USE_STANDBY_WFE0 ); +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , tmp); + }if (read_cpuid_part_number () ==ARM_CPU_PART_CORTEX_A9 )exynos_cpu_save_register ();
@@ -279,6 +347,19 @@ static int exynos_pm_central_resume(void)static void exynos_pm_resume (void ) { +unsigned int tmp; + +if (soc_is_exynos5420 ()) { +/* Restore the sysram cpu state register */ +__raw_writel (exynos5420_cpu_state[0 ], + exynos5420_sysram_base +EXYNOS5420_CPU_STATE ); +__raw_writel (exynos5420_cpu_state[1 ], + exynos5420_ns_sysram_base +EXYNOS5420_CPU_ADDR ); + +regmap_write (pmu_regmap,S5P_CENTRAL_SEQ_OPTION , +EXYNOS5420_USE_STANDBY_WFI_ALL ); + } +if (exynos_pm_central_resume ()) goto early_wakeup;
@@ -287,17 +368,54 @@ static void exynos_pm_resume(void)/* For release retention */ -regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); -regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); +if (soc_is_exynos5420 ()) { +regmap_write (pmu_regmap,EXYNOS_PAD_RET_DRAM_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_MAUDIO_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_JTAG_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_GPIO_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_UART_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCA_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCB_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_MMCC_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_HSI_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIA_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS_PAD_RET_EBIB_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_SPI_OPTION , + (1 <<28 )); +regmap_write (pmu_regmap,EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION , + (1 <<28 )); + }else { +regmap_write (pmu_regmap,S5P_PAD_RET_MAUDIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_GPIO_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_UART_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_MMCB_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIA_OPTION , (1 <<28 )); +regmap_write (pmu_regmap,S5P_PAD_RET_EBIB_OPTION , (1 <<28 )); + } -if (soc_is_exynos5250 ()) +if (soc_is_exynos5250 ()) {s3c_pm_do_restore (exynos5_sys_save,ARRAY_SIZE (exynos5_sys_save)); + }else if (soc_is_exynos5420 ()) { +unsigned int i; + +for (i =0 ; i <ARRAY_SIZE (exynos5420_pmu_reg_save); i++) +regmap_write (pmu_regmap, + (unsigned int )exynos5420_pmu_reg_save[i].reg, + (unsigned int )exynos5420_pmu_reg_save[i].val); + }s3c_pm_do_restore_core (exynos_core_save,ARRAY_SIZE (exynos_core_save));
@@ -306,6 +424,18 @@ static void exynos_pm_resume(void) early_wakeup: +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , &tmp); + tmp &= ~EXYNOS5420_UFS ; +regmap_write (pmu_regmap,EXYNOS5420_SFR_AXI_CGDIS1 , tmp); +regmap_read (pmu_regmap,EXYNOS5420_FSYS2_OPTION , &tmp); + tmp &= ~EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_FSYS2_OPTION , tmp); +regmap_read (pmu_regmap,EXYNOS5420_PSGEN_OPTION , &tmp); + tmp &= ~EXYNOS5420_EMULATION ; +regmap_write (pmu_regmap,EXYNOS5420_PSGEN_OPTION , tmp); + } +/* Clear SLEEP mode set in INFORM1 */ regmap_write (pmu_regmap,S5P_INFORM1 ,0x0 );
@@ -414,8 +544,41 @@ static struct notifier_block exynos_cpu_pm_notifier_block = {void __init exynos_pm_init (void ) { +struct device_node *node;u32 tmp; +if (soc_is_exynos5420 ()) { + node =of_find_compatible_node (NULL ,NULL , +"samsung,exynos4210-sysram" ); +if (!node) { +pr_err ("failed to find secure sysram node\n" ); +return ; + } + + exynos5420_sysram_base =of_iomap (node,0 ); +of_node_put (node); +if (!exynos5420_sysram_base) { +pr_err ("failed to map secure sysram base address\n" ); +return ; + } + + node =of_find_compatible_node (NULL ,NULL , +"samsung,exynos4210-sysram-ns" ); +if (!node) { +pr_err ("failed to find non-secure sysram node\n" ); +iounmap (exynos5420_sysram_base); +return ; + } + + exynos5420_ns_sysram_base =of_iomap (node,0 ); +of_node_put (node); +if (!exynos5420_ns_sysram_base) { +pr_err ("failed to map non-secure sysram base address\n" ); +iounmap (exynos5420_sysram_base); +return ; + } + } + pmu_regmap =get_exynos_pmuregmap ();cpu_pm_register_notifier (&exynos_cpu_pm_notifier_block);
@@ -423,9 +586,15 @@ void __init exynos_pm_init(void) gic_arch_extn.irq_set_wake = exynos_irq_set_wake;/* All wakeup disable */ -regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); - tmp |= ((0xFF <<8 ) | (0x1F <<1 )); -regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); +if (soc_is_exynos5420 ()) { +regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); + tmp |= ((0x7F <<7 ) | (0x1F <<1 )); +regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); + }else { +regmap_read (pmu_regmap,S5P_WAKEUP_MASK , &tmp); + tmp |= ((0xFF <<8 ) | (0x1F <<1 )); +regmap_write (pmu_regmap,S5P_WAKEUP_MASK , tmp); + }register_syscore_ops (&exynos_pm_syscore_ops);suspend_set_ops (&exynos_suspend_ops);
arch/arm/mach-exynos/regs-pmu.h +1 -0
@@ -33,6 +33,7 @@#define S5P_INFORM5 0x0814#define S5P_INFORM6 0x0818#define S5P_INFORM7 0x081C +#define S5P_PMU_SPARE3 0x090c#define EXYNOS_IROM_DATA2 0x0988#define S5P_ARM_CORE0_LOWPWR 0x1000
Signature · 1 line
1.7.9.5
PATCH v4 4/4 clk: samsung: exynos5420: Setup clocks before system suspend
In reply to Abhilash KesavanPrior to suspending the system, we need to ensure that certain clock source and gate registers are unmasked.
--- drivers/clk/samsung/clk-exynos5420.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
drivers/clk/samsung/clk-exynos5420.c +25 -0
@@ -28,6 +28,7 @@#define GATE_BUS_CPU 0x700#define GATE_SCLK_CPU 0x800#define CLKOUT_CMU_CPU 0xa00 +#define SRC_MASK_CPERI 0x4300#define GATE_IP_G2D 0x8800#define CPLL_LOCK 0x10020#define DPLL_LOCK 0x10030
@@ -66,6 +67,8 @@#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288 +#define SRC_MASK_TOP0 0x10300 +#define SRC_MASK_TOP1 0x10304#define SRC_MASK_TOP2 0x10308#define SRC_MASK_TOP7 0x1031c#define SRC_MASK_DISP10 0x1032c
@@ -73,6 +76,7 @@#define SRC_MASK_FSYS 0x10340#define SRC_MASK_PERIC0 0x10350#define SRC_MASK_PERIC1 0x10354 +#define SRC_MASK_ISP 0x10370#define DIV_TOP0 0x10500#define DIV_TOP1 0x10504#define DIV_TOP2 0x10508
@@ -91,6 +95,7 @@#define DIV2_RATIO0 0x10590#define DIV4_RATIO 0x105a0#define GATE_BUS_TOP 0x10700 +#define GATE_BUS_DISP1 0x10728#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_FSYS2 0x10748
@@ -115,6 +120,7 @@#define GATE_TOP_SCLK_MAU 0x1083c#define GATE_TOP_SCLK_FSYS 0x10840#define GATE_TOP_SCLK_PERIC 0x10850 +#define GATE_IP_PERIC 0x10950#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110
@@ -222,11 +228,30 @@ static unsigned long exynos5420_clk_regs[] __initdata = { DIV_KFC0, }; +static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { + { .offset =SRC_MASK_CPERI , .value =0xffffffff , }, + { .offset =SRC_MASK_TOP0 , .value =0x11111111 , }, + { .offset =SRC_MASK_TOP1 , .value =0x11101111 , }, + { .offset =SRC_MASK_TOP2 , .value =0x11111110 , }, + { .offset =SRC_MASK_TOP7 , .value =0x00111100 , }, + { .offset =SRC_MASK_DISP10 , .value =0x11111110 , }, + { .offset =SRC_MASK_MAU , .value =0x10000000 , }, + { .offset =SRC_MASK_FSYS , .value =0x11111110 , }, + { .offset =SRC_MASK_PERIC0 , .value =0x11111110 , }, + { .offset =SRC_MASK_PERIC1 , .value =0x11111100 , }, + { .offset =SRC_MASK_ISP , .value =0x11111000 , }, + { .offset =GATE_BUS_DISP1 , .value =0xffffffff , }, + { .offset =GATE_IP_PERIC , .value =0xffffffff , }, +}; +static int exynos5420_clk_suspend (void ) {samsung_clk_save (reg_base, exynos5420_save,ARRAY_SIZE (exynos5420_clk_regs)); +samsung_clk_restore (reg_base, exynos5420_set_clksrc, +ARRAY_SIZE (exynos5420_set_clksrc)); +return 0 ; }
Signature · 1 line
1.7.9.5
PATCH v4 4/4 clk: samsung: exynos5420: Setup clocks before system suspend
Hi Abhilash,
Quoted 74 lines · Abhilash Kesavan
Prior to suspending the system, we need to ensure that certain clock source and gate registers are unmasked.
Signed-off-by Vikas Sajjan <[email protected]>Signed-off-by Abhilash Kesavan <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)drivers/clk/samsung/clk-exynos5420.c +22
-0@@ -28,6 +28,7 @@#define GATE_BUS_CPU 0x700#define GATE_SCLK_CPU 0x800#define CLKOUT_CMU_CPU 0xa00 +#define SRC_MASK_CPERI 0x4300#define GATE_IP_G2D 0x8800#define CPLL_LOCK 0x10020#define DPLL_LOCK 0x10030@@ -66,6 +67,8 @@#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288 +#define SRC_MASK_TOP0 0x10300 +#define SRC_MASK_TOP1 0x10304#define SRC_MASK_TOP2 0x10308#define SRC_MASK_TOP7 0x1031c#define SRC_MASK_DISP10 0x1032c@@ -73,6 +76,7 @@#define SRC_MASK_FSYS 0x10340#define SRC_MASK_PERIC0 0x10350#define SRC_MASK_PERIC1 0x10354 +#define SRC_MASK_ISP 0x10370#define DIV_TOP0 0x10500#define DIV_TOP1 0x10504#define DIV_TOP2 0x10508@@ -91,6 +95,7 @@#define DIV2_RATIO0 0x10590#define DIV4_RATIO 0x105a0#define GATE_BUS_TOP 0x10700 +#define GATE_BUS_DISP1 0x10728#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_FSYS2 0x10748@@ -115,6 +120,7 @@#define GATE_TOP_SCLK_MAU 0x1083c#define GATE_TOP_SCLK_FSYS 0x10840#define GATE_TOP_SCLK_PERIC 0x10850 +#define GATE_IP_PERIC 0x10950#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110@@ -222,11 +228,30 @@ static unsigned long exynos5420_clk_regs[] __initdata = { DIV_KFC0, }; +static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { + { .offset =SRC_MASK_CPERI , .value =0xffffffff , }, + { .offset =SRC_MASK_TOP0 , .value =0x11111111 , }, + { .offset =SRC_MASK_TOP1 , .value =0x11101111 , }, + { .offset =SRC_MASK_TOP2 , .value =0x11111110 , }, + { .offset =SRC_MASK_TOP7 , .value =0x00111100 , }, + { .offset =SRC_MASK_DISP10 , .value =0x11111110 , }, + { .offset =SRC_MASK_MAU , .value =0x10000000 , }, + { .offset =SRC_MASK_FSYS , .value =0x11111110 , }, + { .offset =SRC_MASK_PERIC0 , .value =0x11111110 , }, + { .offset =SRC_MASK_PERIC1 , .value =0x11111100 , }, + { .offset =SRC_MASK_ISP , .value =0x11111000 , }, + { .offset =GATE_BUS_DISP1 , .value =0xffffffff , }, + { .offset =GATE_IP_PERIC , .value =0xffffffff , }, +}; +
drivers/clk/samsung/clk-exynos5420.c static unsigned long exynos5420_clk_regs[] __initdata = { · line 256
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +3
-0static int exynos5420_clk_suspend (void ) {samsung_clk_save (reg_base, exynos5420_save,ARRAY_SIZE (exynos5420_clk_regs)); +samsung_clk_restore (reg_base, exynos5420_set_clksrc, +ARRAY_SIZE (exynos5420_set_clksrc)); +return 0 ; }
Don't you also need to add those registers to normal suspend/resume list, so the values before setting the pre-suspend values are saved on suspend and then restored on resume?
Otherwise looks good.
Best regards,
Tomasz
PATCH v4 4/4 clk: samsung: exynos5420: Setup clocks before system suspend
Hi Tomasz,
Quoted 82 lines · Tomasz Figa
Hi Abhilash,
Quoted 79 lines · Abhilash Kesavan
Prior to suspending the system, we need to ensure that certain clock source and gate registers are unmasked.
Signed-off-by Vikas Sajjan <[email protected]>Signed-off-by Abhilash Kesavan <[email protected]>--- drivers/clk/samsung/clk-exynos5420.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)drivers/clk/samsung/clk-exynos5420.c +22
-0@@ -28,6 +28,7 @@#define GATE_BUS_CPU 0x700#define GATE_SCLK_CPU 0x800#define CLKOUT_CMU_CPU 0xa00 +#define SRC_MASK_CPERI 0x4300#define GATE_IP_G2D 0x8800#define CPLL_LOCK 0x10020#define DPLL_LOCK 0x10030@@ -66,6 +67,8 @@#define SRC_TOP10 0x10280#define SRC_TOP11 0x10284#define SRC_TOP12 0x10288 +#define SRC_MASK_TOP0 0x10300 +#define SRC_MASK_TOP1 0x10304#define SRC_MASK_TOP2 0x10308#define SRC_MASK_TOP7 0x1031c#define SRC_MASK_DISP10 0x1032c@@ -73,6 +76,7 @@#define SRC_MASK_FSYS 0x10340#define SRC_MASK_PERIC0 0x10350#define SRC_MASK_PERIC1 0x10354 +#define SRC_MASK_ISP 0x10370#define DIV_TOP0 0x10500#define DIV_TOP1 0x10504#define DIV_TOP2 0x10508@@ -91,6 +95,7 @@#define DIV2_RATIO0 0x10590#define DIV4_RATIO 0x105a0#define GATE_BUS_TOP 0x10700 +#define GATE_BUS_DISP1 0x10728#define GATE_BUS_GEN 0x1073c#define GATE_BUS_FSYS0 0x10740#define GATE_BUS_FSYS2 0x10748@@ -115,6 +120,7 @@#define GATE_TOP_SCLK_MAU 0x1083c#define GATE_TOP_SCLK_FSYS 0x10840#define GATE_TOP_SCLK_PERIC 0x10850 +#define GATE_IP_PERIC 0x10950#define TOP_SPARE2 0x10b08#define BPLL_LOCK 0x20010#define BPLL_CON0 0x20110@@ -222,11 +228,30 @@ static unsigned long exynos5420_clk_regs[] __initdata = { DIV_KFC0, }; +static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { + { .offset =SRC_MASK_CPERI , .value =0xffffffff , }, + { .offset =SRC_MASK_TOP0 , .value =0x11111111 , }, + { .offset =SRC_MASK_TOP1 , .value =0x11101111 , }, + { .offset =SRC_MASK_TOP2 , .value =0x11111110 , }, + { .offset =SRC_MASK_TOP7 , .value =0x00111100 , }, + { .offset =SRC_MASK_DISP10 , .value =0x11111110 , }, + { .offset =SRC_MASK_MAU , .value =0x10000000 , }, + { .offset =SRC_MASK_FSYS , .value =0x11111110 , }, + { .offset =SRC_MASK_PERIC0 , .value =0x11111110 , }, + { .offset =SRC_MASK_PERIC1 , .value =0x11111100 , }, + { .offset =SRC_MASK_ISP , .value =0x11111000 , }, + { .offset =GATE_BUS_DISP1 , .value =0xffffffff , }, + { .offset =GATE_IP_PERIC , .value =0xffffffff , }, +}; +static int exynos5420_clk_suspend (void ) {samsung_clk_save (reg_base, exynos5420_save,ARRAY_SIZE (exynos5420_clk_regs));
Quoted 9 lines
drivers/clk/samsung/clk-exynos5420.c static unsigned long exynos5420_clk_regs[] __initdata = { · line 256
Quoted 5 lines
drivers/clk/samsung/clk-exynos5420.c +3
-0+samsung_clk_restore (reg_base, exynos5420_set_clksrc, +ARRAY_SIZE (exynos5420_set_clksrc)); +return 0 ; }Don't you also need to add those registers to normal suspend/resume list, so the values before setting the pre-suspend values are saved on suspend and then restored on resume?
Yes, I should do that. Will fix and re-send.
Regards,
Abhilash
Quoted 10 lines
Otherwise looks good.
Best regards,
Tomasz_______________________________________________
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v4 cover Adds PMU and S2R support for exynos5420
In reply to Abhilash KesavanHi Abhilash,
Quoted 7 lines · Abhilash Kesavan
Rebased on
1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch) merged.
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v4 PMU patchset
https://lkml.org/lkml/2014/5/10/29
I think this patch is not safe to base on yet. I need to find time to review the latest version and share my latest view on this with Pankaj, as I have a bit different design in mind.
In general, I don't like the fact that you end up with using regmap to access registers that are used exclusively by PMU driver or for accesses happening at late suspend or early resume, where concurrent accesses from other drivers simply can't occur.
Best regards,
Tomasz
v4 cover Adds PMU and S2R support for exynos5420
Hi Tomasz,
Quoted 11 lines · Tomasz Figa
Hi Abhilash,
Quoted 7 lines · Abhilash Kesavan
Rebased on
1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch) merged.
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v4 PMU patchset
https://lkml.org/lkml/2014/5/10/29
Quoted 3 lines
I think this patch is not safe to base on yet. I need to find time to review the latest version and share my latest view on this with Pankaj, as I have a bit different design in mind.
OK, do you think the PMU series might make it this cycle or should I drop this as a dependency and re-base my patches just on Daniel's CPUIdle consolidation.
Regards,
Abhilash
Quoted 14 lines
In general, I don't like the fact that you end up with using regmap to access registers that are used exclusively by PMU driver or for accesses happening at late suspend or early resume, where concurrent accesses from other drivers simply can't occur.
Best regards,
Tomasz_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
v4 cover Adds PMU and S2R support for exynos5420
Quoted 14 lines · Abhilash Kesavan
Hi Tomasz,
Quoted 11 lines · Tomasz Figa
Hi Abhilash,
Quoted 7 lines · Abhilash Kesavan
Rebased on
1] Kukjin Kim's tree for-next branch (which has Sachin Kamat's SYSRAM patches merged) with Tomasz Figa's samsung clock tree (samsung-next branch) merged.
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v4 PMU patchset
https://lkml.org/lkml/2014/5/10/29
Quoted 6 lines
Quoted 3 lines
I think this patch is not safe to base on yet. I need to find time to review the latest version and share my latest view on this with Pankaj, as I have a bit different design in mind.
OK, do you think the PMU series might make it this cycle or should I drop this as a dependency and re-base my patches just on Daniel's CPUIdle consolidation.
I'd say it's too late for 3.16 already, for the PMU series at least. 3.15-rc6 will probably show up in next days and Kukjin still has to send pull requests to ARM-SoC, so I'd defer this series for 3.17 as well, especially considering the fact that extending the PMU code in its current form already met with opposition.
Best regards,
Tomasz