powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NAND

PATCH New Aneesh Bansal 2 participants 2 messages May 14, 2014 – May 20, 2014

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Aneesh Bansal

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2014-05-14 06:15 UTC #0 lore raw

PATCH 1/1 powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NAND

In case of secure boot from NAND, CSPR and FTIM settings are same as non-secure NAND boot. CSPR0 is configured as NAND and CSPR1 is configured as NOR.

Signed-off-by Aneesh Bansal <[email protected]>

---
 include/configs/BSC9132QDS.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

include/configs/BSC9132QDS.h +1 -1

index 37e8725..2234874 100644
@@ -361,7 +361,7 @@ combinations. this should be removed later
 #endif
 
 /* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR

Signature · 1 line

1.8.1.4

York Sun

2014-05-20 15:39 UTC #1 lore raw

PATCH 1/1 powerpc/mpc85xx: SECURE BOOT- corrected CSPR settings for BSC9132QDS NAND

Quoted 6 lines · Aneesh Bansal

In case of secure boot from NAND, CSPR and FTIM settings are same as non-secure NAND boot. CSPR0 is configured as NAND and CSPR1 is configured as NOR.
Signed-off-by Aneesh Bansal <[email protected]>
---

Applied to u-boot-mpc85xx/master.

York