board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL

PATCH New Prabhakar Kushwaha 2 participants 2 messages May 15, 2014 – May 20, 2014

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Prabhakar Kushwaha

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2014-05-15 11:13 UTC #0 lore raw

PATCH v2 1/1 board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL

In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed.

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2: Incroporated York' comments

 board/freescale/p1_p2_rdb/Makefile             |   21 +-
 board/freescale/p1_p2_rdb/ddr.c                |   16 +-
 board/freescale/p1_p2_rdb/spl.c                |  141 +++++++++++++
 board/freescale/p1_p2_rdb/spl_minimal.c        |   84 ++++++++
 board/freescale/p1_p2_rdb/tlb.c                |   18 +-
 include/configs/P1_P2_RDB.h                    |  265 ++++++++++++++++--------
 nand_spl/board/freescale/p1_p2_rdb/Makefile    |   91 --------
 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c |   82 --------
 8 files changed, 450 insertions(+), 268 deletions(-)
 create mode 100644 board/freescale/p1_p2_rdb/spl.c
 create mode 100644 board/freescale/p1_p2_rdb/spl_minimal.c
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb/Makefile
 delete mode 100644 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c

board/freescale/p1_p2_rdb/Makefile +20 -1

index f7b568a..a97bf45 100644
@@ -4,8 +4,27 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y	+= spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-y	+= p1_p2_rdb.o
+obj-$(CONFIG_PCI)  += pci.o
+endif
 obj-y	+= ddr.o
 obj-y	+= law.o
-obj-$(CONFIG_PCI)  += pci.o
 obj-y	+= tlb.o
+
+endif

board/freescale/p1_p2_rdb/ddr.c +5 ~~-11~~

index 17d3bea..98ee5f1 100644
@@ -180,27 +180,22 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
 
 phys_size_t fixed_sdram (void)
 {
-	char buf[32];
 	fsl_ddr_cfg_regs_t ddr_cfg_regs;
 	size_t ddr_size;
 	struct cpu_type *cpu;
 	ulong ddr_freq, ddr_freq_mhz;
 
 	cpu = gd->arch.cpu;
-	/* P1020 and it's derivatives support max 32bit DDR width */
-	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
-		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
-	} else {
-		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	}
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
 #if defined(CONFIG_SYS_RAMBOOT)
 	return ddr_size;
 #endif
 	ddr_freq = get_ddr_freq(0);
 	ddr_freq_mhz = ddr_freq / 1000000;
 
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
+	printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
 
 	if(ddr_freq_mhz <= 400)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));

@@ -211,8 +206,7 @@ phys_size_t fixed_sdram (void)
 	else if(ddr_freq_mhz <= 800)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
 	else
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-					strmhz(buf, ddr_freq));
+		panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
 
 	/* P1020 and it's derivatives support max 32bit DDR width */
 	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {

board/freescale/p1_p2_rdb/spl.c new file +141 -0

141 lines not on this page · raw message

board/freescale/p1_p2_rdb/spl_minimal.c new file +84 -0

84 lines not on this page · raw message

board/freescale/p1_p2_rdb/tlb.c +17 -1

index bc98972..73f5729 100644
@@ -37,6 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,

@@ -55,6 +56,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 4, BOOKE_PAGESZ_256K, 1),
 
 #endif /* #if defined(CONFIG_PCI) */
+#endif
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

@@ -65,7 +67,21 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 7, BOOKE_PAGESZ_1G, 1)

include/configs/P1_P2_RDB.h +183 ~~-82~~

356 lines not on this page · raw message

nand_spl/board/freescale/p1_p2_rdb/Makefile deleted +0 ~~-91~~

91 lines not on this page · raw message

nand_spl/board/freescale/p1_p2_rdb/nand_boot.c deleted +0 ~~-82~~

82 lines not on this page · raw message

Signature · 1 line

1.7.9.5

York Sun

2014-05-20 15:40 UTC #1 lore raw

PATCH v2 1/1 board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL

Quoted 12 lines · Prabhakar Kushwaha

In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution.
For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution.

Quoted 8 lines

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed.
Signed-off-by Prabhakar Kushwaha <[email protected]>
---
Changes for v2: Incroporated York' comments

Applied to u-boot-mpc85xx/master.

York