Exynos multi-platform support

PATCH Superseded Sachin Kamat 8 participants 26 messages May 21, 2014 – May 26, 2014

Subsystems (4)

Arm (32-bit) Arm sub-architectures Arm Samsung Exynos CPU frequency scaling framework

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Sachin Kamat

author

2014-05-21 06:52 UTC #0 lore raw

cover Exynos multi-platform support

The patches in this series were earlier sent as part of other series. Now that the other patches have been merged, re-sending these after rebasing them on linux-next (20140519). Tested on Exynos4210, 4412, 5250 and 5420 based boards.

A particular change in this series is the removal of single platform support for Exynos as suggested by Arnd and Olof (patch 2/3). With this change certain features (drivers) which are not yet multi-platform aware like cpufreq, devfreq and DRM based gscaler will not be available now.

Arnd Bergmann (1):
ARM: EXYNOS: Enable multi-platform build support

Sachin Kamat (2):
ARM: EXYNOS: Consolidate Kconfig entries
ARM: multi_v7_defconfig: Enable Exynos platform

 arch/arm/Kconfig                    |   20 ----------
 arch/arm/configs/multi_v7_defconfig |   12 ++++++
 arch/arm/mach-exynos/Kconfig        |   73 +++++++++++++++--------------------
 arch/arm/mach-exynos/Makefile       |    2 +
 arch/arm/plat-samsung/Makefile      |    3 ++
 5 files changed, 49 insertions(+), 61 deletions(-)

Signature · 1 line

1.7.9.5

Sachin Kamat

author

2014-05-21 06:52 UTC #1 lore raw

PATCH 1/3 ARM: EXYNOS: Consolidate Kconfig entries

Instead of repeating the Kconfig entries for every SoC, move them under ARCH_EXYNOS4 and 5 and move the entries common to both 4 and 5 under ARCH_EXYNOS.

Signed-off-by Sachin Kamat <[email protected]>

---
 arch/arm/Kconfig             |   10 ++++++++++
 arch/arm/mach-exynos/Kconfig |   45 ++++--------------------------------------
 2 files changed, 14 insertions(+), 41 deletions(-)

arch/arm/Kconfig +10 -0

index 5e91e40c1d22..666b59b58ab0 100644
@@ -831,18 +831,28 @@ config ARCH_S5PV210
 
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
+	select ARCH_HAS_BANDGAP
 	select ARCH_HAS_CPUFREQ
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_SPARSEMEM_ENABLE
+	select ARM_AMBA
 	select ARM_GIC
+	select CLKSRC_OF
 	select COMMON_CLK_SAMSUNG
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_SCU if SMP
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 	select HAVE_S3C_RTC if RTC_CLASS
+	select HAVE_SMP
 	select NEED_MACH_MEMORY_H
+	select PINCTRL
+	select PINCTRL_EXYNOS
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	select S5P_DEV_MFC
+	select SAMSUNG_DMADEV
 	select SPARSE_IRQ
 	select SRAM
 	select USE_OF

arch/arm/mach-exynos/Kconfig +4 ~~-41~~

93 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Sachin Kamat

author

2014-05-21 06:52 UTC #2 lore raw

PATCH 2/3 ARM: EXYNOS: Enable multi-platform build support

In reply to Sachin Kamat

From: Arnd Bergmann <[email protected]>

This makes it possible to enable the exynos platform as part of a multiplatform kernel, in addition to keeping the single-platform Exynos support.

Signed-off-by Arnd Bergmann <[email protected]>

Signed-off-by Sachin Kamat <[email protected]>

---
 arch/arm/Kconfig               |   30 ------------------------------
 arch/arm/mach-exynos/Kconfig   |   28 ++++++++++++++++++++++++++++
 arch/arm/mach-exynos/Makefile  |    2 ++
 arch/arm/plat-samsung/Makefile |    3 +++
 4 files changed, 33 insertions(+), 30 deletions(-)

arch/arm/Kconfig +0 ~~-30~~

index 666b59b58ab0..26f2bae4d948 100644
@@ -829,36 +829,6 @@ config ARCH_S5PV210
 	help
 	  Samsung S5PV210/S5PC110 series based systems
 
-config ARCH_EXYNOS
-	bool "Samsung EXYNOS"
-	select ARCH_HAS_BANDGAP
-	select ARCH_HAS_CPUFREQ
-	select ARCH_HAS_HOLES_MEMORYMODEL
-	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_SPARSEMEM_ENABLE
-	select ARM_AMBA
-	select ARM_GIC
-	select CLKSRC_OF
-	select COMMON_CLK_SAMSUNG
-	select CPU_V7
-	select GENERIC_CLOCKEVENTS
-	select HAVE_ARM_SCU if SMP
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select HAVE_S3C_RTC if RTC_CLASS
-	select HAVE_SMP
-	select NEED_MACH_MEMORY_H
-	select PINCTRL
-	select PINCTRL_EXYNOS
-	select PM_GENERIC_DOMAINS if PM_RUNTIME
-	select S5P_DEV_MFC
-	select SAMSUNG_DMADEV
-	select SPARSE_IRQ
-	select SRAM
-	select USE_OF
-	help
-	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
-
 config ARCH_DAVINCI
 	bool "TI DaVinci"
 	select ARCH_HAS_HOLES_MEMORYMODEL

arch/arm/mach-exynos/Kconfig +28 -0

index 138070e42aa9..46634175cf54 100644
@@ -7,6 +7,34 @@
 
 # Configuration options for the EXYNOS4
 
+config ARCH_EXYNOS
+	bool "Samsung EXYNOS" if ARCH_MULTI_V7
+	select ARCH_HAS_BANDGAP
+	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CLKSRC_OF
+	select COMMON_CLK_SAMSUNG
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_SCU if SMP
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select HAVE_S3C_RTC if RTC_CLASS
+	select HAVE_SMP
+	select PINCTRL
+	select PINCTRL_EXYNOS
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	select S5P_DEV_MFC
+	select SAMSUNG_DMADEV
+	select SPARSE_IRQ
+	select SRAM
+	select USE_OF
+	help
+	  Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
+
 if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"

arch/arm/mach-exynos/Makefile +2 -0

index 2e0666d31e75..97af694291f1 100644
@@ -5,6 +5,8 @@
 #
 # Licensed under GPLv2
 
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
+
 obj-y				:=
 obj-m				:=
 obj-n				:=

arch/arm/plat-samsung/Makefile +3 -0

index 25c826ed3b65..5e5beaa9ae15 100644
@@ -4,6 +4,9 @@
 #
 # Licensed under GPLv2
 
+ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARCH_EXYNOS)	+= -I$(srctree)/arch/arm/mach-exynos/include
+
 obj-y				:=
 obj-m				:=
 obj-n				:= dummy.o

Signature · 1 line

1.7.9.5

Arnd Bergmann

2014-05-21 08:16 UTC #3 lore raw

PATCH 2/3 ARM: EXYNOS: Enable multi-platform build support

Quoted 21 lines · On Wednesday 21 May 2014 12:22:48 Sachin Kamat wrote:

# Configuration options for the EXYNOS4

arch/arm/mach-exynos/Kconfig +18 -0

+config ARCH_EXYNOS
+       bool "Samsung EXYNOS" if ARCH_MULTI_V7
+       select ARCH_HAS_BANDGAP
+       select ARCH_HAS_CPUFREQ
+       select ARCH_HAS_HOLES_MEMORYMODEL
+       select ARCH_REQUIRE_GPIOLIB
+       select ARM_AMBA
+       select ARM_GIC
+       select CLKSRC_OF
+       select COMMON_CLK_SAMSUNG
+       select CPU_V7
+       select GENERIC_CLOCKEVENTS
+       select HAVE_ARM_SCU if SMP
+       select HAVE_S3C2410_I2C if I2C
+       select HAVE_S3C2410_WATCHDOG if WATCHDOG
+       select HAVE_S3C_RTC if RTC_CLASS
+       select HAVE_SMP
+       select PINCTRL

arch/arm/mach-exynos/Kconfig line 37

Quoted 10 lines

arch/arm/mach-exynos/Kconfig +10 -0

+       select PINCTRL_EXYNOS
+       select PM_GENERIC_DOMAINS if PM_RUNTIME
+       select S5P_DEV_MFC
+       select SAMSUNG_DMADEV
+       select SPARSE_IRQ
+       select SRAM
+       select USE_OF
+       help
+         Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
+

A number of these can be removed now: SPARSE_IRQ, USE_OF, GENERIC_CLOCKEVENTS, CLKSRC_OF, CPU_V7 and HAVE_SMP are implied by ARCH_MULTIPLATFORM or ARCH_MULTI_V7, so we shouldn't duplicate them here.

I believe SAMSUNG_DMADEV cannot work in multiplatform, but we also don't need it any more.

The rest looks good.

Arnd

Sachin Kamat

author

2014-05-21 08:20 UTC #4 lore raw

PATCH 2/3 ARM: EXYNOS: Enable multi-platform build support

Quoted 28 lines · Arnd Bergmann

Quoted 27 lines · On Wednesday 21 May 2014 12:22:48 Sachin Kamat wrote:

# Configuration options for the EXYNOS4

arch/arm/mach-exynos/Kconfig +25 -0

+config ARCH_EXYNOS
+       bool "Samsung EXYNOS" if ARCH_MULTI_V7
+       select ARCH_HAS_BANDGAP
+       select ARCH_HAS_CPUFREQ
+       select ARCH_HAS_HOLES_MEMORYMODEL
+       select ARCH_REQUIRE_GPIOLIB
+       select ARM_AMBA
+       select ARM_GIC
+       select CLKSRC_OF
+       select COMMON_CLK_SAMSUNG
+       select CPU_V7
+       select GENERIC_CLOCKEVENTS
+       select HAVE_ARM_SCU if SMP
+       select HAVE_S3C2410_I2C if I2C
+       select HAVE_S3C2410_WATCHDOG if WATCHDOG
+       select HAVE_S3C_RTC if RTC_CLASS
+       select HAVE_SMP
+       select PINCTRL
+       select PINCTRL_EXYNOS
+       select PM_GENERIC_DOMAINS if PM_RUNTIME
+       select S5P_DEV_MFC
+       select SAMSUNG_DMADEV
+       select SPARSE_IRQ
+       select SRAM
+       select USE_OF

Quoted 8 lines

arch/arm/mach-exynos/Kconfig line 37
Quoted 4 lines
arch/arm/mach-exynos/Kconfig +3 -0
+       help
+         Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
+
A number of these can be removed now: SPARSE_IRQ, USE_OF, GENERIC_CLOCKEVENTS, CLKSRC_OF, CPU_V7 and HAVE_SMP are implied by ARCH_MULTIPLATFORM or ARCH_MULTI_V7, so we shouldn't duplicate them here.

OK.

Quoted 3 lines

I believe SAMSUNG_DMADEV cannot work in multiplatform, but we also don't need it any more.

Yes this is no longer needed now that we use generic DMA engine. Will remove this too.
Thanks for the review.

Signature · 2 lines

With warm regards,
Sachin

Bartlomiej Zolnierkiewicz

2014-05-21 10:36 UTC #5 lore raw

PATCH 2/3 ARM: EXYNOS: Enable multi-platform build support

In reply to Sachin Kamat

Hi,

Quoted 5 lines · Sachin Kamat

From: Arnd Bergmann <[email protected]>
This makes it possible to enable the exynos platform as part of a multiplatform kernel, in addition to keeping the single-platform Exynos support.

The patch description is wrong. After this patch single-platform Exynos support is no longer available and it adds at least one serious regression (cpufreq) which should be fixed before merging this patch. Moreover it seems that this patch (#2) should be merged with patch #3 to preserve bisectability. Please also note that exynos_defconfig is no longer useful after these changes and can be be removed.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Quoted 116 lines

Signed-off-by Arnd Bergmann <[email protected]>

Signed-off-by Sachin Kamat <[email protected]>

---
 arch/arm/Kconfig               |   30 ------------------------------
 arch/arm/mach-exynos/Kconfig   |   28 ++++++++++++++++++++++++++++
 arch/arm/mach-exynos/Makefile  |    2 ++
 arch/arm/plat-samsung/Makefile |    3 +++
 4 files changed, 33 insertions(+), 30 deletions(-)

arch/arm/Kconfig +0 ~~-30~~

index 666b59b58ab0..26f2bae4d948 100644
@@ -829,36 +829,6 @@ config ARCH_S5PV210
 	help
 	  Samsung S5PV210/S5PC110 series based systems
 
-config ARCH_EXYNOS
-	bool "Samsung EXYNOS"
-	select ARCH_HAS_BANDGAP
-	select ARCH_HAS_CPUFREQ
-	select ARCH_HAS_HOLES_MEMORYMODEL
-	select ARCH_REQUIRE_GPIOLIB
-	select ARCH_SPARSEMEM_ENABLE
-	select ARM_AMBA
-	select ARM_GIC
-	select CLKSRC_OF
-	select COMMON_CLK_SAMSUNG
-	select CPU_V7
-	select GENERIC_CLOCKEVENTS
-	select HAVE_ARM_SCU if SMP
-	select HAVE_S3C2410_I2C if I2C
-	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select HAVE_S3C_RTC if RTC_CLASS
-	select HAVE_SMP
-	select NEED_MACH_MEMORY_H
-	select PINCTRL
-	select PINCTRL_EXYNOS
-	select PM_GENERIC_DOMAINS if PM_RUNTIME
-	select S5P_DEV_MFC
-	select SAMSUNG_DMADEV
-	select SPARSE_IRQ
-	select SRAM
-	select USE_OF
-	help
-	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
-
 config ARCH_DAVINCI
 	bool "TI DaVinci"
 	select ARCH_HAS_HOLES_MEMORYMODEL

arch/arm/mach-exynos/Kconfig +28 -0

index 138070e42aa9..46634175cf54 100644
@@ -7,6 +7,34 @@
 
 # Configuration options for the EXYNOS4
 
+config ARCH_EXYNOS
+	bool "Samsung EXYNOS" if ARCH_MULTI_V7
+	select ARCH_HAS_BANDGAP
+	select ARCH_HAS_CPUFREQ
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select ARM_GIC
+	select CLKSRC_OF
+	select COMMON_CLK_SAMSUNG
+	select CPU_V7
+	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_SCU if SMP
+	select HAVE_S3C2410_I2C if I2C
+	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select HAVE_S3C_RTC if RTC_CLASS
+	select HAVE_SMP
+	select PINCTRL
+	select PINCTRL_EXYNOS
+	select PM_GENERIC_DOMAINS if PM_RUNTIME
+	select S5P_DEV_MFC
+	select SAMSUNG_DMADEV
+	select SPARSE_IRQ
+	select SRAM
+	select USE_OF
+	help
+	  Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
+
 if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"

arch/arm/mach-exynos/Makefile +2 -0

index 2e0666d31e75..97af694291f1 100644
@@ -5,6 +5,8 @@
 #
 # Licensed under GPLv2
 
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
+
 obj-y				:=
 obj-m				:=
 obj-n				:=

arch/arm/plat-samsung/Makefile +3 -0

index 25c826ed3b65..5e5beaa9ae15 100644
@@ -4,6 +4,9 @@
 #
 # Licensed under GPLv2
 
+ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARCH_EXYNOS)	+= -I$(srctree)/arch/arm/mach-exynos/include
+
 obj-y				:=
 obj-m				:=
 obj-n				:= dummy.o

Sachin Kamat

author

2014-05-21 11:14 UTC #6 lore raw

PATCH 2/3 ARM: EXYNOS: Enable multi-platform build support

Hi Bartlomiej,

Quoted 4 lines · Bartlomiej Zolnierkiewicz

Hi,
On Wednesday, May 21, 2014 12:22:48 PM Sachin Kamat wrote:

Quoted 8 lines

Quoted 5 lines
From: Arnd Bergmann <[email protected]>
This makes it possible to enable the exynos platform as part of a multiplatform kernel, in addition to keeping the single-platform Exynos support.
The patch description is wrong. After this patch single-platform Exynos support is no longer available

Forgot to update the message while rebasing. Thanks for noticing.

Quoted 1 line

and it adds at least one serious regression

I have mentioned about this in the cover letter.

Quoted 3 lines

(cpufreq) which should be fixed before merging this patch. Moreover it seems that this patch (#2) should be merged with patch #3 to preserve bisectability.

At this point exynos_defconfig works.

Quoted 2 lines

Please also note that exynos_defconfig is no longer useful after these changes and can be be removed.

Yes.

---
With warm regards,
Sachin

Kukjin Kim

2014-05-21 13:40 UTC #7 lore raw

PATCH 2/3 ARM: EXYNOS: Enable multi-platform build support

Quoted 28 lines · Sachin Kamat

Hi Bartlomiej,
Quoted 4 lines · Bartlomiej Zolnierkiewicz
Hi,
On Wednesday, May 21, 2014 12:22:48 PM Sachin Kamat wrote:
Quoted 8 lines
Quoted 5 lines
From: Arnd Bergmann <[email protected]>
This makes it possible to enable the exynos platform as part of a multiplatform kernel, in addition to keeping the single-platform Exynos support.
The patch description is wrong. After this patch single-platform Exynos support is no longer available
Forgot to update the message while rebasing. Thanks for noticing.
Quoted 1 line
and it adds at least one serious regression
I have mentioned about this in the cover letter.
Quoted 3 lines
(cpufreq) which should be fixed before merging this patch. Moreover it seems that this patch (#2) should be merged with patch #3 to preserve bisectability.

Quoted 7 lines

At this point exynos_defconfig works.
Quoted 2 lines
Please also note that exynos_defconfig is no longer useful after these changes and can be be removed.
Yes.

Well, I think keeping the exynos_defconfig would be nice like other platform in multiplatforms...and I'm going to enable possible configs in exynos_defconfig for exynso SoCs then it can cover more for exynos...

Thanks,
Kukjin

Bartlomiej Zolnierkiewicz

2014-05-21 14:02 UTC #8 lore raw

PATCH 2/3 ARM: EXYNOS: Enable multi-platform build support

Hi,

Quoted 29 lines · Kukjin Kim

Quoted 28 lines · Sachin Kamat
Hi Bartlomiej,
Quoted 4 lines · Bartlomiej Zolnierkiewicz
Hi,
On Wednesday, May 21, 2014 12:22:48 PM Sachin Kamat wrote:
Quoted 8 lines
Quoted 5 lines
From: Arnd Bergmann <[email protected]>
This makes it possible to enable the exynos platform as part of a multiplatform kernel, in addition to keeping the single-platform Exynos support.
The patch description is wrong. After this patch single-platform Exynos support is no longer available
Forgot to update the message while rebasing. Thanks for noticing.
Quoted 1 line
and it adds at least one serious regression
I have mentioned about this in the cover letter.
Quoted 3 lines
(cpufreq) which should be fixed before merging this patch. Moreover it seems that this patch (#2) should be merged with patch #3 to preserve bisectability.

Quoted 8 lines

Quoted 7 lines
At this point exynos_defconfig works.
Quoted 2 lines
Please also note that exynos_defconfig is no longer useful after these changes and can be be removed.
Yes.
Well, I think keeping the exynos_defconfig would be nice like other platform in multiplatforms...and I'm going to enable possible configs in exynos_defconfig for exynso SoCs then it can cover more for exynos...

I know that many other platforms still have their own configs [*] but I would strongly prefer to have a single config supporting Exynos SoCs (that would be a multiplatform one) to simplify testing and prevent situations when something works with one config but not the other.

[*] I also hope that they get removed in the longer-term..

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Sachin Kamat

author

2014-05-21 06:52 UTC #9 lore raw

PATCH 3/3 ARM: multi_v7_defconfig: Enable Exynos platform

In reply to Sachin Kamat

Enable Exynos platform and its related IPs.

Signed-off-by Sachin Kamat <[email protected]>

---
 arch/arm/configs/multi_v7_defconfig |   12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/configs/multi_v7_defconfig +12 -0

index 2fbafc529624..b76e978a62ae 100644
@@ -48,6 +48,7 @@ CONFIG_ARCH_SPEAR13XX=y
 CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 CONFIG_ARCH_STI=y
+CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_SIRF=y
 CONFIG_ARCH_TEGRA=y

@@ -72,6 +73,7 @@ CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=8
 CONFIG_HIGHPTE=y
 CONFIG_CMA=y
 CONFIG_ARM_APPENDED_DTB=y

@@ -155,6 +157,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_SIRFSOC=y
 CONFIG_SERIAL_SIRFSOC_CONSOLE=y
 CONFIG_SERIAL_TEGRA=y

@@ -178,6 +182,7 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_EXYNOS5=y
 CONFIG_I2C_MV64XXX=y
 CONFIG_I2C_SIRF=y
 CONFIG_I2C_TEGRA=y

@@ -213,6 +218,7 @@ CONFIG_MFD_AS3722=y
 CONFIG_MFD_CROS_EC=y
 CONFIG_MFD_CROS_EC_SPI=y
 CONFIG_MFD_MAX8907=y
+CONFIG_MFD_SEC_CORE=y
 CONFIG_MFD_PALMAS=y
 CONFIG_MFD_TPS65090=y
 CONFIG_MFD_TPS6586X=y

@@ -223,6 +229,8 @@ CONFIG_REGULATOR_AS3722=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS51632=y
 CONFIG_REGULATOR_TPS62360=y
 CONFIG_REGULATOR_TPS65090=y

@@ -279,12 +287,16 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_PXAV3=y
 CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_DOVE=y
 CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_MVSDIO=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y

Signature · 1 line

1.7.9.5

Tomasz Figa

2014-05-21 08:26 UTC #10 lore raw

cover Exynos multi-platform support

In reply to Sachin Kamat

Hi,

Quoted 10 lines · Sachin Kamat

The patches in this series were earlier sent as part of other series. Now that the other patches have been merged, re-sending these after rebasing them on linux-next (20140519). Tested on Exynos4210, 4412, 5250 and 5420 based boards.
A particular change in this series is the removal of single platform support for Exynos as suggested by Arnd and Olof (patch 2/3). With this change certain features (drivers) which are not yet multi-platform aware like cpufreq, devfreq and DRM based gscaler will not be available now.

I really don't like this. Well, I don't care too much for devfreq and DRM Gscaler, as the the first one doesn't even support DT and Gscaler is usually used through a V4L2 driver, which should be fine. However cpufreq is quite important feature and it will be a serious regression in terms of performance (most boards don't boot at maximum frequency) and power consumption (no ability to scale the CPU down).

So my proposal here is to hack the cpufreq driver with a minimal amount of changes needed to compile and use it on multi-platform builds. I'll send a patch later today to show what I mean. It would have to be merged as a prerequisite for this series, to keep the history bisectable.

Best regards,
Tomasz

Tomasz Figa

2014-05-21 11:12 UTC #11 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around.

This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support.

Signed-off-by Tomasz Figa <[email protected]>

---
 drivers/cpufreq/Kconfig.arm          |  6 +++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++++----------------
 drivers/cpufreq/exynos4210-cpufreq.c | 31 +++++++++++++++++++++++++------
 drivers/cpufreq/exynos4x12-cpufreq.c | 32 ++++++++++++++++++++++++++------
 drivers/cpufreq/exynos5250-cpufreq.c | 35 +++++++++++++++++++++++++++--------
 6 files changed, 95 insertions(+), 41 deletions(-)

drivers/cpufreq/Kconfig.arm +3 -3

index 6a7dd3e..2b7548f 100644
@@ -31,7 +31,7 @@ config ARM_EXYNOS_CPUFREQ
 
 config ARM_EXYNOS4210_CPUFREQ
 	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM
+	depends on CPU_EXYNOS4210
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

@@ -42,7 +42,7 @@ config ARM_EXYNOS4210_CPUFREQ
 
 config ARM_EXYNOS4X12_CPUFREQ
 	bool "SAMSUNG EXYNOS4x12"
-	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
+	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

@@ -53,7 +53,7 @@ config ARM_EXYNOS4X12_CPUFREQ
 
 config ARM_EXYNOS5250_CPUFREQ
 	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250 && !ARCH_MULTIPLATFORM
+	depends on SOC_EXYNOS5250
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

drivers/cpufreq/exynos-cpufreq.c +0 -2

index 7c2a096..1e0ec57 100644
@@ -19,8 +19,6 @@
 #include <linux/platform_device.h>
 #include <linux/of.h>
 
-#include <plat/cpu.h>
-
 #include "exynos-cpufreq.h"
 
 static struct exynos_dvfs_info *exynos_info;

drivers/cpufreq/exynos-cpufreq.h +14 ~~-16~~

index a28ee9d..8dfebac 100644
@@ -50,6 +50,7 @@ struct exynos_dvfs_info {
 	struct cpufreq_frequency_table	*freq_table;
 	void (*set_freq)(unsigned int, unsigned int);
 	bool (*need_apll_change)(unsigned int, unsigned int);
+	void __iomem	*cmu_regs;
 };
 
 #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ

@@ -77,24 +78,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
 }
 #endif
 
-#include <plat/cpu.h>
-#include <mach/map.h>
+#define EXYNOS4_CLKSRC_CPU			0x14200
+#define EXYNOS4_CLKMUX_STATCPU			0x14400
 
-#define EXYNOS4_CLKSRC_CPU			(S5P_VA_CMU + 0x14200)
-#define EXYNOS4_CLKMUX_STATCPU			(S5P_VA_CMU + 0x14400)
-
-#define EXYNOS4_CLKDIV_CPU			(S5P_VA_CMU + 0x14500)
-#define EXYNOS4_CLKDIV_CPU1			(S5P_VA_CMU + 0x14504)
-#define EXYNOS4_CLKDIV_STATCPU			(S5P_VA_CMU + 0x14600)
-#define EXYNOS4_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x14604)
+#define EXYNOS4_CLKDIV_CPU			0x14500
+#define EXYNOS4_CLKDIV_CPU1			0x14504
+#define EXYNOS4_CLKDIV_STATCPU			0x14600
+#define EXYNOS4_CLKDIV_STATCPU1			0x14604
 
 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT	(16)
 #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
 
-#define EXYNOS5_APLL_LOCK			(S5P_VA_CMU + 0x00000)
-#define EXYNOS5_APLL_CON0			(S5P_VA_CMU + 0x00100)
-#define EXYNOS5_CLKMUX_STATCPU			(S5P_VA_CMU + 0x00400)
-#define EXYNOS5_CLKDIV_CPU0			(S5P_VA_CMU + 0x00500)
-#define EXYNOS5_CLKDIV_CPU1			(S5P_VA_CMU + 0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0			(S5P_VA_CMU + 0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x00604)
+#define EXYNOS5_APLL_LOCK			0x00000
+#define EXYNOS5_APLL_CON0			0x00100
+#define EXYNOS5_CLKMUX_STATCPU			0x00400
+#define EXYNOS5_CLKDIV_CPU0			0x00500
+#define EXYNOS5_CLKDIV_CPU1			0x00504
+#define EXYNOS5_CLKDIV_STATCPU0			0x00600
+#define EXYNOS5_CLKDIV_STATCPU1			0x00604

drivers/cpufreq/exynos4210-cpufreq.c +25 -6

index 6384e5b..a412146 100644
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos4210_volt_table[] = {
 	1250000, 1150000, 1050000, 975000, 950000,

@@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_4210[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
 	} while (tmp & 0x1111111);
 
 	/* Change Divider - CPU1 */
 
 	tmp = apll_freq_4210[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
 	} while (tmp & 0x11);
 }

@@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index)
 	clk_set_parent(moutcore, mout_mpll);
 
 	do {
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
 			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index)
 	clk_set_parent(moutcore, mout_apll);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
 		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 }

@@ -115,8 +118,22 @@ static void exynos4210_set_frequency(unsigned int old_index,
 
 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -143,6 +160,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos4210_freq_table;
 	info->set_freq = exynos4210_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

drivers/cpufreq/exynos4x12-cpufreq.c +26 -6

index 63a3907..aaeceb6 100644
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos4x12_volt_table[] = {
 	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,

@@ -105,19 +108,20 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_4x12[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
-	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
+	       & 0x11111111)
 		cpu_relax();
 
 	/* Change Divider - CPU1 */
 	tmp = apll_freq_4x12[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
 	} while (tmp != 0x0);
 }

@@ -130,7 +134,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
 			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -142,7 +146,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
 		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 }

@@ -161,8 +165,22 @@ static void exynos4x12_set_frequency(unsigned int old_index,
 
 int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -194,6 +212,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos4x12_freq_table;
 	info->set_freq = exynos4x12_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

drivers/cpufreq/exynos5250-cpufreq.c +27 -8

index 363a0b3..cbfbe30 100644
@@ -16,8 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
-
-#include <mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -25,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos5250_volt_table[] = {
 	1300000, 1250000, 1225000, 1200000, 1150000,

@@ -87,17 +88,18 @@ static void set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_5250[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
 
-	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
+	       & 0x11111111)
 		cpu_relax();
 
 	/* Change Divider - CPU1 */
 	tmp = apll_freq_5250[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
 
-	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
 		cpu_relax();
 }

@@ -111,7 +113,8 @@ static void set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
+			>> 16);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -122,7 +125,7 @@ static void set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
 		tmp &= (0x7 << 16);
 	} while (tmp != (0x1 << 16));
 }

@@ -141,8 +144,22 @@ static void exynos5250_set_frequency(unsigned int old_index,
 
 int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -169,6 +186,8 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos5250_freq_table;
 	info->set_freq = exynos5250_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

Signature · 1 line

1.9.3

Tomasz Figa

2014-05-21 11:17 UTC #12 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Forwarding to linux-samsung-soc ML, which was omitted by mistake. Sorry, for the noise.

Best regards,
Tomasz

Quoted 405 lines · Tomasz Figa

Signed-off-by Tomasz Figa <[email protected]>

---
 drivers/cpufreq/Kconfig.arm          |  6 +++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++++----------------
 drivers/cpufreq/exynos4210-cpufreq.c | 31 +++++++++++++++++++++++++------
 drivers/cpufreq/exynos4x12-cpufreq.c | 32 ++++++++++++++++++++++++++------
 drivers/cpufreq/exynos5250-cpufreq.c | 35 +++++++++++++++++++++++++++--------
 6 files changed, 95 insertions(+), 41 deletions(-)

drivers/cpufreq/Kconfig.arm +3 -3

index 6a7dd3e..2b7548f 100644
@@ -31,7 +31,7 @@ config ARM_EXYNOS_CPUFREQ
 
 config ARM_EXYNOS4210_CPUFREQ
 	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM
+	depends on CPU_EXYNOS4210
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

@@ -42,7 +42,7 @@ config ARM_EXYNOS4210_CPUFREQ
 
 config ARM_EXYNOS4X12_CPUFREQ
 	bool "SAMSUNG EXYNOS4x12"
-	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
+	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

@@ -53,7 +53,7 @@ config ARM_EXYNOS4X12_CPUFREQ
 
 config ARM_EXYNOS5250_CPUFREQ
 	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250 && !ARCH_MULTIPLATFORM
+	depends on SOC_EXYNOS5250
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

drivers/cpufreq/exynos-cpufreq.c +0 -2

index 7c2a096..1e0ec57 100644
@@ -19,8 +19,6 @@
 #include <linux/platform_device.h>
 #include <linux/of.h>
 
-#include <plat/cpu.h>
-
 #include "exynos-cpufreq.h"
 
 static struct exynos_dvfs_info *exynos_info;

drivers/cpufreq/exynos-cpufreq.h +14 ~~-16~~

index a28ee9d..8dfebac 100644
@@ -50,6 +50,7 @@ struct exynos_dvfs_info {
 	struct cpufreq_frequency_table	*freq_table;
 	void (*set_freq)(unsigned int, unsigned int);
 	bool (*need_apll_change)(unsigned int, unsigned int);
+	void __iomem	*cmu_regs;
 };
 
 #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ

@@ -77,24 +78,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
 }
 #endif
 
-#include <plat/cpu.h>
-#include <mach/map.h>
+#define EXYNOS4_CLKSRC_CPU			0x14200
+#define EXYNOS4_CLKMUX_STATCPU			0x14400
 
-#define EXYNOS4_CLKSRC_CPU			(S5P_VA_CMU + 0x14200)
-#define EXYNOS4_CLKMUX_STATCPU			(S5P_VA_CMU + 0x14400)
-
-#define EXYNOS4_CLKDIV_CPU			(S5P_VA_CMU + 0x14500)
-#define EXYNOS4_CLKDIV_CPU1			(S5P_VA_CMU + 0x14504)
-#define EXYNOS4_CLKDIV_STATCPU			(S5P_VA_CMU + 0x14600)
-#define EXYNOS4_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x14604)
+#define EXYNOS4_CLKDIV_CPU			0x14500
+#define EXYNOS4_CLKDIV_CPU1			0x14504
+#define EXYNOS4_CLKDIV_STATCPU			0x14600
+#define EXYNOS4_CLKDIV_STATCPU1			0x14604
 
 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT	(16)
 #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
 
-#define EXYNOS5_APLL_LOCK			(S5P_VA_CMU + 0x00000)
-#define EXYNOS5_APLL_CON0			(S5P_VA_CMU + 0x00100)
-#define EXYNOS5_CLKMUX_STATCPU			(S5P_VA_CMU + 0x00400)
-#define EXYNOS5_CLKDIV_CPU0			(S5P_VA_CMU + 0x00500)
-#define EXYNOS5_CLKDIV_CPU1			(S5P_VA_CMU + 0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0			(S5P_VA_CMU + 0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x00604)
+#define EXYNOS5_APLL_LOCK			0x00000
+#define EXYNOS5_APLL_CON0			0x00100
+#define EXYNOS5_CLKMUX_STATCPU			0x00400
+#define EXYNOS5_CLKDIV_CPU0			0x00500
+#define EXYNOS5_CLKDIV_CPU1			0x00504
+#define EXYNOS5_CLKDIV_STATCPU0			0x00600
+#define EXYNOS5_CLKDIV_STATCPU1			0x00604

drivers/cpufreq/exynos4210-cpufreq.c +25 -6

index 6384e5b..a412146 100644
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos4210_volt_table[] = {
 	1250000, 1150000, 1050000, 975000, 950000,

@@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_4210[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
 	} while (tmp & 0x1111111);
 
 	/* Change Divider - CPU1 */
 
 	tmp = apll_freq_4210[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
 	} while (tmp & 0x11);
 }

@@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index)
 	clk_set_parent(moutcore, mout_mpll);
 
 	do {
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
 			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index)
 	clk_set_parent(moutcore, mout_apll);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
 		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 }

@@ -115,8 +118,22 @@ static void exynos4210_set_frequency(unsigned int old_index,
 
 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -143,6 +160,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos4210_freq_table;
 	info->set_freq = exynos4210_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

drivers/cpufreq/exynos4x12-cpufreq.c +26 -6

index 63a3907..aaeceb6 100644
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos4x12_volt_table[] = {
 	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,

@@ -105,19 +108,20 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_4x12[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
-	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
+	       & 0x11111111)
 		cpu_relax();
 
 	/* Change Divider - CPU1 */
 	tmp = apll_freq_4x12[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
 	} while (tmp != 0x0);
 }

@@ -130,7 +134,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
 			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -142,7 +146,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
 		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 }

@@ -161,8 +165,22 @@ static void exynos4x12_set_frequency(unsigned int old_index,
 
 int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -194,6 +212,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos4x12_freq_table;
 	info->set_freq = exynos4x12_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

drivers/cpufreq/exynos5250-cpufreq.c +27 -8

index 363a0b3..cbfbe30 100644
@@ -16,8 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
-
-#include <mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -25,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos5250_volt_table[] = {
 	1300000, 1250000, 1225000, 1200000, 1150000,

@@ -87,17 +88,18 @@ static void set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_5250[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
 
-	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
+	       & 0x11111111)
 		cpu_relax();
 
 	/* Change Divider - CPU1 */
 	tmp = apll_freq_5250[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
 
-	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
 		cpu_relax();
 }

@@ -111,7 +113,8 @@ static void set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
+			>> 16);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -122,7 +125,7 @@ static void set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
 		tmp &= (0x7 << 16);
 	} while (tmp != (0x1 << 16));
 }

@@ -141,8 +144,22 @@ static void exynos5250_set_frequency(unsigned int old_index,
 
 int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -169,6 +186,8 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos5250_freq_table;
 	info->set_freq = exynos5250_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

Viresh Kumar

maintainer

2014-05-21 11:22 UTC #13 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

On 21 May 2014 16:47, Tomasz Figa <[email protected]> wrote:

Mostly nitpicks ..

Quoted 5 lines

drivers/cpufreq/Kconfig.arm config ARM_EXYNOS4210_CPUFREQ · line 45
Quoted 5 lines
drivers/cpufreq/Kconfig.arm +1 -1
 config ARM_EXYNOS4X12_CPUFREQ
      bool "SAMSUNG EXYNOS4x12"
-     depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
+     depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)

Get rid of () as well..

Quoted 9 lines

drivers/cpufreq/exynos-cpufreq.h struct exynos_dvfs_info { · line 53

Quoted 9 lines

drivers/cpufreq/exynos-cpufreq.h +1 -0

index a28ee9d..8dfebac 100644
@@ -50,6 +50,7 @@ struct exynos_dvfs_info {
      struct cpufreq_frequency_table  *freq_table;
      void (*set_freq)(unsigned int, unsigned int);
      bool (*need_apll_change)(unsigned int, unsigned int);
+     void __iomem    *cmu_regs;

s/tab/space ? before *cmu_regs ..

Quoted 6 lines

drivers/cpufreq/exynos4210-cpufreq.c int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) · line 163
Quoted 6 lines
drivers/cpufreq/exynos4210-cpufreq.c +1 -0
@@ -143,6 +160,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
      info->freq_table = exynos4210_freq_table;
      info->set_freq = exynos4210_set_frequency;
 
+     cpufreq = info;

I couldn't find this variable .. i.e. 'cpufreq'

Quoted 11 lines

drivers/cpufreq/exynos4210-cpufreq.c +1 -0

+
      return 0;
 
 err_mout_apll:

drivers/cpufreq/exynos4x12-cpufreq.c +1 -0

 
 int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 {
+     struct device_node *np;
      unsigned long rate;

Quoted 13 lines

drivers/cpufreq/exynos4x12-cpufreq.c static void exynos4x12_set_frequency(unsigned int old_index, · line 183

Quoted 13 lines

drivers/cpufreq/exynos4x12-cpufreq.c +13 -0

+     np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
+     if (!np) {
+             pr_err("%s: failed to find clock controller DT node\n",
+                     __func__);
+             return -ENODEV;
+     }
+
+     info->cmu_regs = of_iomap(np, 0);
+     if (!info->cmu_regs) {
+             pr_err("%s: failed to map CMU registers\n", __func__);
+             return -EFAULT;
+     }
+

Don't replicate. Create a routine for all this..

Tomasz Figa

2014-05-21 12:11 UTC #14 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Hi Viresh,

Thanks for the review.

Quoted 11 lines · Viresh Kumar

On 21 May 2014 16:47, Tomasz Figa <[email protected]> wrote:
Mostly nitpicks ..
Quoted 5 lines
drivers/cpufreq/Kconfig.arm config ARM_EXYNOS4210_CPUFREQ · line 45
Quoted 5 lines
drivers/cpufreq/Kconfig.arm +1 -1
 config ARM_EXYNOS4X12_CPUFREQ
      bool "SAMSUNG EXYNOS4x12"
-     depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
+     depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
Get rid of () as well..

Right.

Quoted 12 lines

Quoted 10 lines
drivers/cpufreq/exynos-cpufreq.h struct exynos_dvfs_info { · line 53
Quoted 10 lines
drivers/cpufreq/exynos-cpufreq.h +1 -0
index a28ee9d..8dfebac 100644
@@ -50,6 +50,7 @@ struct exynos_dvfs_info {
      struct cpufreq_frequency_table  *freq_table;
      void (*set_freq)(unsigned int, unsigned int);
      bool (*need_apll_change)(unsigned int, unsigned int);
+     void __iomem    *cmu_regs;
s/tab/space ? before *cmu_regs ..

Other fields in this struct have their names aligned with a tab as well.

Quoted 9 lines

Quoted 7 lines
drivers/cpufreq/exynos4210-cpufreq.c int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) · line 163
Quoted 7 lines
drivers/cpufreq/exynos4210-cpufreq.c +1 -0
@@ -143,6 +160,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
      info->freq_table = exynos4210_freq_table;
      info->set_freq = exynos4210_set_frequency;
 
+     cpufreq = info;
I couldn't find this variable .. i.e. 'cpufreq'

It is a static global variable that is being added at the top of the file.

Quoted 12 lines

Quoted 12 lines
Quoted 12 lines
drivers/cpufreq/exynos4210-cpufreq.c +1 -0
+
      return 0;
 
 err_mout_apll:
drivers/cpufreq/exynos4x12-cpufreq.c +1 -0
 
 int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 {
+     struct device_node *np;
      unsigned long rate;

Quoted 16 lines

Quoted 5 lines

drivers/cpufreq/exynos4x12-cpufreq.c +5 -0

+     np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
+     if (!np) {
+             pr_err("%s: failed to find clock controller DT node\n",
+                     __func__);
+             return -ENODEV;

Quoted 8 lines

drivers/cpufreq/exynos4x12-cpufreq.c

Quoted 8 lines

drivers/cpufreq/exynos4x12-cpufreq.c +8 -0

+     }
+
+     info->cmu_regs = of_iomap(np, 0);
+     if (!info->cmu_regs) {
+             pr_err("%s: failed to map CMU registers\n", __func__);
+             return -EFAULT;
+     }
+

Don't replicate. Create a routine for all this..

While I agree that all three drivers basically use the same look-up and mapping code replicated, this patch is a temporary hack, until all those three drivers are completely removed, most likely in 3.17, so I would prefer doing this in the most ugly way, so that people don't follow this.

Still, I think a comment added before of_find_compatible_node() in each driver saying that this is a hack and why it is there would be nice, though.

Best regards,
Tomasz

Arnd Bergmann

2014-05-21 12:21 UTC #15 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

In reply to Tomasz Figa

Quoted 12 lines · On Wednesday 21 May 2014 13:12:32 Tomasz Figa wrote:

Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around.
This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support.
Signed-off-by Tomasz Figa <[email protected]>

Quoted 8 lines

---
 drivers/cpufreq/Kconfig.arm          |  6 +++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++++----------------
 drivers/cpufreq/exynos4210-cpufreq.c | 31 +++++++++++++++++++++++++------
 drivers/cpufreq/exynos4x12-cpufreq.c | 32 ++++++++++++++++++++++++++------
 drivers/cpufreq/exynos5250-cpufreq.c | 35 +++++++++++++++++++++++++++--------
 6 files changed, 95 insertions(+), 41 deletions(-)

Isn't this completely obsoleted by Thomas Abraham's work on cpufreq-cpu0 support in Exynos? I thought that was going to make it for 3.16.

Arnd

Tomasz Figa

2014-05-21 12:26 UTC #16 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 22 lines · Arnd Bergmann

Quoted 12 lines · On Wednesday 21 May 2014 13:12:32 Tomasz Figa wrote:
Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around.
This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support.
Signed-off-by Tomasz Figa <[email protected]>
Quoted 8 lines
---
 drivers/cpufreq/Kconfig.arm          |  6 +++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++++----------------
 drivers/cpufreq/exynos4210-cpufreq.c | 31 +++++++++++++++++++++++++------
 drivers/cpufreq/exynos4x12-cpufreq.c | 32 ++++++++++++++++++++++++++------
 drivers/cpufreq/exynos5250-cpufreq.c | 35 +++++++++++++++++++++++++++--------
 6 files changed, 95 insertions(+), 41 deletions(-)

Quoted 2 lines

Isn't this completely obsoleted by Thomas Abraham's work on cpufreq-cpu0 support in Exynos? I thought that was going to make it for 3.16.

That would be the best solution, but we need at least one more version of that series and I'm not sure if it isn't already too late to merge it for 3.16.

Best regards,
Tomasz

Thomas Abraham

2014-05-21 12:32 UTC #17 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 23 lines · Tomasz Figa

Quoted 22 lines · Arnd Bergmann
Quoted 20 lines · On Wednesday 21 May 2014 13:12:32 Tomasz Figa wrote:
Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around.
This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support.
Signed-off-by Tomasz Figa <[email protected]>
---
 drivers/cpufreq/Kconfig.arm          |  6 +++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++++----------------
 drivers/cpufreq/exynos4210-cpufreq.c | 31 +++++++++++++++++++++++++------
 drivers/cpufreq/exynos4x12-cpufreq.c | 32 ++++++++++++++++++++++++++------
 drivers/cpufreq/exynos5250-cpufreq.c | 35 +++++++++++++++++++++++++++--------
 6 files changed, 95 insertions(+), 41 deletions(-)

Quoted 6 lines

Quoted 2 lines
Isn't this completely obsoleted by Thomas Abraham's work on cpufreq-cpu0 support in Exynos? I thought that was going to make it for 3.16.
That would be the best solution, but we need at least one more version of that series and I'm not sure if it isn't already too late to merge it for 3.16.

I have addressed most the comments on the v4 patches. I will post v5 of the cpufreq consolidation patches a little later or early tomorrow.

Thanks,
Thomas.

Quoted 8 lines

Best regards,
Tomasz
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Kukjin Kim

2014-05-21 13:31 UTC #18 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 31 lines · Thomas Abraham

Quoted 13 lines · Tomasz Figa
Quoted 12 lines · Arnd Bergmann
Quoted 11 lines · On Wednesday 21 May 2014 13:12:32 Tomasz Figa wrote:
Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around.
This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support.
Quoted 6 lines
Quoted 6 lines
Quoted 6 lines
Signed-off-by Tomasz Figa <[email protected]>
---
 drivers/cpufreq/Kconfig.arm          |  6 +++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++++----------------
 drivers/cpufreq/exynos4210-cpufreq.c | 31 +++++++++++++++++++++++++----
--
Quoted 1 line
Quoted 1 line
Quoted 1 line
 drivers/cpufreq/exynos4x12-cpufreq.c | 32 ++++++++++++++++++++++++++---
---
Quoted 1 line
Quoted 1 line
Quoted 1 line
 drivers/cpufreq/exynos5250-cpufreq.c | 35 +++++++++++++++++++++++++++--
------
Quoted 5 lines
Quoted 4 lines
Quoted 1 line
 6 files changed, 95 insertions(+), 41 deletions(-)
Isn't this completely obsoleted by Thomas Abraham's work on cpufreq-cpu0 support in Exynos? I thought that was going to make it for 3.16.

Quoted 7 lines

Quoted 3 lines
That would be the best solution, but we need at least one more version of that series and I'm not sure if it isn't already too late to merge it for 3.16.
I have addressed most the comments on the v4 patches. I will post v5 of the cpufreq consolidation patches a little later or early tomorrow.

If there is no comments more on Thomas P Abraham's series v4 ;-), I will take that series in this time with ack from Viresh.

Rafael already agreed that exynos related cpufreq is handled in samsung tree with Viresh's ack.

Thanks,
Kukjin

Viresh Kumar

maintainer

2014-05-21 14:05 UTC #19 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 1 line · Kukjin Kim

If there is no comments more on Thomas P Abraham's series v4 ;-), I will take that series in this time with ack from Viresh.

@Thomas: Please post V5 quickly, let close it ASAP :)

Tomasz Figa

2014-05-23 14:52 UTC #20 lore raw

PATCH 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 5 lines · Viresh Kumar

Quoted 1 line · Kukjin Kim
If there is no comments more on Thomas P Abraham's series v4 ;-), I will take that series in this time with ack from Viresh.
@Thomas: Please post V5 quickly, let close it ASAP :)

Well, as far as I can see, the DT binding is not yet acked by DT maintainers, so IMHO the best solution for this release would be to apply my patch to avoid regression. New version with some of Viresh's comments addressed is on the way.

Best regards,
Tomasz

Tomasz Figa

2014-05-23 15:22 UTC #21 lore raw

PATCH v2 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

In reply to Tomasz Figa

Signed-off-by Tomasz Figa <[email protected]>

---
 drivers/cpufreq/Kconfig.arm          |  6 ++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++-------------
 drivers/cpufreq/exynos4210-cpufreq.c | 39 +++++++++++++++++++++++++++-----
 drivers/cpufreq/exynos4x12-cpufreq.c | 40 ++++++++++++++++++++++++++++-----
 drivers/cpufreq/exynos5250-cpufreq.c | 43 +++++++++++++++++++++++++++++-------
 6 files changed, 119 insertions(+), 41 deletions(-)

drivers/cpufreq/Kconfig.arm +3 -3

index 6a7dd3e..36d20d0 100644
@@ -31,7 +31,7 @@ config ARM_EXYNOS_CPUFREQ
 
 config ARM_EXYNOS4210_CPUFREQ
 	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210 && !ARCH_MULTIPLATFORM
+	depends on CPU_EXYNOS4210
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

@@ -42,7 +42,7 @@ config ARM_EXYNOS4210_CPUFREQ
 
 config ARM_EXYNOS4X12_CPUFREQ
 	bool "SAMSUNG EXYNOS4x12"
-	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
+	depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

@@ -53,7 +53,7 @@ config ARM_EXYNOS4X12_CPUFREQ
 
 config ARM_EXYNOS5250_CPUFREQ
 	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250 && !ARCH_MULTIPLATFORM
+	depends on SOC_EXYNOS5250
 	default y
 	select ARM_EXYNOS_CPUFREQ
 	help

drivers/cpufreq/exynos-cpufreq.c +0 -2

index 7c2a096..1e0ec57 100644
@@ -19,8 +19,6 @@
 #include <linux/platform_device.h>
 #include <linux/of.h>
 
-#include <plat/cpu.h>
-
 #include "exynos-cpufreq.h"
 
 static struct exynos_dvfs_info *exynos_info;

drivers/cpufreq/exynos-cpufreq.h +14 ~~-16~~

index a28ee9d..8dfebac 100644
@@ -50,6 +50,7 @@ struct exynos_dvfs_info {
 	struct cpufreq_frequency_table	*freq_table;
 	void (*set_freq)(unsigned int, unsigned int);
 	bool (*need_apll_change)(unsigned int, unsigned int);
+	void __iomem	*cmu_regs;
 };
 
 #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ

@@ -77,24 +78,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
 }
 #endif
 
-#include <plat/cpu.h>
-#include <mach/map.h>
+#define EXYNOS4_CLKSRC_CPU			0x14200
+#define EXYNOS4_CLKMUX_STATCPU			0x14400
 
-#define EXYNOS4_CLKSRC_CPU			(S5P_VA_CMU + 0x14200)
-#define EXYNOS4_CLKMUX_STATCPU			(S5P_VA_CMU + 0x14400)
-
-#define EXYNOS4_CLKDIV_CPU			(S5P_VA_CMU + 0x14500)
-#define EXYNOS4_CLKDIV_CPU1			(S5P_VA_CMU + 0x14504)
-#define EXYNOS4_CLKDIV_STATCPU			(S5P_VA_CMU + 0x14600)
-#define EXYNOS4_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x14604)
+#define EXYNOS4_CLKDIV_CPU			0x14500
+#define EXYNOS4_CLKDIV_CPU1			0x14504
+#define EXYNOS4_CLKDIV_STATCPU			0x14600
+#define EXYNOS4_CLKDIV_STATCPU1			0x14604
 
 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT	(16)
 #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
 
-#define EXYNOS5_APLL_LOCK			(S5P_VA_CMU + 0x00000)
-#define EXYNOS5_APLL_CON0			(S5P_VA_CMU + 0x00100)
-#define EXYNOS5_CLKMUX_STATCPU			(S5P_VA_CMU + 0x00400)
-#define EXYNOS5_CLKDIV_CPU0			(S5P_VA_CMU + 0x00500)
-#define EXYNOS5_CLKDIV_CPU1			(S5P_VA_CMU + 0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0			(S5P_VA_CMU + 0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x00604)
+#define EXYNOS5_APLL_LOCK			0x00000
+#define EXYNOS5_APLL_CON0			0x00100
+#define EXYNOS5_CLKMUX_STATCPU			0x00400
+#define EXYNOS5_CLKDIV_CPU0			0x00500
+#define EXYNOS5_CLKDIV_CPU1			0x00504
+#define EXYNOS5_CLKDIV_STATCPU0			0x00600
+#define EXYNOS5_CLKDIV_STATCPU1			0x00604

drivers/cpufreq/exynos4210-cpufreq.c +33 -6

index 6384e5b..61a5431 100644
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos4210_volt_table[] = {
 	1250000, 1150000, 1050000, 975000, 950000,

@@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_4210[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
 	} while (tmp & 0x1111111);
 
 	/* Change Divider - CPU1 */
 
 	tmp = apll_freq_4210[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
 	} while (tmp & 0x11);
 }

@@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index)
 	clk_set_parent(moutcore, mout_mpll);
 
 	do {
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
 			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index)
 	clk_set_parent(moutcore, mout_apll);
 
 	do {
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
 		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 }

@@ -115,8 +118,30 @@ static void exynos4210_set_frequency(unsigned int old_index,
 
 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	/*
+	 * HACK: This is a temporary workaround to get access to clock
+	 * controller registers directly and remove static mappings and
+	 * dependencies on platform headers. It is necessary to enable
+	 * Exynos multi-platform support and will be removed together with
+	 * this whole driver as soon as Exynos gets migrated to use
+	 * cpufreq-cpu0 driver.
+	 */
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -143,6 +168,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos4210_freq_table;
 	info->set_freq = exynos4210_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

drivers/cpufreq/exynos4x12-cpufreq.c +34 -6

index 63a3907..351a207 100644
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos4x12_volt_table[] = {
 	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,

@@ -105,19 +108,20 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
 
 	tmp = apll_freq_4x12[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
-	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
+	       & 0x11111111)
 		cpu_relax();
 
 	/* Change Divider - CPU1 */
 	tmp = apll_freq_4x12[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
 	} while (tmp != 0x0);
 }

@@ -130,7 +134,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
 			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 		tmp &= 0x7;
 	} while (tmp != 0x2);

@@ -142,7 +146,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
 	do {
 		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
 		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 }

@@ -161,8 +165,30 @@ static void exynos4x12_set_frequency(unsigned int old_index,
 
 int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 {
+	struct device_node *np;
 	unsigned long rate;
 
+	/*
+	 * HACK: This is a temporary workaround to get access to clock
+	 * controller registers directly and remove static mappings and
+	 * dependencies on platform headers. It is necessary to enable
+	 * Exynos multi-platform support and will be removed together with
+	 * this whole driver as soon as Exynos gets migrated to use
+	 * cpufreq-cpu0 driver.
+	 */
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
 	cpu_clk = clk_get(NULL, "armclk");
 	if (IS_ERR(cpu_clk))
 		return PTR_ERR(cpu_clk);

@@ -194,6 +220,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
 	info->freq_table = exynos4x12_freq_table;
 	info->set_freq = exynos4x12_set_frequency;
 
+	cpufreq = info;
+
 	return 0;
 
 err_mout_apll:

drivers/cpufreq/exynos5250-cpufreq.c +35 -8

94 lines not on this page · raw message

Signature · 1 line

1.9.3

Kukjin Kim

2014-05-25 21:41 UTC #22 lore raw

PATCH v2 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 12 lines · Tomasz Figa

Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around.
This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support.
Signed-off-by Tomasz Figa<[email protected]>

Quoted 9 lines

---
  drivers/cpufreq/Kconfig.arm          |  6 ++---
  drivers/cpufreq/exynos-cpufreq.c     |  2 --
  drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++-------------
  drivers/cpufreq/exynos4210-cpufreq.c | 39 +++++++++++++++++++++++++++-----
  drivers/cpufreq/exynos4x12-cpufreq.c | 40 ++++++++++++++++++++++++++++-----
  drivers/cpufreq/exynos5250-cpufreq.c | 43 +++++++++++++++++++++++++++++-------
  6 files changed, 119 insertions(+), 41 deletions(-)

Viresh,

I'm not sure Thomas' v5 cpufreq-cpu0 driver can be upstreamed for 3.16 because of dependency with others, some of them got ack though...

* "PM / OPP: move cpufreq specific helpers out of OPP layer"
- https://www.mail-archive.com/linux-omap at vger.kernel.org/msg104610.html
* "cpufreq: opp: Add device tree based lookup of boost mode frequency"
- http://www.spinics.net/lists/arm-kernel/msg334336.html

So firstly, I've queued this instead with exynos-multiplatform series...

How do you think?

- Kukjin

Quoted 407 lines

drivers/cpufreq/Kconfig.arm +3 -3

index 6a7dd3e..36d20d0 100644
@@ -31,7 +31,7 @@ config ARM_EXYNOS_CPUFREQ
 
  config ARM_EXYNOS4210_CPUFREQ
  	bool "SAMSUNG EXYNOS4210"
-	depends on CPU_EXYNOS4210&&  !ARCH_MULTIPLATFORM
+	depends on CPU_EXYNOS4210
  	default y
  	select ARM_EXYNOS_CPUFREQ
  	help

@@ -42,7 +42,7 @@ config ARM_EXYNOS4210_CPUFREQ
 
  config ARM_EXYNOS4X12_CPUFREQ
  	bool "SAMSUNG EXYNOS4x12"
-	depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)&&  !ARCH_MULTIPLATFORM
+	depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
  	default y
  	select ARM_EXYNOS_CPUFREQ
  	help

@@ -53,7 +53,7 @@ config ARM_EXYNOS4X12_CPUFREQ
 
  config ARM_EXYNOS5250_CPUFREQ
  	bool "SAMSUNG EXYNOS5250"
-	depends on SOC_EXYNOS5250&&  !ARCH_MULTIPLATFORM
+	depends on SOC_EXYNOS5250
  	default y
  	select ARM_EXYNOS_CPUFREQ
  	help

drivers/cpufreq/exynos-cpufreq.c +0 -2

index 7c2a096..1e0ec57 100644
@@ -19,8 +19,6 @@
  #include<linux/platform_device.h>
  #include<linux/of.h>
 
-#include<plat/cpu.h>
-
  #include "exynos-cpufreq.h"
 
  static struct exynos_dvfs_info *exynos_info;

drivers/cpufreq/exynos-cpufreq.h +14 ~~-16~~

index a28ee9d..8dfebac 100644
@@ -50,6 +50,7 @@ struct exynos_dvfs_info {
  	struct cpufreq_frequency_table	*freq_table;
  	void (*set_freq)(unsigned int, unsigned int);
  	bool (*need_apll_change)(unsigned int, unsigned int);
+	void __iomem	*cmu_regs;
  };
 
  #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ

@@ -77,24 +78,21 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
  }
  #endif
 
-#include<plat/cpu.h>
-#include<mach/map.h>
+#define EXYNOS4_CLKSRC_CPU			0x14200
+#define EXYNOS4_CLKMUX_STATCPU			0x14400
 
-#define EXYNOS4_CLKSRC_CPU			(S5P_VA_CMU + 0x14200)
-#define EXYNOS4_CLKMUX_STATCPU			(S5P_VA_CMU + 0x14400)
-
-#define EXYNOS4_CLKDIV_CPU			(S5P_VA_CMU + 0x14500)
-#define EXYNOS4_CLKDIV_CPU1			(S5P_VA_CMU + 0x14504)
-#define EXYNOS4_CLKDIV_STATCPU			(S5P_VA_CMU + 0x14600)
-#define EXYNOS4_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x14604)
+#define EXYNOS4_CLKDIV_CPU			0x14500
+#define EXYNOS4_CLKDIV_CPU1			0x14504
+#define EXYNOS4_CLKDIV_STATCPU			0x14600
+#define EXYNOS4_CLKDIV_STATCPU1			0x14604
 
  #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT	(16)
  #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK	(0x7<<  EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
 
-#define EXYNOS5_APLL_LOCK			(S5P_VA_CMU + 0x00000)
-#define EXYNOS5_APLL_CON0			(S5P_VA_CMU + 0x00100)
-#define EXYNOS5_CLKMUX_STATCPU			(S5P_VA_CMU + 0x00400)
-#define EXYNOS5_CLKDIV_CPU0			(S5P_VA_CMU + 0x00500)
-#define EXYNOS5_CLKDIV_CPU1			(S5P_VA_CMU + 0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0			(S5P_VA_CMU + 0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1			(S5P_VA_CMU + 0x00604)
+#define EXYNOS5_APLL_LOCK			0x00000
+#define EXYNOS5_APLL_CON0			0x00100
+#define EXYNOS5_CLKMUX_STATCPU			0x00400
+#define EXYNOS5_CLKDIV_CPU0			0x00500
+#define EXYNOS5_CLKDIV_CPU1			0x00504
+#define EXYNOS5_CLKDIV_STATCPU0			0x00600
+#define EXYNOS5_CLKDIV_STATCPU1			0x00604

drivers/cpufreq/exynos4210-cpufreq.c +33 -6

index 6384e5b..61a5431 100644
@@ -16,6 +16,8 @@
  #include<linux/io.h>
  #include<linux/slab.h>
  #include<linux/cpufreq.h>
+#include<linux/of.h>
+#include<linux/of_address.h>
 
  #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
  static struct clk *moutcore;
  static struct clk *mout_mpll;
  static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
  static unsigned int exynos4210_volt_table[] = {
  	1250000, 1150000, 1050000, 975000, 950000,

@@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
 
  	tmp = apll_freq_4210[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
  	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
  	} while (tmp&  0x1111111);
 
  	/* Change Divider - CPU1 */
 
  	tmp = apll_freq_4210[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
  	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
  	} while (tmp&  0x11);
  }

@@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index)
  	clk_set_parent(moutcore, mout_mpll);
 
  	do {
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
  			>>  EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
  		tmp&= 0x7;
  	} while (tmp != 0x2);

@@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index)
  	clk_set_parent(moutcore, mout_apll);
 
  	do {
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
  		tmp&= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
  	} while (tmp != (0x1<<  EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
  }

@@ -115,8 +118,30 @@ static void exynos4210_set_frequency(unsigned int old_index,
 
  int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
  {
+	struct device_node *np;
  	unsigned long rate;
 
+	/*
+	 * HACK: This is a temporary workaround to get access to clock
+	 * controller registers directly and remove static mappings and
+	 * dependencies on platform headers. It is necessary to enable
+	 * Exynos multi-platform support and will be removed together with
+	 * this whole driver as soon as Exynos gets migrated to use
+	 * cpufreq-cpu0 driver.
+	 */
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
  	cpu_clk = clk_get(NULL, "armclk");
  	if (IS_ERR(cpu_clk))
  		return PTR_ERR(cpu_clk);

@@ -143,6 +168,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
  	info->freq_table = exynos4210_freq_table;
  	info->set_freq = exynos4210_set_frequency;
 
+	cpufreq = info;
+
  	return 0;
 
  err_mout_apll:

drivers/cpufreq/exynos4x12-cpufreq.c +34 -6

index 63a3907..351a207 100644
@@ -16,6 +16,8 @@
  #include<linux/io.h>
  #include<linux/slab.h>
  #include<linux/cpufreq.h>
+#include<linux/of.h>
+#include<linux/of_address.h>
 
  #include "exynos-cpufreq.h"

@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
  static struct clk *moutcore;
  static struct clk *mout_mpll;
  static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
  static unsigned int exynos4x12_volt_table[] = {
  	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,

@@ -105,19 +108,20 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
 
  	tmp = apll_freq_4x12[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
-	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU)&  0x11111111)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
+	&  0x11111111)
  		cpu_relax();
 
  	/* Change Divider - CPU1 */
  	tmp = apll_freq_4x12[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
  	do {
  		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
  	} while (tmp != 0x0);
  }

@@ -130,7 +134,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
  	do {
  		cpu_relax();
-		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
  			>>  EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
  		tmp&= 0x7;
  	} while (tmp != 0x2);

@@ -142,7 +146,7 @@ static void exynos4x12_set_apll(unsigned int index)
 
  	do {
  		cpu_relax();
-		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
  		tmp&= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
  	} while (tmp != (0x1<<  EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
  }

@@ -161,8 +165,30 @@ static void exynos4x12_set_frequency(unsigned int old_index,
 
  int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
  {
+	struct device_node *np;
  	unsigned long rate;
 
+	/*
+	 * HACK: This is a temporary workaround to get access to clock
+	 * controller registers directly and remove static mappings and
+	 * dependencies on platform headers. It is necessary to enable
+	 * Exynos multi-platform support and will be removed together with
+	 * this whole driver as soon as Exynos gets migrated to use
+	 * cpufreq-cpu0 driver.
+	 */
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
  	cpu_clk = clk_get(NULL, "armclk");
  	if (IS_ERR(cpu_clk))
  		return PTR_ERR(cpu_clk);

@@ -194,6 +220,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
  	info->freq_table = exynos4x12_freq_table;
  	info->set_freq = exynos4x12_set_frequency;
 
+	cpufreq = info;
+
  	return 0;
 
  err_mout_apll:

drivers/cpufreq/exynos5250-cpufreq.c +35 -8

index 363a0b3..c91ce69 100644
@@ -16,8 +16,8 @@
  #include<linux/io.h>
  #include<linux/slab.h>
  #include<linux/cpufreq.h>
-
-#include<mach/map.h>
+#include<linux/of.h>
+#include<linux/of_address.h>
 
  #include "exynos-cpufreq.h"

@@ -25,6 +25,7 @@ static struct clk *cpu_clk;
  static struct clk *moutcore;
  static struct clk *mout_mpll;
  static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
  static unsigned int exynos5250_volt_table[] = {
  	1300000, 1250000, 1225000, 1200000, 1150000,

@@ -87,17 +88,18 @@ static void set_clkdiv(unsigned int div_index)
 
  	tmp = apll_freq_5250[div_index].clk_div_cpu0;
 
-	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
 
-	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0)&  0x11111111)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
+	&  0x11111111)
  		cpu_relax();
 
  	/* Change Divider - CPU1 */
  	tmp = apll_freq_5250[div_index].clk_div_cpu1;
 
-	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
+	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
 
-	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1)&  0x11)
+	while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1)&  0x11)
  		cpu_relax();
  }

@@ -111,7 +113,8 @@ static void set_apll(unsigned int index)
 
  	do {
  		cpu_relax();
-		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU)>>  16);
+		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
+			>>  16);
  		tmp&= 0x7;
  	} while (tmp != 0x2);

@@ -122,7 +125,7 @@ static void set_apll(unsigned int index)
 
  	do {
  		cpu_relax();
-		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
+		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
  		tmp&= (0x7<<  16);
  	} while (tmp != (0x1<<  16));
  }

@@ -141,8 +144,30 @@ static void exynos5250_set_frequency(unsigned int old_index,
 
  int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
  {
+	struct device_node *np;
  	unsigned long rate;
 
+	/*
+	 * HACK: This is a temporary workaround to get access to clock
+	 * controller registers directly and remove static mappings and
+	 * dependencies on platform headers. It is necessary to enable
+	 * Exynos multi-platform support and will be removed together with
+	 * this whole driver as soon as Exynos gets migrated to use
+	 * cpufreq-cpu0 driver.
+	 */
+	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
+	if (!np) {
+		pr_err("%s: failed to find clock controller DT node\n",
+			__func__);
+		return -ENODEV;
+	}
+
+	info->cmu_regs = of_iomap(np, 0);
+	if (!info->cmu_regs) {
+		pr_err("%s: failed to map CMU registers\n", __func__);
+		return -EFAULT;
+	}
+
  	cpu_clk = clk_get(NULL, "armclk");
  	if (IS_ERR(cpu_clk))
  		return PTR_ERR(cpu_clk);

@@ -169,6 +194,8 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
  	info->freq_table = exynos5250_freq_table;
  	info->set_freq = exynos5250_set_frequency;
 
+	cpufreq = info;
+
  	return 0;
 
  err_mout_apll:

Signature · 7 lines

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

Viresh Kumar

maintainer

2014-05-26 05:40 UTC #23 lore raw

PATCH v2 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 5 lines · Kukjin Kim

I'm not sure Thomas' v5 cpufreq-cpu0 driver can be upstreamed for 3.16 because of dependency with others, some of them got ack though...
* "PM / OPP: move cpufreq specific helpers out of OPP layer"
- https://www.mail-archive.com/linux-omap at vger.kernel.org/msg104610.html

This is already lying in Rafael's tree.

Quoted 6 lines

* "cpufreq: opp: Add device tree based lookup of boost mode frequency"
- http://www.spinics.net/lists/arm-kernel/msg334336.html
So firstly, I've queued this instead with exynos-multiplatform series...
How do you think?

Looks fine to me. Thanks.

Kukjin Kim

2014-05-26 22:06 UTC #24 lore raw

PATCH v2 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

Quoted 9 lines · Viresh Kumar

Quoted 5 lines · Kukjin Kim
I'm not sure Thomas' v5 cpufreq-cpu0 driver can be upstreamed for 3.16 because of dependency with others, some of them got ack though...
* "PM / OPP: move cpufreq specific helpers out of OPP layer"
- https://www.mail-archive.com/linux-omap at vger.kernel.org/msg104610.html
This is already lying in Rafael's tree.

Good.

Quoted 3 lines

Quoted 3 lines
* "cpufreq: opp: Add device tree based lookup of boost mode frequency"
- http://www.spinics.net/lists/arm-kernel/msg334336.html

Probably need more time?

Quoted 5 lines

Quoted 3 lines
So firstly, I've queued this instead with exynos-multiplatform series...
How do you think?
Looks fine to me. Thanks.

OK, I applied with your ack.

Thanks,
- Kukjin

Viresh Kumar

maintainer

2014-05-26 05:40 UTC #25 lore raw

PATCH v2 1/1 cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM

In reply to Tomasz Figa

Quoted 12 lines · Tomasz Figa

Currently Exynos cpufreq drivers rely on globally mapped clock controller registers to configure frequency of CPU cores. This is obviously wrong and will be removed in near future, but to enable support for multi-platform builds without introducing a regression it needs to be worked around.
This patch hacks the code to look for clock controller node in device tree and map its registers using of_iomap(), instead of relying on global mapping, so dependencies on platform headers are removed and the driver can compile again with multiplatform support.
Signed-off-by Tomasz Figa <[email protected]>

Quoted 8 lines

---
 drivers/cpufreq/Kconfig.arm          |  6 ++---
 drivers/cpufreq/exynos-cpufreq.c     |  2 --
 drivers/cpufreq/exynos-cpufreq.h     | 30 ++++++++++++-------------
 drivers/cpufreq/exynos4210-cpufreq.c | 39 +++++++++++++++++++++++++++-----
 drivers/cpufreq/exynos4x12-cpufreq.c | 40 ++++++++++++++++++++++++++++-----
 drivers/cpufreq/exynos5250-cpufreq.c | 43 +++++++++++++++++++++++++++++-------
 6 files changed, 119 insertions(+), 41 deletions(-)

Looks fine..

Acked-by Viresh Kumar <[email protected]>