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ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk

PATCH New Tomi Valkeinen 2 participants 3 messages May 21, 2014 – May 23, 2014 Device tree bindings

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#0 lore raw

PATCH 1/2 ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk

Add ti,set-rate-parent to dss_dss_clk so that the DSS driver can set the rate.

---
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 1 +
 1 file changed, 1 insertion(+)
arch/arm/boot/dts/omap54xx-clocks.dtsi +1 -0
index d487fdab3921..d44bdaa8fe68 100644
@@ -851,6 +851,7 @@
 		clocks = <&dpll_per_h12x2_ck>;
 		ti,bit-shift = <8>;
 		reg = <0x1420>;
+		ti,set-rate-parent;
 	};
 
 	dss_sys_clk: dss_sys_clk {
Signature · 1 line
1.9.1
#1 lore raw

PATCH 2/2 ARM: dts: am43xx-clocks.dtsi: add ti, set-rate-parent to display clock path

We need set-rate-parent flags for the display's clock path so that the DSS driver can change the clock rate of the PLL.

This patchs adds the ti,set-rate-parent flag to disp_clk and dpll_disp_m2_ck clock nodes.

---
 arch/arm/boot/dts/am43xx-clocks.dtsi | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/boot/dts/am43xx-clocks.dtsi +2 -0
index 142009cc9332..a6f7ee74990f 100644
@@ -229,6 +229,7 @@
 		reg = <0x2e30>;
 		ti,index-starts-at-one;
 		ti,invert-autoidle-bit;
+		ti,set-rate-parent;
 	};
 
 	dpll_per_ck: dpll_per_ck {
@@ -511,6 +512,7 @@
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
 		reg = <0x4244>;
+		ti,set-rate-parent;
 	};
 
 	dpll_extdev_ck: dpll_extdev_ck {
Signature · 1 line
1.9.1
#2 lore raw

PATCH 1/2 ARM: dts: omap5-clocks.dtsi: add ti,set-rate-parent to dss_dss_clk

In reply to Tomi Valkeinen
Quoted 4 lines · Tomi Valkeinen

Add ti,set-rate-parent to dss_dss_clk so that the DSS driver can set the rate.

Both patches queued for 3.16, thanks.

-Tero

Quoted 17 lines
---
  arch/arm/boot/dts/omap54xx-clocks.dtsi | 1 +
  1 file changed, 1 insertion(+)
arch/arm/boot/dts/omap54xx-clocks.dtsi +1 -0
index d487fdab3921..d44bdaa8fe68 100644
@@ -851,6 +851,7 @@
  		clocks = <&dpll_per_h12x2_ck>;
  		ti,bit-shift = <8>;
  		reg = <0x1420>;
+		ti,set-rate-parent;
  	};
 
  	dss_sys_clk: dss_sys_clk {