ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk
PATCH 1/2 ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk
Add ti,set-rate-parent to dss_dss_clk so that the DSS driver can set the rate.
Signed-off-by Tomi Valkeinen <[email protected]>
--- arch/arm/boot/dts/omap54xx-clocks.dtsi | 1 + 1 file changed, 1 insertion(+)
arch/arm/boot/dts/omap54xx-clocks.dtsi +1 -0
@@ -851,6 +851,7 @@ clocks = <&dpll_per_h12x2_ck>; ti,bit-shift = <8>; reg = <0x1420>; + ti,set-rate-parent; }; dss_sys_clk: dss_sys_clk {
Signature · 1 line
1.9.1
PATCH 2/2 ARM: dts: am43xx-clocks.dtsi: add ti, set-rate-parent to display clock path
We need set-rate-parent flags for the display's clock path so that the DSS driver can change the clock rate of the PLL.
This patchs adds the ti,set-rate-parent flag to disp_clk and dpll_disp_m2_ck clock nodes.
Signed-off-by Tomi Valkeinen <[email protected]>
--- arch/arm/boot/dts/am43xx-clocks.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/am43xx-clocks.dtsi +2 -0
@@ -229,6 +229,7 @@ reg = <0x2e30>; ti,index-starts-at-one; ti,invert-autoidle-bit; + ti,set-rate-parent; }; dpll_per_ck: dpll_per_ck {
@@ -511,6 +512,7 @@ compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x4244>; + ti,set-rate-parent; }; dpll_extdev_ck: dpll_extdev_ck {
Signature · 1 line
1.9.1
PATCH 1/2 ARM: dts: omap5-clocks.dtsi: add ti,set-rate-parent to dss_dss_clk
In reply to Tomi ValkeinenQuoted 4 lines · Tomi Valkeinen
Add ti,set-rate-parent to
dss_dss_clkso that the DSS driver can set the rate.Signed-off-by Tomi Valkeinen <[email protected]>
Both patches queued for 3.16, thanks.
-Tero
Quoted 17 lines
--- arch/arm/boot/dts/omap54xx-clocks.dtsi | 1 + 1 file changed, 1 insertion(+)arch/arm/boot/dts/omap54xx-clocks.dtsi +1
-0@@ -851,6 +851,7 @@ clocks = <&dpll_per_h12x2_ck>; ti,bit-shift = <8>; reg = <0x1420>; + ti,set-rate-parent; }; dss_sys_clk: dss_sys_clk {